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pcsx2
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Finish previous revert as TortoiseGit failed epicly at it.

This commit is contained in:
refractionpcsx2 2015-06-10 10:11:06 +01:00
parent cbcb7962ce
commit 72b828ef0d
2 changed files with 39 additions and 11 deletions
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30
pcsx2/MMI.cpp
View File

@ -16,7 +16,6 @@
#include "PrecompiledHeader.h"
#include "Common.h"
#include "Utilities/Math.h"
namespace R5900 {
namespace Interpreter {
@ -146,13 +145,30 @@ namespace MMI {
//*****************MMI OPCODES*********************************
void PLZCW() {
if (!_Rd_)
return;
static __fi void _PLZCW(int n)
{
// This function counts the number of "like" bits in the source register, starting
// with the MSB and working its way down, and returns the result MINUS ONE.
// So 0xff00 would return 7, not 8.
// Return the leading sign bits, excluding the original bit
cpuRegs.GPR.r[_Rd_].UL[0] = count_leading_sign_bits(cpuRegs.GPR.r[_Rs_].SL[0]) - 1;
cpuRegs.GPR.r[_Rd_].UL[1] = count_leading_sign_bits(cpuRegs.GPR.r[_Rs_].SL[1]) - 1;
int c = 0;
s32 i = cpuRegs.GPR.r[_Rs_].SL[n];
// Negate the source based on the sign bit. This allows us to use a simple
// unified bit test of the MSB for either condition.
if( i >= 0 ) i = ~i;
// shift first, compare, then increment. This excludes the sign bit from our final count.
while( i <<= 1, i < 0 ) c++;
cpuRegs.GPR.r[_Rd_].UL[n] = c;
}
void PLZCW() {
if (!_Rd_) return;
_PLZCW (0);
_PLZCW (1);
}
__fi void PMFHL_CLAMP(u16& dst, s32 src)

20
pcsx2/x86/iMMI.cpp
View File

@ -25,7 +25,6 @@
#include "R5900OpcodeTables.h"
#include "iR5900.h"
#include "iMMI.h"
#include "Utilities/Math.h"
using namespace x86Emitter;
@ -67,10 +66,23 @@ void recPLZCW()
_deleteEEreg(_Rd_, 0);
GPR_SET_CONST(_Rd_);
// Return the leading sign bits, excluding the original bit
g_cpuConstRegs[_Rd_].UL[0] = count_leading_sign_bits(g_cpuConstRegs[_Rs_].SL[0]) - 1;
g_cpuConstRegs[_Rd_].UL[1] = count_leading_sign_bits(g_cpuConstRegs[_Rs_].SL[1]) - 1;
for(regs = 0; regs < 2; ++regs) {
u32 val = g_cpuConstRegs[_Rs_].UL[regs];
if( val != 0 ) {
u32 setbit = val&0x80000000;
g_cpuConstRegs[_Rd_].UL[regs] = 0;
val <<= 1;
while((val & 0x80000000) == setbit) {
g_cpuConstRegs[_Rd_].UL[regs]++;
val <<= 1;
}
}
else {
g_cpuConstRegs[_Rd_].UL[regs] = 31;
}
}
return;
}