diff --git a/3rdparty/cpuinfo/include/cpuinfo.h b/3rdparty/cpuinfo/include/cpuinfo.h
index 387611cc9b..6eb4b8c38e 100644
--- a/3rdparty/cpuinfo/include/cpuinfo.h
+++ b/3rdparty/cpuinfo/include/cpuinfo.h
@@ -419,6 +419,8 @@ enum cpuinfo_uarch {
 	cpuinfo_uarch_zen3 = 0x0020010B,
 	/** AMD Zen 4 microarchitecture. */
 	cpuinfo_uarch_zen4 = 0x0020010C,
+	/** AMD Zen 5 microarchitecture. */
+	cpuinfo_uarch_zen5 = 0x0020010D,
 
 	/** NSC Geode and AMD Geode GX and LX. */
 	cpuinfo_uarch_geode = 0x00200200,
@@ -818,6 +820,7 @@ struct cpuinfo_x86_isa {
 	bool avx512vp2intersect;
 	bool avx512_4vnniw;
 	bool avx512_4fmaps;
+	bool avx10_1;
 	bool amx_bf16;
 	bool amx_tile;
 	bool amx_int8;
@@ -1433,6 +1436,14 @@ static inline bool cpuinfo_has_x86_avx_ne_convert(void) {
 #endif
 }
 
+static inline bool cpuinfo_has_x86_avx10_1(void) {
+#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
+	return cpuinfo_isa.avx10_1;
+#else
+	return false;
+#endif
+}
+
 static inline bool cpuinfo_has_x86_hle(void) {
 #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
 	return cpuinfo_isa.hle;
diff --git a/3rdparty/cpuinfo/src/arm/cache.c b/3rdparty/cpuinfo/src/arm/cache.c
index dd19919311..97740c4372 100644
--- a/3rdparty/cpuinfo/src/arm/cache.c
+++ b/3rdparty/cpuinfo/src/arm/cache.c
@@ -1341,7 +1341,8 @@ void cpuinfo_arm_decode_cache(
 			 * information, please refer to the technical manuals
 			 * linked above
 			 */
-			const uint32_t min_l2_size_KB = uarch == cpuinfo_uarch_neoverse_v2 ? 1024 : 256;
+			const uint32_t min_l2_size_KB =
+				(uarch == cpuinfo_uarch_neoverse_v2 || midr_is_ampere_altra(midr)) ? 1024 : 256;
 			const uint32_t min_l3_size_KB = 0;
 
 			*l1i = (struct cpuinfo_cache){
diff --git a/3rdparty/cpuinfo/src/arm/midr.h b/3rdparty/cpuinfo/src/arm/midr.h
index 89ebbb5836..5530d5a996 100644
--- a/3rdparty/cpuinfo/src/arm/midr.h
+++ b/3rdparty/cpuinfo/src/arm/midr.h
@@ -34,6 +34,7 @@
 #define CPUINFO_ARM_MIDR_KRYO_SILVER_820 UINT32_C(0x510F2110)
 #define CPUINFO_ARM_MIDR_EXYNOS_M1_M2 UINT32_C(0x530F0010)
 #define CPUINFO_ARM_MIDR_DENVER2 UINT32_C(0x4E0F0030)
+#define CPUINFO_ARM_MIDR_AMPERE_ALTRA UINT32_C(0x413fd0c1)
 
 inline static uint32_t midr_set_implementer(uint32_t midr, uint32_t implementer) {
 	return (midr & ~CPUINFO_ARM_MIDR_IMPLEMENTER_MASK) |
@@ -167,6 +168,11 @@ inline static bool midr_is_kryo_gold(uint32_t midr) {
 	return (midr & uarch_mask) == (CPUINFO_ARM_MIDR_KRYO_GOLD & uarch_mask);
 }
 
+inline static bool midr_is_ampere_altra(uint32_t midr) {
+	const uint32_t uarch_mask = CPUINFO_ARM_MIDR_IMPLEMENTER_MASK | CPUINFO_ARM_MIDR_PART_MASK;
+	return (midr & uarch_mask) == (CPUINFO_ARM_MIDR_AMPERE_ALTRA & uarch_mask);
+}
+
 inline static uint32_t midr_score_core(uint32_t midr) {
 	const uint32_t core_mask = CPUINFO_ARM_MIDR_IMPLEMENTER_MASK | CPUINFO_ARM_MIDR_PART_MASK;
 	switch (midr & core_mask) {
diff --git a/3rdparty/cpuinfo/src/x86/isa.c b/3rdparty/cpuinfo/src/x86/isa.c
index bfd5e776b1..47a6afa320 100644
--- a/3rdparty/cpuinfo/src/x86/isa.c
+++ b/3rdparty/cpuinfo/src/x86/isa.c
@@ -429,6 +429,11 @@ struct cpuinfo_x86_isa cpuinfo_x86_detect_isa(
 	 */
 	isa.avx512f = avx512_regs && !!(structured_feature_info0.ebx & UINT32_C(0x00010000));
 
+	/*
+	 * AVX 10.1 instructions:
+	 */
+	isa.avx10_1 = avx512_regs && !!(structured_feature_info1.edx & UINT32_C(0x00080000));
+
 	/*
 	 * AVX512PF instructions:
 	 * - Intel: ebx[bit 26] in structured feature info (ecx = 0).
diff --git a/3rdparty/cpuinfo/src/x86/uarch.c b/3rdparty/cpuinfo/src/x86/uarch.c
index b291ebcf0c..a21eabb0a0 100644
--- a/3rdparty/cpuinfo/src/x86/uarch.c
+++ b/3rdparty/cpuinfo/src/x86/uarch.c
@@ -387,6 +387,8 @@ enum cpuinfo_uarch cpuinfo_x86_decode_uarch(
 							return cpuinfo_uarch_zen4;
 					}
 					break;
+				case 0x1a:
+					return cpuinfo_uarch_zen5;
 			}
 			break;
 		case cpuinfo_vendor_hygon: