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PCSX2: 

- Fix SPR interrupts to a delay of 4 cycles always. Makes sure they're handled first.
(Fixes Obscure2 and Alone in the Dark FMV.)
GSdx:
- One more CRC :p

git-svn-id: http://pcsx2.googlecode.com/svn/trunk@2584 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
ramapcsx2 2010-02-10 18:44:58 +00:00
parent 9906e82efc
commit 706c68c1cd
4 changed files with 12 additions and 9 deletions
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6
pcsx2/R5900.cpp
View File

@ -428,9 +428,11 @@ __forceinline void _cpuBranchTest_Shared()
// We're in a BranchTest. All dynarec registers are flushed
// so there is no need to freeze registers here.
CpuVU0->ExecuteBlock();
DevCon.Warning("VU0 running when in BranchTest");
// This might be needed to keep the EE and VU0 in sync.
// A better fix will require hefty changes to the VU recs. -_-
// Fixme:
// Check Silver Surfer. Currently has SPS varying with different branch deltas set below.
if(VU0.VI[REG_VPU_STAT].UL & 0x1)
cpuSetNextBranchDelta( 768 );
}
@ -559,4 +561,4 @@ __forceinline void CPU_INT( u32 n, s32 ecycle)
}
cpuSetNextBranchDelta( cpuRegs.eCycle[n] );
}
}

12
pcsx2/SPR.cpp
View File

@ -202,7 +202,7 @@ static __forceinline void _dmaSPR0()
if (!done)
{
ptag = (tDMA_TAG*)&psSu32(spr0->sadr); //Set memory pointer to SADR
CPU_INT(DMAC_FROM_SPR, ptag[0].QWC / BIAS); // the lower 16bits of the tag / BIAS);
CPU_INT(DMAC_FROM_SPR, /*ptag[0].QWC / BIAS*/ 4 ); // the lower 16bits of the tag / BIAS);
return;
}
SPR_LOG("spr0 dmaChain complete %8.8x_%8.8x size=%d, id=%d, addr=%lx spr=%lx",
@ -264,13 +264,13 @@ void dmaSPR0() // fromSPR
{
tDMA_TAG *ptag;
ptag = (tDMA_TAG*)&psSu32(spr0->sadr); //Set memory pointer to SADR
CPU_INT(DMAC_FROM_SPR, ptag[0].QWC / BIAS);
CPU_INT(DMAC_FROM_SPR, /*ptag[0].QWC / BIAS*/ 4 );
return;
}
// COMPLETE HACK!!! For now at least.. FFX Videos dont rely on interrupts or reading DMA values
// It merely assumes that the last one has finished then starts another one (broke with the DMA fix)
// This "shouldn't" cause any problems as SPR is generally faster than the other DMAS anyway. (Refraction)
CPU_INT(DMAC_FROM_SPR, spr0->qwc / BIAS);
CPU_INT(DMAC_FROM_SPR, /*spr0->qwc / BIAS*/ 4 );
}
__forceinline static void SPR1transfer(u32 *data, int size)
@ -387,7 +387,7 @@ void _dmaSPR1() // toSPR work function
if (!done)
{
ptag = dmaGetAddr(spr1->tadr); //Set memory pointer to TADR
CPU_INT(DMAC_TO_SPR, (ptag[0].QWC / BIAS));// the lower 16 bits of the tag / BIAS);
CPU_INT(DMAC_TO_SPR, /*(ptag[0].QWC / BIAS)*/ 4 );// the lower 16 bits of the tag / BIAS);
}
break;
}
@ -411,13 +411,13 @@ void dmaSPR1() // toSPR
{
tDMA_TAG *ptag;
ptag = dmaGetAddr(spr1->tadr); //Set memory pointer to TADR
CPU_INT(DMAC_TO_SPR, ptag[0].QWC / BIAS);
CPU_INT(DMAC_TO_SPR, /*ptag[0].QWC / BIAS*/ 4 );
return;
}
// COMPLETE HACK!!! For now at least.. FFX Videos dont rely on interrupts or reading DMA values
// It merely assumes that the last one has finished then starts another one (broke with the DMA fix)
// This "shouldn't" cause any problems as SPR is generally faster than the other DMAS anyway. (Refraction)
CPU_INT(DMAC_TO_SPR, spr1->qwc / BIAS);
CPU_INT(DMAC_TO_SPR, /*spr1->qwc / BIAS*/ 4 );
}
void SPRTOinterrupt()

2
pcsx2/Sif0.cpp
View File

@ -35,7 +35,7 @@ static __forceinline void Sif0Init()
static __forceinline bool WriteFifoToEE()
{
const int readSize = min((s32)sif0dma->qwc, sif0.fifo.size >> 2);
//if (readSize <= 0)
//if (readSize > 0)
//{
tDMA_TAG *ptag;

1
plugins/GSdx/GSCrc.cpp
View File

@ -157,6 +157,7 @@ CRC::Game CRC::m_games[] =
{0xD7273511, SMTDDS1, US, ZWriteMustNotClear}, // SMT Digital Devil Saga
{0x1683A6BE, SMTDDS1, EU, ZWriteMustNotClear}, // SMT Digital Devil Saga
{0x44865CE1, SMTDDS1, JP, ZWriteMustNotClear}, // SMT Digital Devil Saga
{0xD382C164, SMTDDS2, US, ZWriteMustNotClear}, // SMT Digital Devil Saga 2
{0xE47C1A9C, SMTDDS2, JP, ZWriteMustNotClear}, // SMT Digital Devil Saga 2
{0x0B8AB37B, RozenMaidenGebetGarden, JP, 0},
};