ShuriZma
/
pcsx2
mirror of https://github.com/PCSX2/pcsx2.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

SPU2-X: Don't force align transfer addresses, fixes The Bouncer. I honestly don't know on what basis they were force aligned in the first place. The Bouncer very strangely has correctly aligned sample data in IOP memory which it uploads using an unaligned DMA with SPU2 set to an unaligned address, resulting in the data being correctly aligned in the end. Weird. It also writes the address twice in the order high word, low, low, high, the first pair being aligned and the second pair not. Really weird. 

git-svn-id: http://pcsx2.googlecode.com/svn/trunk@5398 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
sudonim1@gmail.com 2012-09-02 21:33:16 +00:00
parent b643fa06d5
commit 7027c54309
1 changed files with 7 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
plugins/spu2-x/src/Dma.cpp
View File

@ -314,7 +314,7 @@ void V_Core::PlainDMAWrite(u16 *pMem, u32 size)
#endif #endif
} }
TSA = TDA & 0xFFFF0; TSA = TDA;
DMAICounter = size; DMAICounter = size;
TADR = MADR + (size<<1); TADR = MADR + (size<<1);
} }
@ -322,7 +322,7 @@ void V_Core::PlainDMAWrite(u16 *pMem, u32 size)
void V_Core::DoDMAread(u16* pMem, u32 size) void V_Core::DoDMAread(u16* pMem, u32 size)
{ {
#ifndef ENABLE_NEW_IOPDMA_SPU2 #ifndef ENABLE_NEW_IOPDMA_SPU2
TSA &= 0xffff8; TSA &= 0xfffff;
u32 buff1end = TSA + size; u32 buff1end = TSA + size;
u32 buff2end = 0; u32 buff2end = 0;
@ -379,7 +379,7 @@ void V_Core::DoDMAread(u16* pMem, u32 size)
} }
} }
TSA = TDA & 0xFFFFF; TSA = TDA;
DMAICounter = size; DMAICounter = size;
Regs.STATX &= ~0x80; Regs.STATX &= ~0x80;
@ -408,7 +408,7 @@ void V_Core::DoDMAwrite(u16* pMem, u32 size)
DebugCores[Index].dmaFlag = 2; DebugCores[Index].dmaFlag = 2;
} }
TSA &= ~7; TSA &= 0xfffff;
bool adma_enable = ((AutoDMACtrl&(Index+1))==(Index+1)); bool adma_enable = ((AutoDMACtrl&(Index+1))==(Index+1));
@ -436,7 +436,7 @@ s32 V_Core::NewDmaRead(u32* data, u32 bytesLeft, u32* bytesProcessed)
bool DmaStarting = !DmaStarted; bool DmaStarting = !DmaStarted;
DmaStarted = true; DmaStarted = true;
TSA &= 0xffff8; TSA &= 0xfffff;
u16* pMem = (u16*)data; u16* pMem = (u16*)data;
@ -495,7 +495,7 @@ s32 V_Core::NewDmaRead(u32* data, u32 bytesLeft, u32* bytesProcessed)
} }
} }
TSA = TDA & 0xFFFFF; TSA = TDA;
Regs.STATX &= ~0x80; Regs.STATX &= ~0x80;
Regs.STATX |= 0x400; Regs.STATX |= 0x400;
@ -526,7 +526,7 @@ s32 V_Core::NewDmaWrite(u32* data, u32 bytesLeft, u32* bytesProcessed)
DebugCores[Index].dmaFlag = 1; DebugCores[Index].dmaFlag = 1;
} }
TSA &= ~7; TSA &= 0xfffff;
bool adma_enable = ((AutoDMACtrl&(Index+1))==(Index+1)); bool adma_enable = ((AutoDMACtrl&(Index+1))==(Index+1));