diff --git a/PCSX2_suite.sln b/PCSX2_suite.sln
index ec8bd18146..ca95cd4b5f 100644
--- a/PCSX2_suite.sln
+++ b/PCSX2_suite.sln
@@ -570,7 +570,6 @@ Global
{2F6C0388-20CB-4242-9F6C-A6EBB6A83F47} = {78EBE642-7A4D-4EA7-86BE-5639C6646C38}
{E4081455-398C-4610-A87C-90A8A7D72DC3} = {703FD00B-D7A0-41E3-BD03-CEC86B385DAF}
{BF7B81A5-E348-4F7C-A69F-F74C8EEEAD70} = {E1828E40-2FBB-48FE-AE7F-5587755DCE0E}
- {3D0EB14D-32F3-4D82-9C6D-B806ADBB859C} = {E1828E40-2FBB-48FE-AE7F-5587755DCE0E}
{04439C5F-05FB-4A9C-AAD1-5388C25377DB} = {E1828E40-2FBB-48FE-AE7F-5587755DCE0E}
{A51123F5-9505-4EAE-85E7-D320290A272C} = {88F517F9-CE1C-4005-9BDF-4481FEB55053}
{4639972E-424E-4E13-8B07-CA403C481346} = {88F517F9-CE1C-4005-9BDF-4481FEB55053}
diff --git a/pcsx2/CMakeLists.txt b/pcsx2/CMakeLists.txt
index 061a891131..03aee64370 100644
--- a/pcsx2/CMakeLists.txt
+++ b/pcsx2/CMakeLists.txt
@@ -56,7 +56,7 @@ set(pcsx2Sources
GameDatabase.cpp
Dump.cpp
Elfheader.cpp
- FW.cpp
+ FW.cpp
FiFo.cpp
FPU.cpp
Gif.cpp
@@ -136,7 +136,7 @@ set(pcsx2Headers
Dump.h
GameDatabase.h
Elfheader.h
- FW.h
+ FW.h
Gif.h
Gif_Unit.h
GS.h
diff --git a/pcsx2/FW.cpp b/pcsx2/FW.cpp
index 91a8d1ee68..3d3bafa22b 100644
--- a/pcsx2/FW.cpp
+++ b/pcsx2/FW.cpp
@@ -13,6 +13,8 @@
* If not, see .
*/
+#include "PrecompiledHeader.h"
+
#include
#include
using namespace std;
@@ -20,179 +22,182 @@ using namespace std;
#include "FW.h"
u8 phyregs[16];
-s8 *fwregs;
+s8* fwregs;
void (*FWirq)();
s32 FWopen()
{
- memset(phyregs, 0, sizeof(phyregs));
- // Initializing our registers.
- fwregs = (s8 *)calloc(0x10000, 1);
- if (fwregs == NULL) {
- DevCon.WriteLn("FW: Error allocating Memory");
- return -1;
- }
- return 0;
+ memset(phyregs, 0, sizeof(phyregs));
+ // Initializing our registers.
+ fwregs = (s8*)calloc(0x10000, 1);
+ if (fwregs == NULL)
+ {
+ DevCon.WriteLn("FW: Error allocating Memory");
+ return -1;
+ }
+ return 0;
}
void FWclose()
{
- // Freeing the registers.
- free(fwregs);
- fwregs = NULL;
-
+ // Freeing the registers.
+ free(fwregs);
+ fwregs = NULL;
}
void PHYWrite()
{
- u8 reg = (PHYACC >> 8) & 0xf;
- u8 data = PHYACC & 0xff;
+ u8 reg = (PHYACC >> 8) & 0xf;
+ u8 data = PHYACC & 0xff;
- phyregs[reg] = data;
+ phyregs[reg] = data;
- PHYACC &= ~0x4000ffff;
+ PHYACC &= ~0x4000ffff;
}
void PHYRead()
{
- u8 reg = (PHYACC >> 24) & 0xf;
+ u8 reg = (PHYACC >> 24) & 0xf;
- PHYACC &= ~0x80000000;
+ PHYACC &= ~0x80000000;
- PHYACC |= phyregs[reg] | (reg << 8);
+ PHYACC |= phyregs[reg] | (reg << 8);
- if (fwRu32(0x8424) & 0x40000000) //RRx interrupt mask
- {
- fwRu32(0x8420) |= 0x40000000;
- FWirq();
- }
+ if (fwRu32(0x8424) & 0x40000000) //RRx interrupt mask
+ {
+ fwRu32(0x8420) |= 0x40000000;
+ FWirq();
+ }
}
u32 FWread32(u32 addr)
{
- u32 ret = 0;
+ u32 ret = 0;
- switch (addr) {
- //Node ID Register the top part is default, bottom part i got from my ps2
- case 0x1f808400:
- ret = /*(0x3ff << 22) | 1;*/ 0xffc00001;
- break;
- // Control Register 2
- case 0x1f808410:
- ret = fwRu32(addr); //SCLK OK (Needs to be set when FW is "Ready"
- break;
- //Interrupt 0 Register
- case 0x1f808420:
- ret = fwRu32(addr);
- break;
+ switch (addr)
+ {
+ //Node ID Register the top part is default, bottom part i got from my ps2
+ case 0x1f808400:
+ ret = /*(0x3ff << 22) | 1;*/ 0xffc00001;
+ break;
+ // Control Register 2
+ case 0x1f808410:
+ ret = fwRu32(addr); //SCLK OK (Needs to be set when FW is "Ready"
+ break;
+ //Interrupt 0 Register
+ case 0x1f808420:
+ ret = fwRu32(addr);
+ break;
- //Dunno what this is, but my home console always returns this value 0x10000001
- //Seems to be related to the Node ID however (does some sort of compare/check)
- case 0x1f80847c:
- ret = 0x10000001;
- break;
+ //Dunno what this is, but my home console always returns this value 0x10000001
+ //Seems to be related to the Node ID however (does some sort of compare/check)
+ case 0x1f80847c:
+ ret = 0x10000001;
+ break;
- // Include other relevant 32 bit addresses we need to catch here.
- default:
- // By default, read fwregs.
- ret = fwRu32(addr);
- break;
- }
+ // Include other relevant 32 bit addresses we need to catch here.
+ default:
+ // By default, read fwregs.
+ ret = fwRu32(addr);
+ break;
+ }
- DevCon.WriteLn("FW: read mem 0x%x: 0x%x", addr, ret);
+ DevCon.WriteLn("FW: read mem 0x%x: 0x%x", addr, ret);
- return ret;
+ return ret;
}
void FWwrite32(u32 addr, u32 value)
{
- switch (addr) {
- // Include other memory locations we want to catch here.
- // For example:
- //
- // case 0x1f808400:
- // case 0x1f808414:
- // case 0x1f808420:
- // case 0x1f808428:
- // case 0x1f808430:
- //
+ switch (addr)
+ {
+ // Include other memory locations we want to catch here.
+ // For example:
+ //
+ // case 0x1f808400:
+ // case 0x1f808414:
+ // case 0x1f808420:
+ // case 0x1f808428:
+ // case 0x1f808430:
+ //
- //PHY access
- case 0x1f808414:
- //If in read mode (top bit set) we read the PHY register requested then set the RRx interrupt if it's enabled
- //Im presuming we send that back to pcsx2 then. This register stores the result, plus whatever was written (minus the read/write flag
- fwRu32(addr) = value; //R/W Bit cleaned in underneath function
- if (value & 0x40000000) //Writing to PHY
- {
- PHYWrite();
- } else if (value & 0x80000000) //Reading from PHY
- {
- PHYRead();
- }
- break;
+ //PHY access
+ case 0x1f808414:
+ //If in read mode (top bit set) we read the PHY register requested then set the RRx interrupt if it's enabled
+ //Im presuming we send that back to pcsx2 then. This register stores the result, plus whatever was written (minus the read/write flag
+ fwRu32(addr) = value; //R/W Bit cleaned in underneath function
+ if (value & 0x40000000) //Writing to PHY
+ {
+ PHYWrite();
+ }
+ else if (value & 0x80000000) //Reading from PHY
+ {
+ PHYRead();
+ }
+ break;
- //Control Register 0
- case 0x1f808408:
- //This enables different functions of the link interface
- //Just straight writes, should brobably struct these later.
- //Default written settings (on unreal tournament) are
- //Urcv M = 1
- //RSP 0 = 1
- //Retlim = 0xF
- //Cyc Tmr En = 1
- //Bus ID Rst = 1
- //Rcv Self ID = 1
- fwRu32(addr) = value;
- // if((value & 0x800000) && (fwRu32(0x842C) & 0x2))
- // {
- // fwRu32(0x8428) |= 0x2;
- // FWirq();
- // }
- fwRu32(addr) &= ~0x800000;
- break;
- //Control Register 2
- case 0x1f808410: // fwRu32(addr) = value; break;
- //Ignore writes to this for now, apart from 0x2 which is Link Power Enable
- //0x8 is SCLK OK (Ready) which should be set for emulation
- fwRu32(addr) = 0x8 /*| value & 0x2*/;
- break;
- //Interrupt 0 Register
- case 0x1f808420:
- //Interrupt 1 Register
- case 0x1f808428:
- //Interrupt 2 Register
- case 0x1f808430:
- //Writes of 1 clear the corresponding bits
- fwRu32(addr) &= ~value;
- break;
- //Interrupt 0 Register Mask
- case 0x1f808424:
- //Interrupt 1 Register Mask
- case 0x1f80842C:
- //Interrupt 2 Register Mask
- case 0x1f808434:
- //These are direct writes (as it's a mask!)
- fwRu32(addr) = value;
- break;
- //DMA Control and Status Register 0
- case 0x1f8084B8:
- fwRu32(addr) = value;
- break;
- //DMA Control and Status Register 1
- case 0x1f808538:
- fwRu32(addr) = value;
- break;
- default:
- // By default, just write it to fwregs.
- fwRu32(addr) = value;
- break;
- }
- DevCon.WriteLn("FW: write mem 0x%x: 0x%x", addr, value);
+ //Control Register 0
+ case 0x1f808408:
+ //This enables different functions of the link interface
+ //Just straight writes, should brobably struct these later.
+ //Default written settings (on unreal tournament) are
+ //Urcv M = 1
+ //RSP 0 = 1
+ //Retlim = 0xF
+ //Cyc Tmr En = 1
+ //Bus ID Rst = 1
+ //Rcv Self ID = 1
+ fwRu32(addr) = value;
+ // if((value & 0x800000) && (fwRu32(0x842C) & 0x2))
+ // {
+ // fwRu32(0x8428) |= 0x2;
+ // FWirq();
+ // }
+ fwRu32(addr) &= ~0x800000;
+ break;
+ //Control Register 2
+ case 0x1f808410: // fwRu32(addr) = value; break;
+ //Ignore writes to this for now, apart from 0x2 which is Link Power Enable
+ //0x8 is SCLK OK (Ready) which should be set for emulation
+ fwRu32(addr) = 0x8 /*| value & 0x2*/;
+ break;
+ //Interrupt 0 Register
+ case 0x1f808420:
+ //Interrupt 1 Register
+ case 0x1f808428:
+ //Interrupt 2 Register
+ case 0x1f808430:
+ //Writes of 1 clear the corresponding bits
+ fwRu32(addr) &= ~value;
+ break;
+ //Interrupt 0 Register Mask
+ case 0x1f808424:
+ //Interrupt 1 Register Mask
+ case 0x1f80842C:
+ //Interrupt 2 Register Mask
+ case 0x1f808434:
+ //These are direct writes (as it's a mask!)
+ fwRu32(addr) = value;
+ break;
+ //DMA Control and Status Register 0
+ case 0x1f8084B8:
+ fwRu32(addr) = value;
+ break;
+ //DMA Control and Status Register 1
+ case 0x1f808538:
+ fwRu32(addr) = value;
+ break;
+ default:
+ // By default, just write it to fwregs.
+ fwRu32(addr) = value;
+ break;
+ }
+ DevCon.WriteLn("FW: write mem 0x%x: 0x%x", addr, value);
}
void FWirqCallback(void (*callback)())
{
- // Register FWirq, so we can trigger an interrupt with it later.
- FWirq = callback;
+ // Register FWirq, so we can trigger an interrupt with it later.
+ FWirq = callback;
}
diff --git a/pcsx2/FW.h b/pcsx2/FW.h
index 9f47f02875..ca84028274 100644
--- a/pcsx2/FW.h
+++ b/pcsx2/FW.h
@@ -20,9 +20,9 @@
#define FWdefs
// Our main memory storage, and defines for accessing it.
-extern s8 *fwregs;
-#define fwRs32(mem) (*(s32 *)&fwregs[(mem)&0xffff])
-#define fwRu32(mem) (*(u32 *)&fwregs[(mem)&0xffff])
+extern s8* fwregs;
+#define fwRs32(mem) (*(s32*)&fwregs[(mem)&0xffff])
+#define fwRu32(mem) (*(u32*)&fwregs[(mem)&0xffff])
//PHY Access Address for ease of use :P
#define PHYACC fwRu32(0x8414)
diff --git a/pcsx2/windows/VCprojects/pcsx2.vcxproj.filters b/pcsx2/windows/VCprojects/pcsx2.vcxproj.filters
index 9825383c5a..467fa10e0c 100644
--- a/pcsx2/windows/VCprojects/pcsx2.vcxproj.filters
+++ b/pcsx2/windows/VCprojects/pcsx2.vcxproj.filters
@@ -154,6 +154,9 @@
{a5904fb6-e846-4cbf-940c-ca1c604140a0}
+
+ {157740ae-b338-4d7f-81cb-cffa9d39a756}
+
@@ -893,7 +896,7 @@
System
- System
+ System\Ps2\Iop\FW
@@ -1354,7 +1357,7 @@
System\Include
- System\Include
+ System\Ps2\Iop\FW