mirror of https://github.com/PCSX2/pcsx2.git
some changes, should be a bit faster with "disable extra VU flags" checked
git-svn-id: http://pcsx2-playground.googlecode.com/svn/trunk@121 a6443dda-0b58-4228-96e9-037be469359c
This commit is contained in:
cottonvibes
Gregory Hainaut
parent
7107048266
commit
6f1fa0ec7a
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@ -4261,62 +4261,64 @@ void recVUMI_DIV(VURegs *VU, int info)
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void recVUMI_SQRT( VURegs *VU, int info )
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{
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int vftemp = ALLOCTEMPX86(MODE_8BITREG);
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u8* pjmp;
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int vftemp;
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//SysPrintf("SQRT Opcode \n");
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if( xmmregs[EEREC_T].mode & MODE_WRITE ) _unpackVFSS_xyzw(EEREC_TEMP, EEREC_T, _Ftf_);
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else SSE_MOVSS_M32_to_XMM(EEREC_TEMP, (uptr)&VU->VF[_Ft_].UL[_Ftf_]);
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AND32ItoM(VU_VI_ADDR(REG_STATUS_FLAG, 2), 0xFCF); // Clear D/I flags
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if( xmmregs[EEREC_T].mode & MODE_WRITE )
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_unpackVFSS_xyzw(EEREC_TEMP, EEREC_T, _Ftf_);
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else
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SSE_MOVSS_M32_to_XMM(EEREC_TEMP, (uptr)&VU->VF[_Ft_].UL[_Ftf_]);
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if (CHECK_VU_EXTRA_FLAGS) {
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vftemp = ALLOCTEMPX86(MODE_8BITREG);
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if (vftemp < 0) {SysPrintf("VU: SQRT allocation error!!!\n"); vftemp = EAX;}
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/* Check for negative divide */
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//XOR32RtoR(vftemp, vftemp);
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SSE_MOVMSKPS_XMM_to_R32(vftemp, EEREC_TEMP);
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AND32ItoR(vftemp, 1); //Check sign
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pjmp = JZ8(0); //Skip if none are
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OR32ItoM(VU_VI_ADDR(REG_STATUS_FLAG, 2), 0x410); //Invalid Flag - Negative number sqrt
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SSE_ANDPS_M128_to_XMM(EEREC_TEMP, (u32)const_clip); //So we do a cardinal sqrt
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x86SetJ8(pjmp);
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_freeX86reg(vftemp);
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}
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SSE_ANDPS_M128_to_XMM(EEREC_TEMP, (u32)const_clip); //Do a cardinal sqrt
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SSE_MINSS_M32_to_XMM(EEREC_TEMP, (uptr)g_maxvals); //Clamp infinities (only need to do positive clamp since EEREC_TEMP is positive)
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SSE_SQRTSS_XMM_to_XMM(EEREC_TEMP, EEREC_TEMP);
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//SSE_MINSS_M32_to_XMM(EEREC_TEMP, (uptr)g_maxvals); //Shouldn't need to clamp again
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SSE_MOVSS_XMM_to_M32(VU_VI_ADDR(REG_Q, 0), EEREC_TEMP);
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_freeX86reg(vftemp);
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}
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PCSX2_ALIGNED16(u64 RSQRT_TEMP_XMM[2]);
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void recVUMI_RSQRT(VURegs *VU, int info)
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{
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int vftemp = ALLOCTEMPX86(MODE_8BITREG);
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int t1reg;
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u32* ajmp32;
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u32* bjmp32;
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u8* ajmp8;
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u32* ajmp32, * bjmp32;
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int t1reg, vftemp;
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if( _Ftf_ ) _unpackVFSS_xyzw(EEREC_TEMP, EEREC_T, _Ftf_);
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else SSE_MOVSS_XMM_to_XMM(EEREC_TEMP, EEREC_T);
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AND32ItoM(VU_VI_ADDR(REG_STATUS_FLAG, 2), 0xFCF); // Clear D/I flags
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if( _Ftf_ )
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_unpackVFSS_xyzw(EEREC_TEMP, EEREC_T, _Ftf_);
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else
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SSE_MOVSS_XMM_to_XMM(EEREC_TEMP, EEREC_T);
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if (CHECK_VU_EXTRA_FLAGS) {
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vftemp = ALLOCTEMPX86(MODE_8BITREG);
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if (vftemp < 0) { SysPrintf("VU: RSQRT allocation error!!!\n"); vftemp = EAX; }
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/* Check for negative divide */
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//XOR32RtoR(vftemp, vftemp);
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SSE_MOVMSKPS_XMM_to_R32(vftemp, EEREC_TEMP);
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AND32ItoR(vftemp, 1); //Check sign
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ajmp32 = JZ32(0); //Skip if none are
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ajmp8 = JZ8(0); //Skip if none are
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OR32ItoM(VU_VI_ADDR(REG_STATUS_FLAG, 2), 0x410); //Invalid Flag - Negative number sqrt
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SSE_ANDPS_M128_to_XMM(EEREC_TEMP, (u32)const_clip); //So we do a cardinal sqrt
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x86SetJ32(ajmp32);
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if (CHECK_EXTRA_OVERFLOW) // Clamp Infinities to Fmax
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SSE_MINSS_M32_to_XMM(EEREC_TEMP, (uptr)g_maxvals);
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x86SetJ8(ajmp8);
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}
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SSE_ANDPS_M128_to_XMM(EEREC_TEMP, (u32)const_clip); //Do a cardinal sqrt
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if (CHECK_EXTRA_OVERFLOW) SSE_MINSS_M32_to_XMM(EEREC_TEMP, (uptr)g_maxvals);// Clamp Infinities to Fmax
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SSE_SQRTSS_XMM_to_XMM(EEREC_TEMP, EEREC_TEMP);
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t1reg = _vuGetTempXMMreg(info);
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@ -4324,16 +4326,16 @@ void recVUMI_RSQRT(VURegs *VU, int info)
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if( t1reg >= 0 )
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{
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//SysPrintf("RSQRT Opcode Part 1 \n");
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if (CHECK_VU_EXTRA_FLAGS) {
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// Ft can still be zero here! so we need to check if its zero and set the correct flag.
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SSE_XORPS_XMM_to_XMM(t1reg, t1reg); // Clear t1reg
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//XOR32RtoR(vftemp, vftemp);
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SSE_CMPEQSS_XMM_to_XMM(t1reg, EEREC_TEMP); // Set all F's if each vector is zero
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SSE_MOVMSKPS_XMM_to_R32(vftemp, t1reg); // Move the sign bits of the previous calculation
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AND32ItoR( vftemp, 0x01 ); // Grab "Is Zero" bits from the previous calculation
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ajmp32 = JZ32(0); // Skip if none are
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OR32ItoM(VU_VI_ADDR(REG_STATUS_FLAG, 2), 0x820); // Zero divide flag
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_unpackVFSS_xyzw(EEREC_TEMP, EEREC_S, _Fsf_);
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@ -4341,17 +4343,19 @@ void recVUMI_RSQRT(VURegs *VU, int info)
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SSE_ORPS_M128_to_XMM(EEREC_TEMP, (uptr)&g_maxvals[0]); // If division by zero, then EEREC_TEMP = positive fmax
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SSE_MOVSS_XMM_to_M32(VU_VI_ADDR(REG_Q, 0), EEREC_TEMP);
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bjmp32 = JMP32(0);
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x86SetJ32(ajmp32);
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}
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_unpackVFSS_xyzw(t1reg, EEREC_S, _Fsf_);
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if (CHECK_EXTRA_OVERFLOW) // Clamp Infinities
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vuFloat2(t1reg, t1reg, 0x8);
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if (CHECK_EXTRA_OVERFLOW) vuFloat2(t1reg, t1reg, 0x8); // Clamp Infinities
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SSE_DIVSS_XMM_to_XMM(t1reg, EEREC_TEMP);
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vuFloat2(t1reg, t1reg, 0x8);
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SSE_MOVSS_XMM_to_M32(VU_VI_ADDR(REG_Q, 0), t1reg);
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if (CHECK_VU_EXTRA_FLAGS) {
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x86SetJ32(bjmp32);
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_freeX86reg(vftemp);
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}
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_freeXMMreg(t1reg);
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}
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@ -4362,6 +4366,7 @@ void recVUMI_RSQRT(VURegs *VU, int info)
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; // Makes t1reg not be EEREC_TEMP or EEREC_S.
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SSE_MOVAPS_XMM_to_M128( (uptr)&RSQRT_TEMP_XMM[0], t1reg ); // backup data in t1reg to a temp address
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if (CHECK_VU_EXTRA_FLAGS) {
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// Ft can still be zero here! so we need to check if its zero and set the correct flag.
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SSE_XORPS_XMM_to_XMM(t1reg, t1reg); // Clear t1reg
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//XOR32RtoR(vftemp, vftemp);
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@ -4371,7 +4376,6 @@ void recVUMI_RSQRT(VURegs *VU, int info)
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AND32ItoR( vftemp, 0x01 ); // Grab "Is Zero" bits from the previous calculation
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ajmp32 = JZ32(0); // Skip if none are
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OR32ItoM(VU_VI_ADDR(REG_STATUS_FLAG, 2), 0x820); // Zero divide flag
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_unpackVFSS_xyzw(EEREC_TEMP, EEREC_S, _Fsf_);
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@ -4379,8 +4383,8 @@ void recVUMI_RSQRT(VURegs *VU, int info)
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SSE_ORPS_M128_to_XMM(EEREC_TEMP, (uptr)&g_maxvals[0]); // If division by zero, then EEREC_TEMP = positive fmax
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SSE_MOVSS_XMM_to_M32(VU_VI_ADDR(REG_Q, 0), EEREC_TEMP);
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bjmp32 = JMP32(0);
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x86SetJ32(ajmp32);
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}
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_unpackVFSS_xyzw(t1reg, EEREC_S, _Fsf_);
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if (CHECK_EXTRA_OVERFLOW) // Clamp Infinities
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@ -4389,12 +4393,13 @@ void recVUMI_RSQRT(VURegs *VU, int info)
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vuFloat2(t1reg, t1reg, 0x8);
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SSE_MOVSS_XMM_to_M32(VU_VI_ADDR(REG_Q, 0), t1reg);
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if (CHECK_VU_EXTRA_FLAGS) {
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x86SetJ32(bjmp32);
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_freeX86reg(vftemp);
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}
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SSE_MOVAPS_M128_to_XMM( t1reg, (uptr)&RSQRT_TEMP_XMM[0] ); // restore t1reg data
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}
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_freeX86reg(vftemp);
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}
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void _addISIMMtoIT(VURegs *VU, s16 imm, int info)
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