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* Likely fix for cpuIntsEnabled; I think this is the behavior Ref intended. :) 

git-svn-id: http://pcsx2.googlecode.com/svn/trunk@3345 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
Jake.Stine 2010-06-29 16:06:12 +00:00
parent f8365215c4
commit 6d57e15615
1 changed files with 10 additions and 3 deletions
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13
pcsx2/R5900.cpp
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@ -351,10 +351,10 @@ static __forceinline void _cpuTestPERF()
static bool cpuIntsEnabled(int Interrupt)
{
//int IntType = cpuRegs.CP0.n.Status.val & Interrupt; //Choose either INTC or DMAC, depending on what called it
bool IntType = !!(cpuRegs.CP0.n.Status.val & Interrupt); //Choose either INTC or DMAC, depending on what called it
return cpuRegs.CP0.n.Status.b.EIE && cpuRegs.CP0.n.Status.b.IE &&
!cpuRegs.CP0.n.Status.b.EXL && (cpuRegs.CP0.n.Status.b.ERL == 0) && Interrupt;
!cpuRegs.CP0.n.Status.b.EXL && (cpuRegs.CP0.n.Status.b.ERL == 0) && IntType;
}
// if cpuRegs.cycle is greater than this cycle, should check cpuBranchTest for updates
@ -484,9 +484,13 @@ __forceinline void _cpuBranchTest_Shared()
__releaseinline void cpuTestINTCInts()
{
// Check the internal Event System -- if one's already scheduled then don't bother:
if( cpuRegs.interrupt & (1 << 30) ) return;
//if( (cpuRegs.CP0.n.Status.val & 0x10407) != 0x10401 ) return;
// Check the COP0's Status register for general interrupt disables, and the 0x400
// bit (which is INTC master toggle).
if( !cpuIntsEnabled(0x400) ) return;
if( (psHu32(INTC_STAT) & psHu32(INTC_MASK)) == 0 ) return;
cpuRegs.interrupt|= 1 << 30;
@ -506,8 +510,11 @@ __releaseinline void cpuTestINTCInts()
__forceinline void cpuTestDMACInts()
{
// Check the internal Event System -- if one's already scheduled then don't bother:
if ( cpuRegs.interrupt & (1 << 31) ) return;
// Check the COP0's Status register for general interrupt disables, and the 0x800
// bit (which is the DMAC master toggle).
if( !cpuIntsEnabled(0x800) ) return;
if ( ( (psHu16(0xe012) & psHu16(0xe010)) == 0) &&