mirror of https://github.com/PCSX2/pcsx2.git
More overflow checking made optional
git-svn-id: http://pcsx2-playground.googlecode.com/svn/trunk@27 a6443dda-0b58-4228-96e9-037be469359c
This commit is contained in:
parent
4eb51a4ec4
commit
6d2a9644a8
|
@ -1338,7 +1338,7 @@ void vuFloat3(uptr x86ptr)
|
||||||
|
|
||||||
void CheckForOverflow(VURegs *VU, int info, int regd)
|
void CheckForOverflow(VURegs *VU, int info, int regd)
|
||||||
{
|
{
|
||||||
testWhenOverflow(info, regd, EEREC_TEMP);
|
//testWhenOverflow(info, regd, EEREC_TEMP);
|
||||||
//CheckForOverflow_(regd, EEREC_TEMP, _X_Y_Z_W);
|
//CheckForOverflow_(regd, EEREC_TEMP, _X_Y_Z_W);
|
||||||
if (EEREC_TEMP != regd) {
|
if (EEREC_TEMP != regd) {
|
||||||
//testWhenOverflow(info, regd, EEREC_TEMP);
|
//testWhenOverflow(info, regd, EEREC_TEMP);
|
||||||
|
@ -3610,17 +3610,20 @@ void recVUMI_ITOF0( VURegs *VU, int info )
|
||||||
|
|
||||||
VU_MERGE_REGS(EEREC_T, EEREC_TEMP);
|
VU_MERGE_REGS(EEREC_T, EEREC_TEMP);
|
||||||
xmmregs[EEREC_T].mode |= MODE_WRITE;
|
xmmregs[EEREC_T].mode |= MODE_WRITE;
|
||||||
|
if (CHECK_EXTRA_OVERFLOW)
|
||||||
vuFloat2(EEREC_T, EEREC_TEMP, _X_Y_Z_W); // Clamp infinities
|
vuFloat2(EEREC_T, EEREC_TEMP, _X_Y_Z_W); // Clamp infinities
|
||||||
}
|
}
|
||||||
else {
|
else {
|
||||||
if( cpucaps.hasStreamingSIMD2Extensions ) {
|
if( cpucaps.hasStreamingSIMD2Extensions ) {
|
||||||
SSE2_CVTDQ2PS_XMM_to_XMM(EEREC_T, EEREC_S);
|
SSE2_CVTDQ2PS_XMM_to_XMM(EEREC_T, EEREC_S);
|
||||||
|
if (CHECK_EXTRA_OVERFLOW)
|
||||||
vuFloat2(EEREC_T, EEREC_TEMP, 15); // Clamp infinities
|
vuFloat2(EEREC_T, EEREC_TEMP, 15); // Clamp infinities
|
||||||
}
|
}
|
||||||
else {
|
else {
|
||||||
_deleteVFtoXMMreg(_Fs_, VU==&VU1, 1);
|
_deleteVFtoXMMreg(_Fs_, VU==&VU1, 1);
|
||||||
SSE2EMU_CVTDQ2PS_M128_to_XMM(EEREC_T, VU_VFx_ADDR( _Fs_ ));
|
SSE2EMU_CVTDQ2PS_M128_to_XMM(EEREC_T, VU_VFx_ADDR( _Fs_ ));
|
||||||
xmmregs[EEREC_T].mode |= MODE_WRITE;
|
xmmregs[EEREC_T].mode |= MODE_WRITE;
|
||||||
|
if (CHECK_EXTRA_OVERFLOW)
|
||||||
vuFloat2(EEREC_T, EEREC_TEMP, 15); // Clamp infinities
|
vuFloat2(EEREC_T, EEREC_TEMP, 15); // Clamp infinities
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
@ -3640,6 +3643,7 @@ void recVUMI_ITOFX(VURegs *VU, int addr, int info)
|
||||||
SSE_MULPS_M128_to_XMM(EEREC_TEMP, addr);
|
SSE_MULPS_M128_to_XMM(EEREC_TEMP, addr);
|
||||||
VU_MERGE_REGS(EEREC_T, EEREC_TEMP);
|
VU_MERGE_REGS(EEREC_T, EEREC_TEMP);
|
||||||
xmmregs[EEREC_T].mode |= MODE_WRITE;
|
xmmregs[EEREC_T].mode |= MODE_WRITE;
|
||||||
|
if (CHECK_EXTRA_OVERFLOW)
|
||||||
vuFloat2(EEREC_T, EEREC_TEMP, _X_Y_Z_W); // Clamp infinities
|
vuFloat2(EEREC_T, EEREC_TEMP, _X_Y_Z_W); // Clamp infinities
|
||||||
} else {
|
} else {
|
||||||
if(cpucaps.hasStreamingSIMD2Extensions) SSE2_CVTDQ2PS_XMM_to_XMM(EEREC_T, EEREC_S);
|
if(cpucaps.hasStreamingSIMD2Extensions) SSE2_CVTDQ2PS_XMM_to_XMM(EEREC_T, EEREC_S);
|
||||||
|
@ -3650,6 +3654,7 @@ void recVUMI_ITOFX(VURegs *VU, int addr, int info)
|
||||||
}
|
}
|
||||||
|
|
||||||
SSE_MULPS_M128_to_XMM(EEREC_T, addr);
|
SSE_MULPS_M128_to_XMM(EEREC_T, addr);
|
||||||
|
if (CHECK_EXTRA_OVERFLOW)
|
||||||
vuFloat2(EEREC_T, EEREC_TEMP, 15); // Clamp infinities
|
vuFloat2(EEREC_T, EEREC_TEMP, 15); // Clamp infinities
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
@ -3891,7 +3896,7 @@ void recVUMI_DIV(VURegs *VU, int info)
|
||||||
SSE_DIVSS_XMM_to_XMM(EEREC_TEMP, EEREC_T);
|
SSE_DIVSS_XMM_to_XMM(EEREC_TEMP, EEREC_T);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
if (CHECK_EXTRA_OVERFLOW)
|
||||||
vuFloat2(EEREC_TEMP, EEREC_TEMP, 0x8);
|
vuFloat2(EEREC_TEMP, EEREC_TEMP, 0x8);
|
||||||
|
|
||||||
SSE_MOVSS_XMM_to_M32(VU_VI_ADDR(REG_Q, 0), EEREC_TEMP);
|
SSE_MOVSS_XMM_to_M32(VU_VI_ADDR(REG_Q, 0), EEREC_TEMP);
|
||||||
|
@ -3933,6 +3938,7 @@ void recVUMI_SQRT( VURegs *VU, int info )
|
||||||
|
|
||||||
SSE_SQRTSS_XMM_to_XMM(EEREC_TEMP, EEREC_TEMP);
|
SSE_SQRTSS_XMM_to_XMM(EEREC_TEMP, EEREC_TEMP);
|
||||||
|
|
||||||
|
if (CHECK_EXTRA_OVERFLOW)
|
||||||
vuFloat2(EEREC_TEMP, EEREC_TEMP, 0x8);
|
vuFloat2(EEREC_TEMP, EEREC_TEMP, 0x8);
|
||||||
|
|
||||||
SSE_MOVSS_XMM_to_M32(VU_VI_ADDR(REG_Q, 0), EEREC_TEMP);
|
SSE_MOVSS_XMM_to_M32(VU_VI_ADDR(REG_Q, 0), EEREC_TEMP);
|
||||||
|
@ -4047,6 +4053,7 @@ void recVUMI_RSQRT(VURegs *VU, int info)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
if (CHECK_EXTRA_OVERFLOW)
|
||||||
vuFloat2(EEREC_TEMP, EEREC_TEMP, 0x8);
|
vuFloat2(EEREC_TEMP, EEREC_TEMP, 0x8);
|
||||||
|
|
||||||
SSE_MOVSS_XMM_to_M32(VU_VI_ADDR(REG_Q, 0), EEREC_TEMP);
|
SSE_MOVSS_XMM_to_M32(VU_VI_ADDR(REG_Q, 0), EEREC_TEMP);
|
||||||
|
@ -5489,6 +5496,7 @@ void recVUMI_ESADD( VURegs *VU, int info)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
if (CHECK_EXTRA_OVERFLOW)
|
||||||
vuFloat2(EEREC_TEMP, EEREC_D, 0x8);
|
vuFloat2(EEREC_TEMP, EEREC_D, 0x8);
|
||||||
|
|
||||||
SSE_MOVSS_XMM_to_M32(VU_VI_ADDR(REG_P, 0), EEREC_TEMP);
|
SSE_MOVSS_XMM_to_M32(VU_VI_ADDR(REG_P, 0), EEREC_TEMP);
|
||||||
|
@ -5526,6 +5534,7 @@ void recVUMI_ERSADD( VURegs *VU, int info )
|
||||||
|
|
||||||
// don't use RCPSS (very bad precision)
|
// don't use RCPSS (very bad precision)
|
||||||
SSE_DIVSS_XMM_to_XMM(EEREC_TEMP, EEREC_D);
|
SSE_DIVSS_XMM_to_XMM(EEREC_TEMP, EEREC_D);
|
||||||
|
if (CHECK_EXTRA_OVERFLOW)
|
||||||
vuFloat2(EEREC_TEMP, EEREC_D, 0x8);
|
vuFloat2(EEREC_TEMP, EEREC_D, 0x8);
|
||||||
|
|
||||||
SSE_MOVSS_XMM_to_M32(VU_VI_ADDR(REG_P, 0), EEREC_TEMP);
|
SSE_MOVSS_XMM_to_M32(VU_VI_ADDR(REG_P, 0), EEREC_TEMP);
|
||||||
|
|
Loading…
Reference in New Issue