mirror of https://github.com/PCSX2/pcsx2.git
PCSX2:
- Added *.MDF Disc Images to the "Run ISO" file browser. I'm not entirely sure if theres any file system differences between .mdf and .iso (couldn't find much info on it); but all my .mdf files are working as-is with gigaherz's code, so I think compatibility should be fine. - Moved "Run ISO" menu option above "Run BIOS" since users will run ISO's more often than the bios xD microVU: - More work in progress stuff... hopefully I finish within the next few days. git-svn-id: http://pcsx2.googlecode.com/svn/trunk@1543 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
cottonvibes
parent
81009002bb
commit
6c8a075131
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@ -455,7 +455,7 @@ BOOL Open_Iso_File_Proc( std::string& outstr )
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OPENFILENAME ofn;
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char szFileName[ g_MaxPath ];
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char szFileTitle[ g_MaxPath ];
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char * filter = "ISO Files (*.ISO)\0*.ISO\0Blockdump Files (*.dump)\0*.dump\0ALL Files (*.*)\0*.*\0";
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char * filter = "Compatible Disc Image Files (*.ISO, *.MDF)\0*.ISO;*.MDF\0Blockdump Files (*.dump)\0*.dump\0ALL Files (*.*)\0*.*\0";
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memzero_obj( szFileName );
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memzero_obj( szFileTitle );
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@ -1001,8 +1001,8 @@ void CreateMainMenu() {
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ADDSUBMENUS(0, 1, _("&States"));
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ADDSEPARATOR(0);
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ADDMENUITEM(0, _("&Open ELF File..."), ID_FILEOPEN);
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ADDMENUITEM(0, _("Run &ISO Image..."), ID_FILE_RUNISO);
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ADDMENUITEM(0, _("Run &BIOS (No Disc)"), ID_FILE_RUNBIOS);
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ADDMENUITEM(0, _("Run &ISO Image..."), ID_FILE_RUNISO);
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ADDMENUITEM(0, _("&Run CD/DVD"), ID_FILE_RUNCD);
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ADDSUBMENUS(1, 3, _("&Save"));
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ADDSUBMENUS(1, 2, _("&Load"));
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@ -174,6 +174,9 @@ microVUt(void) mVUsetupBranch(mV, int* xStatus, int* xMac, int* xClip, int xCycl
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// Shuffle P/Q regs since every block starts at instance #0
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if (mVU->p || mVU->q) { SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, shufflePQ); }
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// Flush Allocated Regs
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mVU->regAlloc->flushAll();
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}
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microVUt(void) mVUincCycles(mV, int x) {
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@ -367,6 +370,9 @@ microVUr(void*) mVUcompile(microVU* mVU, u32 startPC, uptr pState) {
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// Setup Program Bounds/Range
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mVUsetupRange(mVU, startPC, 1);
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// Reset regAlloc
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mVU->regAlloc->reset();
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// First Pass
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iPC = startPC / 4;
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@ -178,12 +178,6 @@ private:
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microXMM xmmReg[xmmTotal];
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VURegs* vuRegs;
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int counter;
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void clearReg(int reg) {
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xmmReg[reg].reg = 0;
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xmmReg[reg].count = 0;
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xmmReg[reg].isNeeded = 0;
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xmmReg[reg].isTemp = 1;
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}
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int findFreeRegRec(int startIdx) {
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for (int i = startIdx; i < xmmTotal; i++) {
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if (!xmmReg[i].isNeeded) {
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@ -217,13 +211,18 @@ public:
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}
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counter = 0;
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}
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void flushAll() {
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for (int i = 0; i < xmmTotal; i++) {
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writeBackReg(i);
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}
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}
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void writeBackReg(int reg) {
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if (xmmReg[reg].reg && (xmmReg[reg].xyzw || (xmmReg[reg].reg >= 32))) {
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if (xmmReg[reg].reg && xmmReg[reg].xyzw) {
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if (xmmReg[reg].reg == 32) SSE_MOVAPS_XMM_to_M128((uptr)&vuRegs->ACC.UL[0], reg);
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else mVUsaveReg(reg, (uptr)&vuRegs->VF[xmmReg[reg].reg].UL[0], xmmReg[reg].xyzw, 1);
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for (int i = 0; i < xmmTotal; i++) {
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if (i = reg) continue;
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if (!xmmReg[i].isTemp && xmmReg[i].reg == xmmReg[reg].reg) {
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if (i == reg) continue;
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if (!xmmReg[i].isTemp && (xmmReg[i].reg == xmmReg[reg].reg)) {
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clearReg(i); // Invalidate any Cached Regs
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}
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}
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@ -240,23 +239,35 @@ public:
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void clearNeeded(int reg) {
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xmmReg[reg].isNeeded = 0;
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}
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int allocReg(int vfReg = -1, bool writeBack = 0, int xyzw = 0, int vfWriteBack = 0) {
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void clearReg(int reg) {
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xmmReg[reg].reg = 0;
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xmmReg[reg].count = 0;
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xmmReg[reg].xyzw = 0;
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xmmReg[reg].isNeeded = 0;
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xmmReg[reg].isTemp = 1;
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}
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int allocReg(int vfReg = -1, bool writeBack = 0, int xyzw = 0, int vfWriteBack = 0, bool cloneWrite = 1, bool needToLoad = 1) {
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counter++;
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for (int i = 0; i < xmmTotal; i++) {
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if ((vfReg >= 0) && (!xmmReg[i].isTemp) && (xmmReg[i].reg == vfReg)) {
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if (writeBack) {
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int z = findFreeReg();
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writeBackReg(z);
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if (xyzw == 8) SSE2_PSHUFD_XMM_to_XMM(z, i, 0);
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else if (xyzw == 4) SSE2_PSHUFD_XMM_to_XMM(z, i, 1);
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else if (xyzw == 2) SSE2_PSHUFD_XMM_to_XMM(z, i, 2);
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else if (xyzw == 1) SSE2_PSHUFD_XMM_to_XMM(z, i, 3);
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else if (z != i) SSE_MOVAPS_XMM_to_XMM (z, i);
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int z = i;
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if (cloneWrite) {
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z = findFreeReg();
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writeBackReg(z);
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if (needToLoad) {
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if (xyzw == 8) SSE2_PSHUFD_XMM_to_XMM(z, i, 0);
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else if (xyzw == 4) SSE2_PSHUFD_XMM_to_XMM(z, i, 1);
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else if (xyzw == 2) SSE2_PSHUFD_XMM_to_XMM(z, i, 2);
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else if (xyzw == 1) SSE2_PSHUFD_XMM_to_XMM(z, i, 3);
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else if (z != i) SSE_MOVAPS_XMM_to_XMM (z, i);
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}
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}
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xmmReg[z].reg = vfWriteBack;
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xmmReg[z].count = counter;
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xmmReg[z].xyzw = xyzw;
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xmmReg[z].isNeeded = 1;
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xmmReg[z].isTemp = 1;
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xmmReg[z].isTemp = (cloneWrite) ? 1 : 0;
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return z;
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}
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xmmReg[i].count = counter;
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@ -268,7 +279,10 @@ public:
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writeBackReg(x);
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if (vfReg >= 0) {
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if (writeBack) {
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mVUloadReg(x, (uptr)&vuRegs->VF[vfReg].UL[0], xyzw);
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if (needToLoad) {
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if (vfReg == 32) mVUloadReg(x, (uptr)&vuRegs->ACC.UL[0], xyzw);
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else mVUloadReg(x, (uptr)&vuRegs->VF[vfReg].UL[0], xyzw);
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}
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xmmReg[x].reg = vfWriteBack;
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xmmReg[x].count = counter;
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xmmReg[x].xyzw = xyzw;
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@ -276,8 +290,10 @@ public:
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xmmReg[x].isTemp = 1;
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}
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else {
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if (vfReg == 32) SSE_MOVAPS_M128_to_XMM((uptr)&vuRegs->ACC.UL[0], x);
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else SSE_MOVAPS_M128_to_XMM((uptr)&vuRegs->VF[vfReg].UL[0], x);
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if (needToLoad) {
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if (vfReg == 32) SSE_MOVAPS_M128_to_XMM(x, (uptr)&vuRegs->ACC.UL[0]);
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else SSE_MOVAPS_M128_to_XMM(x, (uptr)&vuRegs->VF[vfReg].UL[0]);
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}
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xmmReg[x].reg = vfReg;
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xmmReg[x].count = counter;
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xmmReg[x].xyzw = 0;
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@ -27,30 +27,31 @@
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#define SHIFT_XYZW(gprReg) { if (_XYZW_SS && modXYZW && !_W) { SHL32ItoR(gprReg, ADD_XYZW); } }
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// Note: If modXYZW is true, then it adjusts XYZW for Single Scalar operations
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microVUt(void) mVUupdateFlags(mV, int reg, int regT1, int regT2, int xyzw, bool modXYZW) {
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microVUt(void) mVUupdateFlags(mV, int reg, int tempX, int regT1, int xyzw, bool modXYZW) {
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int sReg, mReg = gprT1;
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static const u16 flipMask[16] = {0, 8, 4, 12, 2, 10, 6, 14, 1, 9, 5, 13, 3, 11, 7, 15};
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//SysPrintf("Status = %d; Mac = %d\n", sFLAG.doFlag, mFLAG.doFlag);
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if (mVUsFlagHack) { sFLAG.doFlag = 0; }
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if (!sFLAG.doFlag && !mFLAG.doFlag) { return; }
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if (!mFLAG.doFlag || (_XYZW_SS && modXYZW)) { regT1 = reg; }
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else { SSE2_PSHUFD_XMM_to_XMM(regT1, reg, 0x1B); } // Flip wzyx to xyzw
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if (!sFLAG.doFlag && !mFLAG.doFlag) { return; }
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if (!(!mFLAG.doFlag || (_XYZW_SS && modXYZW))) {
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SSE2_PSHUFD_XMM_to_XMM(reg, reg, 0x1B); // Flip wzyx to xyzw
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}
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if (sFLAG.doFlag) {
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getFlagReg(sReg, sFLAG.write); // Set sReg to valid GPR by Cur Flag Instance
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mVUallocSFLAGa(sReg, sFLAG.lastWrite); // Get Prev Status Flag
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if (sFLAG.doNonSticky) AND32ItoR(sReg, 0xfffc00ff); // Clear O,U,S,Z flags
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}
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if (regT1 < 0) { regT1 = mVU->regAlloc->allocReg(); }
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//-------------------------Check for Signed flags------------------------------
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// The following code makes sure the Signed Bit isn't set with Negative Zero
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SSE_XORPS_XMM_to_XMM(regT2, regT2); // Clear regT2
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SSE_CMPEQPS_XMM_to_XMM(regT2, regT1); // Set all F's if each vector is zero
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SSE_MOVMSKPS_XMM_to_R32(gprT2, regT2); // Used for Zero Flag Calculation
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SSE_ANDNPS_XMM_to_XMM(regT2, regT1);
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SSE_XORPS_XMM_to_XMM(regT1, regT1); // Clear regT2
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SSE_CMPEQPS_XMM_to_XMM(regT1, reg); // Set all F's if each vector is zero
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SSE_MOVMSKPS_XMM_to_R32(gprT2, regT1); // Used for Zero Flag Calculation
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SSE_ANDNPS_XMM_to_XMM(regT1, reg);
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SSE_MOVMSKPS_XMM_to_R32(mReg, regT2); // Move the sign bits of the t1reg
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SSE_MOVMSKPS_XMM_to_R32(mReg, regT1); // Move the sign bits of the t1reg
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AND32ItoR(mReg, AND_XYZW); // Grab "Is Signed" bits from the previous calculation
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SHL32ItoR(mReg, 4 + ADD_XYZW);
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@ -63,6 +64,9 @@ microVUt(void) mVUupdateFlags(mV, int reg, int regT1, int regT2, int xyzw, bool
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//-------------------------Write back flags------------------------------
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if (!(!mFLAG.doFlag || (_XYZW_SS && modXYZW))) {
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SSE2_PSHUFD_XMM_to_XMM(reg, reg, 0x1B); // Flip wzyx to xyzw
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}
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if (mFLAG.doFlag) mVUallocMFLAGb(mVU, mReg, mFLAG.write); // Set Mac Flag
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if (sFLAG.doFlag) {
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OR32RtoR (sReg, mReg);
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@ -463,22 +467,186 @@ static void (*SSE_SS[]) (x86SSERegType, x86SSERegType) = {
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SSE_MINSS_XMM_to_XMM // 4
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};
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void mVU_FMACa(microVU* mVU, int opCase, int opType, bool updateFlags) {
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int Fs, Ft;
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opCase1 { Ft = mVU->regAlloc->allocReg(_Ft_); if (_XYZW_SS && _X_Y_Z_W != 8) { SSE2_PSHUFD_XMM_to_XMM(Ft, Ft, shuffleXYZW(_X_Y_Z_W)); } }
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opCase2 { Ft = mVU->regAlloc->allocReg(_Ft_); mVU->regAlloc->clearNeeded(Ft); Ft = mVU->regAlloc->allocReg(); }
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void setupFtReg(microVU* mVU, int& Ft, int opCase) {
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opCase1 { Ft = mVU->regAlloc->allocReg(_Ft_); }
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opCase2 {
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if (!_XYZW_SS) {
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int tempFt = mVU->regAlloc->allocReg(_Ft_);
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Ft = mVU->regAlloc->allocReg();
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mVUunpack_xyzw(Ft, tempFt, _bc_);
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mVU->regAlloc->clearNeeded(tempFt);
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}
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else Ft = mVU->regAlloc->allocReg(_Ft_);
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}
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opCase3 { Ft = mVU->regAlloc->allocReg(); getIreg(Ft, 1); }
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opCase4 { Ft = mVU->regAlloc->allocReg(); getQreg(Ft); }
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}
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Fs = mVU->regAlloc->allocReg(_Fs_, 1, _X_Y_Z_W, _Fd_);
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void mVU_FMACa(microVU* mVU, int recPass, int opCase, int opType, bool isACC) {
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pass1 {
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opCase1 { mVUanalyzeFMAC1(mVU, ((isACC) ? 0 : _Fd_), _Fs_, _Ft_); }
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opCase2 { mVUanalyzeFMAC3(mVU, ((isACC) ? 0 : _Fd_), _Fs_, _Ft_); }
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opCase3 { mVUanalyzeFMAC1(mVU, ((isACC) ? 0 : _Fd_), _Fs_, 0); }
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opCase4 { mVUanalyzeFMAC1(mVU, ((isACC) ? 0 : _Fd_), _Fs_, 0); }
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if ((opType == 3) || (opType == 4)) { sFLAG.doFlag = 0; }
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}
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pass2 {
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int Fs, Ft, ACC;
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mVU->regAlloc->reset();
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setupFtReg(mVU, Ft, opCase);
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if (_XYZW_SS) SSE_SS[opType](Fs, Ft);
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else SSE_PS[opType](Fs, Ft);
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if (isACC) {
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ACC = mVU->regAlloc->allocReg(32, 1, 0xf, 32, 0, (_X_Y_Z_W!=0xf));
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Fs = mVU->regAlloc->allocReg(_Fs_, 1, _X_Y_Z_W, 0);
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if (_XYZW_SS && _X_Y_Z_W != 8) SSE2_PSHUFD_XMM_to_XMM(ACC, ACC, shuffleXYZW(_X_Y_Z_W));
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}
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else { Fs = mVU->regAlloc->allocReg(_Fs_, 1, _X_Y_Z_W, _Fd_); }
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opCase1 { if (_XYZW_SS && _X_Y_Z_W != 8) { SSE2_PSHUFD_XMM_to_XMM(Ft, Ft, shuffleXYZW(_X_Y_Z_W)); } }
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opCase1 { if (_XYZW_SS && _X_Y_Z_W != 8) { SSE2_PSHUFD_XMM_to_XMM(Ft, Ft, shuffleXYZW(_X_Y_Z_W)); } }
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opCase2 { if (_XYZW_SS && (!_bc_x)) { SSE2_PSHUFD_XMM_to_XMM(Ft, Ft, shuffleXYZW((1 << (3 - _bc_)))); } }
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mVU->regAlloc->clearNeeded(Ft);
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mVU->regAlloc->writeBackReg(Fs);
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if (_XYZW_SS) SSE_SS[opType](Fs, Ft);
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else SSE_PS[opType](Fs, Ft);
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opCase1 { if (_XYZW_SS && _X_Y_Z_W != 8) { SSE2_PSHUFD_XMM_to_XMM(Ft, Ft, shuffleXYZW(_X_Y_Z_W)); } }
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opCase2 { if (_XYZW_SS && (!_bc_x)) { SSE2_PSHUFD_XMM_to_XMM(Ft, Ft, shuffleXYZW((1 << (3 - _bc_)))); } }
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if (isACC) {
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if (_XYZW_SS) SSE_MOVSS_XMM_to_XMM(ACC, Fs);
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else mVUmergeRegs(ACC, Fs, _X_Y_Z_W);
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mVUupdateFlags(mVU, ACC, 0, Fs, _X_Y_Z_W, 1);
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if (_XYZW_SS && _X_Y_Z_W != 8) SSE2_PSHUFD_XMM_to_XMM(ACC, ACC, shuffleXYZW(_X_Y_Z_W));
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mVU->regAlloc->clearNeeded(ACC);
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}
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else mVUupdateFlags(mVU, Fs, 0, (((opCase==2)&&(!_XYZW_SS)) ? Ft : -1), _X_Y_Z_W, 1);
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if (isACC) SSE_MOVAPS_XMM_to_XMM(xmmACC, ACC); // For Testing
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mVU->regAlloc->clearNeeded(Ft);
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mVU->regAlloc->writeBackReg(Fs);
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mVU->regAlloc->flushAll(); // Flush All for Testing
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}
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}
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// MADDA/MSUBA
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void mVU_FMACb(microVU* mVU, int recPass, int opCase, int opType) {
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pass1 {
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opCase1 { mVUanalyzeFMAC1(mVU, 0, _Fs_, _Ft_); }
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opCase2 { mVUanalyzeFMAC3(mVU, 0, _Fs_, _Ft_); }
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opCase3 { mVUanalyzeFMAC1(mVU, 0, _Fs_, 0); }
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opCase4 { mVUanalyzeFMAC1(mVU, 0, _Fs_, 0); }
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}
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pass2 {
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int Fs, Ft, ACC;
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mVU->regAlloc->reset();
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setupFtReg(mVU, Ft, opCase);
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ACC = mVU->regAlloc->allocReg(32, 1, 0xf, 32, 0, 1);
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Fs = mVU->regAlloc->allocReg(_Fs_, 1, _X_Y_Z_W, 0);
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if (_XYZW_SS && _X_Y_Z_W != 8) { SSE2_PSHUFD_XMM_to_XMM(ACC, ACC, shuffleXYZW(_X_Y_Z_W)); }
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opCase1 { if (_XYZW_SS && _X_Y_Z_W != 8) { SSE2_PSHUFD_XMM_to_XMM(Ft, Ft, shuffleXYZW(_X_Y_Z_W)); } }
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opCase2 { if (_XYZW_SS && (!_bc_x)) { SSE2_PSHUFD_XMM_to_XMM(Ft, Ft, shuffleXYZW((1 << (3 - _bc_)))); } }
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if (_XYZW_SS) SSE_SS[2](Fs, Ft);
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else SSE_PS[2](Fs, Ft);
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opCase1 { if (_XYZW_SS && _X_Y_Z_W != 8) { SSE2_PSHUFD_XMM_to_XMM(Ft, Ft, shuffleXYZW(_X_Y_Z_W)); } }
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opCase2 { if (_XYZW_SS && (!_bc_x)) { SSE2_PSHUFD_XMM_to_XMM(Ft, Ft, shuffleXYZW((1 << (3 - _bc_)))); } }
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if (_XYZW_SS || _X_Y_Z_W == 0xf) {
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if (_XYZW_SS) SSE_SS[opType](ACC, Fs);
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else SSE_PS[opType](ACC, Fs);
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mVUupdateFlags(mVU, ACC, 0, Fs, _X_Y_Z_W, 1);
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if (_XYZW_SS && _X_Y_Z_W != 8) SSE2_PSHUFD_XMM_to_XMM(ACC, ACC, shuffleXYZW(_X_Y_Z_W));
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}
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else {
|
||||
int tempACC = mVU->regAlloc->allocReg();
|
||||
SSE_MOVAPS_XMM_to_XMM(tempACC, ACC);
|
||||
SSE_PS[opType](tempACC, Fs);
|
||||
mVUmergeRegs(ACC, tempACC, _X_Y_Z_W);
|
||||
mVU->regAlloc->clearNeeded(tempACC);
|
||||
}
|
||||
|
||||
SSE_MOVAPS_XMM_to_XMM(xmmACC, ACC); // For Testing
|
||||
mVU->regAlloc->clearNeeded(ACC);
|
||||
mVU->regAlloc->clearNeeded(Ft);
|
||||
mVU->regAlloc->clearReg(Fs);
|
||||
mVU->regAlloc->flushAll(); // Flush All for Testing
|
||||
}
|
||||
}
|
||||
|
||||
// MADD
|
||||
void mVU_FMACc(microVU* mVU, int recPass, int opCase) {
|
||||
pass1 {
|
||||
opCase1 { mVUanalyzeFMAC1(mVU, _Fd_, _Fs_, _Ft_); }
|
||||
opCase2 { mVUanalyzeFMAC3(mVU, _Fd_, _Fs_, _Ft_); }
|
||||
opCase3 { mVUanalyzeFMAC1(mVU, _Fd_, _Fs_, 0); }
|
||||
opCase4 { mVUanalyzeFMAC1(mVU, _Fd_, _Fs_, 0); }
|
||||
}
|
||||
pass2 {
|
||||
int Fs, Ft, ACC;
|
||||
mVU->regAlloc->reset();
|
||||
setupFtReg(mVU, Ft, opCase);
|
||||
|
||||
ACC = mVU->regAlloc->allocReg(32);
|
||||
Fs = mVU->regAlloc->allocReg(_Fs_, 1, _X_Y_Z_W, _Fd_);
|
||||
|
||||
if (_XYZW_SS && _X_Y_Z_W != 8) { SSE2_PSHUFD_XMM_to_XMM(ACC, ACC, shuffleXYZW(_X_Y_Z_W)); }
|
||||
opCase1 { if (_XYZW_SS && _X_Y_Z_W != 8) { SSE2_PSHUFD_XMM_to_XMM(Ft, Ft, shuffleXYZW(_X_Y_Z_W)); } }
|
||||
opCase2 { if (_XYZW_SS && (!_bc_x)) { SSE2_PSHUFD_XMM_to_XMM(Ft, Ft, shuffleXYZW((1 << (3 - _bc_)))); } }
|
||||
|
||||
if (_XYZW_SS) { SSE_SS[2](Fs, Ft); SSE_SS[0](Fs, ACC); }
|
||||
else { SSE_PS[2](Fs, Ft); SSE_PS[0](Fs, ACC); }
|
||||
|
||||
mVUupdateFlags(mVU, Fs, 0, -1, _X_Y_Z_W, 1);
|
||||
|
||||
if (_XYZW_SS && _X_Y_Z_W != 8) { SSE2_PSHUFD_XMM_to_XMM(ACC, ACC, shuffleXYZW(_X_Y_Z_W)); }
|
||||
opCase1 { if (_XYZW_SS && _X_Y_Z_W != 8) { SSE2_PSHUFD_XMM_to_XMM(Ft, Ft, shuffleXYZW(_X_Y_Z_W)); } }
|
||||
opCase2 { if (_XYZW_SS && (!_bc_x)) { SSE2_PSHUFD_XMM_to_XMM(Ft, Ft, shuffleXYZW((1 << (3 - _bc_)))); } }
|
||||
|
||||
mVU->regAlloc->clearNeeded(ACC);
|
||||
mVU->regAlloc->clearNeeded(Ft);
|
||||
mVU->regAlloc->writeBackReg(Fs);
|
||||
mVU->regAlloc->flushAll(); // Flush All for Testing
|
||||
}
|
||||
}
|
||||
|
||||
// MSUB
|
||||
void mVU_FMACd(microVU* mVU, int recPass, int opCase) {
|
||||
pass1 {
|
||||
opCase1 { mVUanalyzeFMAC1(mVU, _Fd_, _Fs_, _Ft_); }
|
||||
opCase2 { mVUanalyzeFMAC3(mVU, _Fd_, _Fs_, _Ft_); }
|
||||
opCase3 { mVUanalyzeFMAC1(mVU, _Fd_, _Fs_, 0); }
|
||||
opCase4 { mVUanalyzeFMAC1(mVU, _Fd_, _Fs_, 0); }
|
||||
}
|
||||
pass2 {
|
||||
int Fs, Ft, Fd, ACC;
|
||||
mVU->regAlloc->reset();
|
||||
setupFtReg(mVU, Ft, opCase);
|
||||
|
||||
ACC = mVU->regAlloc->allocReg(32);
|
||||
Fs = mVU->regAlloc->allocReg(_Fs_, 1, _X_Y_Z_W, 0);
|
||||
Fd = mVU->regAlloc->allocReg(_Fd_, 1, _X_Y_Z_W, _Fd_, 1, 0);
|
||||
|
||||
if (_XYZW_SS && _X_Y_Z_W != 8) { SSE2_PSHUFD_XMM_to_XMM(ACC, ACC, shuffleXYZW(_X_Y_Z_W)); }
|
||||
else { SSE_MOVAPS_XMM_to_XMM (Fd, ACC); }
|
||||
opCase1 { if (_XYZW_SS && _X_Y_Z_W != 8) { SSE2_PSHUFD_XMM_to_XMM(Ft, Ft, shuffleXYZW(_X_Y_Z_W)); } }
|
||||
opCase2 { if (_XYZW_SS && (!_bc_x)) { SSE2_PSHUFD_XMM_to_XMM(Ft, Ft, shuffleXYZW((1 << (3 - _bc_)))); } }
|
||||
|
||||
if (_XYZW_SS) { SSE_SS[2](Fs, Ft); SSE_SS[0](Fd, Fs); }
|
||||
else { SSE_PS[2](Fs, Ft); SSE_PS[0](Fd, Fs); }
|
||||
|
||||
mVUupdateFlags(mVU, Fd, 0, Fs, _X_Y_Z_W, 1);
|
||||
|
||||
opCase1 { if (_XYZW_SS && _X_Y_Z_W != 8) { SSE2_PSHUFD_XMM_to_XMM(Ft, Ft, shuffleXYZW(_X_Y_Z_W)); } }
|
||||
opCase2 { if (_XYZW_SS && (!_bc_x)) { SSE2_PSHUFD_XMM_to_XMM(Ft, Ft, shuffleXYZW((1 << (3 - _bc_)))); } }
|
||||
|
||||
mVU->regAlloc->clearNeeded(ACC);
|
||||
mVU->regAlloc->clearNeeded(Ft);
|
||||
mVU->regAlloc->clearReg(Fs);
|
||||
mVU->regAlloc->writeBackReg(Fd);
|
||||
mVU->regAlloc->flushAll(); // Flush All for Testing
|
||||
}
|
||||
}
|
||||
|
||||
//------------------------------------------------------------------
|
||||
|
|
@ -495,6 +663,91 @@ mVUop(mVU_ABS) {
|
|||
}
|
||||
pass3 { mVUlog("ABS"); mVUlogFtFs(); }
|
||||
}
|
||||
/*
|
||||
mVUop(mVU_ADD) { mVU_FMACa(mVU, recPass, 1, 0, 0); }
|
||||
mVUop(mVU_ADDi) { mVU_FMACa(mVU, recPass, 3, 0, 0); }
|
||||
mVUop(mVU_ADDq) { mVU_FMACa(mVU, recPass, 4, 0, 0); }
|
||||
mVUop(mVU_ADDx) { mVU_FMACa(mVU, recPass, 2, 0, 0); }
|
||||
mVUop(mVU_ADDy) { mVU_FMACa(mVU, recPass, 2, 0, 0); }
|
||||
mVUop(mVU_ADDz) { mVU_FMACa(mVU, recPass, 2, 0, 0); }
|
||||
mVUop(mVU_ADDw) { mVU_FMACa(mVU, recPass, 2, 0, 0); }
|
||||
mVUop(mVU_ADDA) { mVU_FMACa(mVU, recPass, 1, 0, 1); }
|
||||
mVUop(mVU_ADDAi) { mVU_FMACa(mVU, recPass, 3, 0, 1); }
|
||||
mVUop(mVU_ADDAq) { mVU_FMACa(mVU, recPass, 4, 0, 1); }
|
||||
mVUop(mVU_ADDAx) { mVU_FMACa(mVU, recPass, 2, 0, 1); }
|
||||
mVUop(mVU_ADDAy) { mVU_FMACa(mVU, recPass, 2, 0, 1); }
|
||||
mVUop(mVU_ADDAz) { mVU_FMACa(mVU, recPass, 2, 0, 1); }
|
||||
mVUop(mVU_ADDAw) { mVU_FMACa(mVU, recPass, 2, 0, 1); }
|
||||
mVUop(mVU_SUB) { mVU_FMACa(mVU, recPass, 1, 1, 0); }
|
||||
mVUop(mVU_SUBi) { mVU_FMACa(mVU, recPass, 3, 1, 0); }
|
||||
mVUop(mVU_SUBq) { mVU_FMACa(mVU, recPass, 4, 1, 0); }
|
||||
mVUop(mVU_SUBx) { mVU_FMACa(mVU, recPass, 2, 1, 0); }
|
||||
mVUop(mVU_SUBy) { mVU_FMACa(mVU, recPass, 2, 1, 0); }
|
||||
mVUop(mVU_SUBz) { mVU_FMACa(mVU, recPass, 2, 1, 0); }
|
||||
mVUop(mVU_SUBw) { mVU_FMACa(mVU, recPass, 2, 1, 0); }
|
||||
mVUop(mVU_SUBA) { mVU_FMACa(mVU, recPass, 1, 1, 1); }
|
||||
mVUop(mVU_SUBAi) { mVU_FMACa(mVU, recPass, 3, 1, 1); }
|
||||
mVUop(mVU_SUBAq) { mVU_FMACa(mVU, recPass, 4, 1, 1); }
|
||||
mVUop(mVU_SUBAx) { mVU_FMACa(mVU, recPass, 2, 1, 1); }
|
||||
mVUop(mVU_SUBAy) { mVU_FMACa(mVU, recPass, 2, 1, 1); }
|
||||
mVUop(mVU_SUBAz) { mVU_FMACa(mVU, recPass, 2, 1, 1); }
|
||||
mVUop(mVU_SUBAw) { mVU_FMACa(mVU, recPass, 2, 1, 1); }
|
||||
mVUop(mVU_MUL) { mVU_FMACa(mVU, recPass, 1, 2, 0); }
|
||||
mVUop(mVU_MULi) { mVU_FMACa(mVU, recPass, 3, 2, 0); }
|
||||
mVUop(mVU_MULq) { mVU_FMACa(mVU, recPass, 4, 2, 0); }
|
||||
mVUop(mVU_MULx) { mVU_FMACa(mVU, recPass, 2, 2, 0); }
|
||||
mVUop(mVU_MULy) { mVU_FMACa(mVU, recPass, 2, 2, 0); }
|
||||
mVUop(mVU_MULz) { mVU_FMACa(mVU, recPass, 2, 2, 0); }
|
||||
mVUop(mVU_MULw) { mVU_FMACa(mVU, recPass, 2, 2, 0); }
|
||||
mVUop(mVU_MULA) { mVU_FMACa(mVU, recPass, 1, 2, 1); }
|
||||
mVUop(mVU_MULAi) { mVU_FMACa(mVU, recPass, 3, 2, 1); }
|
||||
mVUop(mVU_MULAq) { mVU_FMACa(mVU, recPass, 4, 2, 1); }
|
||||
mVUop(mVU_MULAx) { mVU_FMACa(mVU, recPass, 2, 2, 1); }
|
||||
mVUop(mVU_MULAy) { mVU_FMACa(mVU, recPass, 2, 2, 1); }
|
||||
mVUop(mVU_MULAz) { mVU_FMACa(mVU, recPass, 2, 2, 1); }
|
||||
mVUop(mVU_MULAw) { mVU_FMACa(mVU, recPass, 2, 2, 1); }
|
||||
mVUop(mVU_MADD) { mVU_FMACc(mVU, recPass, 1); }
|
||||
mVUop(mVU_MADDi) { mVU_FMACc(mVU, recPass, 3); }
|
||||
mVUop(mVU_MADDq) { mVU_FMACc(mVU, recPass, 4); }
|
||||
mVUop(mVU_MADDx) { mVU_FMACc(mVU, recPass, 2); }
|
||||
mVUop(mVU_MADDy) { mVU_FMACc(mVU, recPass, 2); }
|
||||
mVUop(mVU_MADDz) { mVU_FMACc(mVU, recPass, 2); }
|
||||
mVUop(mVU_MADDw) { mVU_FMACc(mVU, recPass, 2); }
|
||||
mVUop(mVU_MADDA) { mVU_FMACb(mVU, recPass, 1, 0); }
|
||||
mVUop(mVU_MADDAi) { mVU_FMACb(mVU, recPass, 3, 0); }
|
||||
mVUop(mVU_MADDAq) { mVU_FMACb(mVU, recPass, 4, 0); }
|
||||
mVUop(mVU_MADDAx) { mVU_FMACb(mVU, recPass, 2, 0); }
|
||||
mVUop(mVU_MADDAy) { mVU_FMACb(mVU, recPass, 2, 0); }
|
||||
mVUop(mVU_MADDAz) { mVU_FMACb(mVU, recPass, 2, 0); }
|
||||
mVUop(mVU_MADDAw) { mVU_FMACb(mVU, recPass, 2, 0); }
|
||||
mVUop(mVU_MSUB) { mVU_FMACd(mVU, recPass, 1); }
|
||||
mVUop(mVU_MSUBi) { mVU_FMACd(mVU, recPass, 3); }
|
||||
mVUop(mVU_MSUBq) { mVU_FMACd(mVU, recPass, 4); }
|
||||
mVUop(mVU_MSUBx) { mVU_FMACd(mVU, recPass, 2); }
|
||||
mVUop(mVU_MSUBy) { mVU_FMACd(mVU, recPass, 2); }
|
||||
mVUop(mVU_MSUBz) { mVU_FMACd(mVU, recPass, 2); }
|
||||
mVUop(mVU_MSUBw) { mVU_FMACd(mVU, recPass, 2); }
|
||||
mVUop(mVU_MSUBA) { mVU_FMACb(mVU, recPass, 1, 1); }
|
||||
mVUop(mVU_MSUBAi) { mVU_FMACb(mVU, recPass, 3, 1); }
|
||||
mVUop(mVU_MSUBAq) { mVU_FMACb(mVU, recPass, 4, 1); }
|
||||
mVUop(mVU_MSUBAx) { mVU_FMACb(mVU, recPass, 2, 1); }
|
||||
mVUop(mVU_MSUBAy) { mVU_FMACb(mVU, recPass, 2, 1); }
|
||||
mVUop(mVU_MSUBAz) { mVU_FMACb(mVU, recPass, 2, 1); }
|
||||
mVUop(mVU_MSUBAw) { mVU_FMACb(mVU, recPass, 2, 1); }
|
||||
mVUop(mVU_MAX) { mVU_FMACa(mVU, recPass, 1, 3, 0); }
|
||||
mVUop(mVU_MAXi) { mVU_FMACa(mVU, recPass, 3, 3, 0); }
|
||||
mVUop(mVU_MAXx) { mVU_FMACa(mVU, recPass, 2, 3, 0); }
|
||||
mVUop(mVU_MAXy) { mVU_FMACa(mVU, recPass, 2, 3, 0); }
|
||||
mVUop(mVU_MAXz) { mVU_FMACa(mVU, recPass, 2, 3, 0); }
|
||||
mVUop(mVU_MAXw) { mVU_FMACa(mVU, recPass, 2, 3, 0); }
|
||||
mVUop(mVU_MINI) { mVU_FMACa(mVU, recPass, 1, 4, 0); }
|
||||
mVUop(mVU_MINIi) { mVU_FMACa(mVU, recPass, 3, 4, 0); }
|
||||
mVUop(mVU_MINIx) { mVU_FMACa(mVU, recPass, 2, 4, 0); }
|
||||
mVUop(mVU_MINIy) { mVU_FMACa(mVU, recPass, 2, 4, 0); }
|
||||
mVUop(mVU_MINIz) { mVU_FMACa(mVU, recPass, 2, 4, 0); }
|
||||
mVUop(mVU_MINIw) { mVU_FMACa(mVU, recPass, 2, 4, 0); }
|
||||
*/
|
||||
|
||||
mVUop(mVU_ADD) { mVU_FMAC1 (ADD, "ADD"); }
|
||||
mVUop(mVU_ADDi) { mVU_FMAC6 (ADD2, "ADDi"); }
|
||||
mVUop(mVU_ADDq) { mVU_FMAC22(ADD, "ADDq"); }
|
||||
|
|
|
|||
Loading…
Reference in New Issue