mirror of https://github.com/PCSX2/pcsx2.git
ee: update cache emulation for 64 bits
This commit is contained in:
TellowKrinkle
refractionpcsx2
parent
82ea30cf3f
commit
6ad8563c16
628
pcsx2/Cache.cpp
628
pcsx2/Cache.cpp
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@ -22,253 +22,293 @@
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using namespace R5900;
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using namespace vtlb_private;
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_cacheS pCache[64];
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// The lower parts of a cache tags structure is as follows:
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// 31 - 12: The physical address cache tag.
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// 11 - 7: Unused.
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// 6: Dirty flag.
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// 5: Valid flag.
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// 4: LRF flag - least recently filled flag.
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// 3: Lock flag.
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// 2-0: Unused.
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// 0xFFF - 12 bits, so x & ~0xFFF = the physical address cache tag.
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const u32 DIRTY_FLAG = 0x40;
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const u32 VALID_FLAG = 0x20;
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const u32 LRF_FLAG = 0x10;
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const u32 LOCK_FLAG = 0x8;
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// TODO: You can't assume the vtlb entry is in both states at once!
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int getFreeCache(u32 mem, int mode, int * way)
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namespace
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{
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int number = 0;
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const int i = (mem >> 6) & 0x3F;
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const auto vmv = vtlbdata.vmap[mem >> VTLB_PAGE_BITS];
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union alignas(64) CacheData
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{
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u8 bytes[64];
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constexpr CacheData(): bytes{0} {}
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};
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struct CacheTag
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{
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uptr rawValue = 0;
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CacheTag() = default;
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// The lower parts of a cache tags structure is as follows:
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// 31 - 12: The physical address cache tag.
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// 11 - 7: Unused.
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// 6: Dirty flag.
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// 5: Valid flag.
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// 4: LRF flag - least recently filled flag.
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// 3: Lock flag.
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// 2-0: Unused.
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enum Flags : decltype(rawValue)
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{
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DIRTY_FLAG = 0x40,
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VALID_FLAG = 0x20,
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LRF_FLAG = 0x10,
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LOCK_FLAG = 0x8,
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ALL_FLAGS = 0xFFF
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};
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int flags() const
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{
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return rawValue & ALL_FLAGS;
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}
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bool isValid() const { return rawValue & VALID_FLAG; }
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bool isDirty() const { return rawValue & DIRTY_FLAG; }
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bool lrf() const { return rawValue & LRF_FLAG; }
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bool isLocked() const { return rawValue & LOCK_FLAG; }
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bool isDirtyAndValid() const
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{
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return (rawValue & (DIRTY_FLAG | VALID_FLAG)) == (DIRTY_FLAG | VALID_FLAG);
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}
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void setValid() { rawValue |= VALID_FLAG; }
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void setDirty() { rawValue |= DIRTY_FLAG; }
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void setLocked() { rawValue |= LOCK_FLAG; }
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void clearValid() { rawValue &= ~VALID_FLAG; }
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void clearDirty() { rawValue &= ~DIRTY_FLAG; }
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void clearLocked() { rawValue &= ~LOCK_FLAG; }
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void toggleLRF() { rawValue ^= LRF_FLAG; }
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uptr addr() const { return rawValue & ~ALL_FLAGS; }
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void setAddr(uptr addr)
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{
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rawValue &= ALL_FLAGS;
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rawValue |= (addr & ~ALL_FLAGS);
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}
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bool matches(uptr other) const
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{
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return isValid() && addr() == (other & ~ALL_FLAGS);
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}
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void clear()
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{
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rawValue &= LRF_FLAG;
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}
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};
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struct CacheLine
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{
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CacheTag& tag;
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CacheData& data;
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int set;
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uptr addr()
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{
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return tag.addr() | (set << 6);
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}
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void writeBackIfNeeded()
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{
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if (!tag.isDirtyAndValid())
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return;
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uptr target = addr();
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CACHE_LOG("Write back at %zx", target);
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*reinterpret_cast<CacheData*>(target) = data;
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tag.clearDirty();
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}
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void load(uptr ppf)
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{
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pxAssertMsg(!tag.isDirtyAndValid(), "Loaded a value into cache without writing back the old one!");
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tag.setAddr(ppf);
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data = *reinterpret_cast<CacheData*>(ppf & ~0x3FULL);
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tag.setValid();
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tag.clearDirty();
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}
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void clear()
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{
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tag.clear();
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data = CacheData();
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}
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};
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struct CacheSet
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{
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CacheTag tags[2];
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CacheData data[2];
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};
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struct Cache
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{
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CacheSet sets[64];
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int setIdxFor(u32 vaddr) const
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{
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return (vaddr >> 6) & 0x3F;
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}
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CacheLine lineAt(int idx, int way)
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{
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return { sets[idx].tags[way], sets[idx].data[way], idx };
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}
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};
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static Cache cache;
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}
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void resetCache()
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{
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memzero(cache);
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}
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static bool findInCache(const CacheSet& set, uptr ppf, int* way)
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{
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auto check = [&](int checkWay) -> bool
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{
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if (!set.tags[checkWay].matches(ppf))
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return false;
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*way = checkWay;
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return true;
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};
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return check(0) || check(1);
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}
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static int getFreeCache(u32 mem, int* way)
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{
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const int setIdx = cache.setIdxFor(mem);
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CacheSet& set = cache.sets[setIdx];
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VTLBVirtual vmv = vtlbdata.vmap[mem >> VTLB_PAGE_BITS];
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pxAssertMsg(!vmv.isHandler(mem), "Cache currently only supports non-handler addresses!");
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uptr ppf = vmv.assumePtr(mem);
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const u32 paddr = vmv.assumeHandlerGetPAddr(mem);
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if((cpuRegs.CP0.n.Config & 0x10000) == 0) CACHE_LOG("Cache off!");
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if ((pCache[i].tag[0] & ~0xFFF) == (paddr & ~0xFFF) && (pCache[i].tag[0] & VALID_FLAG))
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if((cpuRegs.CP0.n.Config & 0x10000) == 0)
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CACHE_LOG("Cache off!");
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if (findInCache(set, ppf, way))
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{
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*way = 0;
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if (pCache[i].tag[0] & LOCK_FLAG) CACHE_LOG("Index %x Way %x Locked!!", i, 0);
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return i;
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if (set.tags[*way].isLocked())
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CACHE_LOG("Index %x Way %x Locked!!", setIdx, *way);
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}
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else if((pCache[i].tag[1] & ~0xFFF) == (paddr & ~0xFFF) && (pCache[i].tag[1] & VALID_FLAG))
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{
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*way = 1;
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if (pCache[i].tag[1] & LOCK_FLAG) CACHE_LOG("Index %x Way %x Locked!!", i, 1);
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return i;
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}
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number = (((pCache[i].tag[0]) & LRF_FLAG) ^ ((pCache[i].tag[1]) & LRF_FLAG)) >> 4;
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ppf = (ppf & ~0x3F);
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if ((pCache[i].tag[number] & (DIRTY_FLAG | VALID_FLAG)) == (DIRTY_FLAG | VALID_FLAG)) // Dirty Write
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{
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s32 oldppf = (pCache[i].tag[number] & ~0x80000fff) + (mem & 0xFC0);
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CACHE_LOG("Dirty cache fill! PPF %x", oldppf);
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*reinterpret_cast<mem64_t*>(oldppf) = pCache[i].data[number][0].b8._u64[0];
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*reinterpret_cast<mem64_t*>(oldppf+8) = pCache[i].data[number][0].b8._u64[1];
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*reinterpret_cast<mem64_t*>(oldppf+16) = pCache[i].data[number][1].b8._u64[0];
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*reinterpret_cast<mem64_t*>(oldppf+24) = pCache[i].data[number][1].b8._u64[1];
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*reinterpret_cast<mem64_t*>(oldppf+32) = pCache[i].data[number][2].b8._u64[0];
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*reinterpret_cast<mem64_t*>(oldppf+40) = pCache[i].data[number][2].b8._u64[1];
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*reinterpret_cast<mem64_t*>(oldppf+48) = pCache[i].data[number][3].b8._u64[0];
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*reinterpret_cast<mem64_t*>(oldppf+56) = pCache[i].data[number][3].b8._u64[1];
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pCache[i].tag[number] &= ~DIRTY_FLAG;
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}
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pCache[i].data[number][0].b8._u64[0] = *reinterpret_cast<mem64_t*>(ppf);
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pCache[i].data[number][0].b8._u64[1] = *reinterpret_cast<mem64_t*>(ppf+8);
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pCache[i].data[number][1].b8._u64[0] = *reinterpret_cast<mem64_t*>(ppf+16);
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pCache[i].data[number][1].b8._u64[1] = *reinterpret_cast<mem64_t*>(ppf+24);
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pCache[i].data[number][2].b8._u64[0] = *reinterpret_cast<mem64_t*>(ppf+32);
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pCache[i].data[number][2].b8._u64[1] = *reinterpret_cast<mem64_t*>(ppf+40);
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pCache[i].data[number][3].b8._u64[0] = *reinterpret_cast<mem64_t*>(ppf+48);
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pCache[i].data[number][3].b8._u64[1] = *reinterpret_cast<mem64_t*>(ppf+56);
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*way = number;
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pCache[i].tag[number] |= VALID_FLAG;
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pCache[i].tag[number] &= 0xFFF;
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pCache[i].tag[number] |= paddr & ~0xFFF;
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if(pCache[i].tag[number] & LRF_FLAG)
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pCache[i].tag[number] &= ~LRF_FLAG;
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else
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pCache[i].tag[number] |= LRF_FLAG;
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{
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int newWay = set.tags[0].lrf() ^ set.tags[1].lrf();
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*way = newWay;
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CacheLine line = cache.lineAt(setIdx, newWay);
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return i;
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line.writeBackIfNeeded();
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line.load(ppf);
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line.tag.toggleLRF();
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}
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return setIdx;
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}
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template <typename Int>
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void writeCache(u32 mem, Int value)
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{
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int way = 0;
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const int idx = getFreeCache(mem, &way);
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CACHE_LOG("writeCache%d %8.8x adding to %d, way %d, value %llx", 8 * sizeof(value), mem, idx, way, value);
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CacheLine line = cache.lineAt(idx, way);
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line.tag.setDirty(); // Set dirty bit for writes;
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u32 aligned = mem & ~(sizeof(value) - 1);
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*reinterpret_cast<Int*>(&line.data.bytes[aligned & 0x3f]) = value;
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}
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void writeCache8(u32 mem, u8 value)
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{
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int number = 0;
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const int i = getFreeCache(mem, 1, &number);
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if (i == -1)
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{
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auto vmv = vtlbdata.vmap[mem >> VTLB_PAGE_BITS];
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*reinterpret_cast<mem8_t*>(vmv.assumePtr(mem)) = value;
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return;
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}
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CACHE_LOG("writeCache8 %8.8x adding to %d, way %d, value %x", mem, i, number, value);
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pCache[i].tag[number] |= DIRTY_FLAG; // Set Dirty Bit if mode == write
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pCache[i].data[number][(mem >> 4) & 0x3].b8._u8[(mem & 0xf)] = value;
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writeCache<u8>(mem, value);
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}
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void writeCache16(u32 mem, u16 value)
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{
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int number = 0;
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const int i = getFreeCache(mem, 1, &number);
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if (i == -1)
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{
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auto vmv = vtlbdata.vmap[mem >> VTLB_PAGE_BITS];
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*reinterpret_cast<mem16_t*>(vmv.assumePtr(mem)) = value;
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return;
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}
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CACHE_LOG("writeCache16 %8.8x adding to %d, way %d, value %x", mem, i, number, value);
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pCache[i].tag[number] |= DIRTY_FLAG; // Set Dirty Bit if mode == write
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pCache[i].data[number][(mem >> 4) & 0x3].b8._u16[(mem & 0xf) >> 1] = value;
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writeCache<u16>(mem, value);
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}
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void writeCache32(u32 mem, u32 value)
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{
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int number = 0;
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const int i = getFreeCache(mem, 1, &number);
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if (i == -1)
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{
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auto vmv = vtlbdata.vmap[mem >> VTLB_PAGE_BITS];
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*reinterpret_cast<mem32_t*>(vmv.assumePtr(mem)) = value;
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return;
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}
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CACHE_LOG("writeCache32 %8.8x adding to %d, way %d, value %x", mem, i, number, value);
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pCache[i].tag[number] |= DIRTY_FLAG; // Set Dirty Bit if mode == write
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pCache[i].data[number][(mem >> 4) & 0x3].b8._u32[(mem & 0xf) >> 2] = value;
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writeCache<u32>(mem, value);
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}
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void writeCache64(u32 mem, const u64 value)
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{
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int number = 0;
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const int i = getFreeCache(mem, 1, &number);
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if (i == -1)
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{
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auto vmv = vtlbdata.vmap[mem >> VTLB_PAGE_BITS];
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*reinterpret_cast<mem64_t*>(vmv.assumePtr(mem)) = value;
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return;
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}
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CACHE_LOG("writeCache64 %8.8x adding to %d, way %d, value %x", mem, i,number,value);
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pCache[i].tag[number] |= DIRTY_FLAG; // Set Dirty Bit if mode == write
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pCache[i].data[number][(mem >> 4) & 0x3].b8._u64[(mem & 0xf) >> 3] = value;
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writeCache<u64>(mem, value);
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}
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void writeCache128(u32 mem, const mem128_t* value)
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{
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int number = 0;
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const int i = getFreeCache(mem, 1, &number);
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int way = 0;
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const int idx = getFreeCache(mem, &way);
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if (i == -1)
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{
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auto vmv = vtlbdata.vmap[mem >> VTLB_PAGE_BITS];
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auto ptr = reinterpret_cast<mem64_t*>(vmv.assumePtr(mem));
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ptr[0] = value->lo;
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ptr[1] = value->hi;
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return;
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}
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CACHE_LOG("writeCache128 %8.8x adding to %d way %x tag %x vallo = %x_%x valhi = %x_%x", mem, i, number, pCache[i].tag[number], value->lo, value->hi);
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pCache[i].tag[number] |= DIRTY_FLAG; // Set Dirty Bit if mode == write
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pCache[i].data[number][(mem>>4) & 0x3].b8._u64[0] = value->lo;
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pCache[i].data[number][(mem>>4) & 0x3].b8._u64[1] = value->hi;
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CACHE_LOG("writeCache128 %8.8x adding to %d, way %x, lo %x, hi %x", mem, idx, way, value->lo, value->hi);
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CacheLine line = cache.lineAt(idx, way);
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line.tag.setDirty(); // Set dirty bit for writes;
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u32 aligned = mem & ~0xF;
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*reinterpret_cast<mem128_t*>(&line.data.bytes[aligned & 0x3f]) = *value;
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}
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template <typename Int>
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Int readCache(u32 mem)
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{
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int way = 0;
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const int idx = getFreeCache(mem, &way);
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CacheLine line = cache.lineAt(idx, way);
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u32 aligned = mem & ~(sizeof(Int) - 1);
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Int value = *reinterpret_cast<Int*>(&line.data.bytes[aligned & 0x3f]);
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CACHE_LOG("readCache%d %8.8x from %d, way %d, value %llx", 8 * sizeof(value), mem, idx, way, value);
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return value;
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}
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u8 readCache8(u32 mem)
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{
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int number = 0;
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const int i = getFreeCache(mem, 0, &number);
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if (i == -1)
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{
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auto vmv = vtlbdata.vmap[mem >> VTLB_PAGE_BITS];
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return *reinterpret_cast<u8*>(vmv.assumePtr(mem));
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}
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CACHE_LOG("readCache %8.8x from %d, way %d QW %x u8 part %x Really Reading %x", mem, i, number, (mem >> 4) & 0x3, (mem & 0xf) >> 2, (u32)pCache[i].data[number][(mem >> 4) & 0x3].b8._u8[(mem & 0xf)]);
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return pCache[i].data[number][(mem >> 4) & 0x3].b8._u8[(mem & 0xf)];
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return readCache<u8>(mem);
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}
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u16 readCache16(u32 mem)
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{
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int number = 0;
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const int i = getFreeCache(mem, 0, &number);
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if (i == -1)
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{
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auto vmv = vtlbdata.vmap[mem >> VTLB_PAGE_BITS];
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return *reinterpret_cast<u16*>(vmv.assumePtr(mem));
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}
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CACHE_LOG("readCache %8.8x from %d, way %d QW %x u16 part %x Really Reading %x", mem, i, number, (mem >> 4) & 0x3, (mem & 0xf) >> 2, (u32)pCache[i].data[number][(mem >> 4) & 0x3].b8._u16[(mem & 0xf) >> 1]);
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return pCache[i].data[number][(mem >> 4) & 0x3].b8._u16[(mem & 0xf) >> 1];
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return readCache<u16>(mem);
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}
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u32 readCache32(u32 mem)
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{
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int number = 0;
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const int i = getFreeCache(mem, 0, &number);
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if (i == -1)
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{
|
||||
auto vmv = vtlbdata.vmap[mem >> VTLB_PAGE_BITS];
|
||||
return *reinterpret_cast<u32*>(vmv.assumePtr(mem));
|
||||
}
|
||||
|
||||
CACHE_LOG("readCache %8.8x from %d, way %d QW %x u32 part %x Really Reading %x", mem, i, number, (mem >> 4) & 0x3, (mem & 0xf) >> 2, (u32)pCache[i].data[number][(mem >> 4) & 0x3].b8._u32[(mem & 0xf) >> 2]);
|
||||
return pCache[i].data[number][(mem >> 4) & 0x3].b8._u32[(mem & 0xf) >> 2];
|
||||
return readCache<u32>(mem);
|
||||
}
|
||||
|
||||
u64 readCache64(u32 mem)
|
||||
{
|
||||
int number = 0;
|
||||
int i = getFreeCache(mem, 0, &number);
|
||||
|
||||
if (i == -1)
|
||||
{
|
||||
auto vmv = vtlbdata.vmap[mem >> VTLB_PAGE_BITS];
|
||||
return *reinterpret_cast<u64*>(vmv.assumePtr(mem));
|
||||
}
|
||||
|
||||
CACHE_LOG("readCache %8.8x from %d, way %d QW %x u64 part %x Really Reading %x_%x", mem, i, number, (mem >> 4) & 0x3, (mem & 0xf) >> 2, pCache[i].data[number][(mem >> 4) & 0x3].b8._u64[(mem & 0xf) >> 3]);
|
||||
return pCache[i].data[number][(mem >> 4) & 0x3].b8._u64[(mem & 0xf) >> 3];
|
||||
return readCache<u64>(mem);
|
||||
}
|
||||
|
||||
__forceinline void clear_cache(int index, int way)
|
||||
template <typename Op>
|
||||
void doCacheHitOp(u32 addr, const char* name, Op op)
|
||||
{
|
||||
pCache[index].tag[way] &= LRF_FLAG;
|
||||
const int index = cache.setIdxFor(addr);
|
||||
CacheSet& set = cache.sets[index];
|
||||
VTLBVirtual vmv = vtlbdata.vmap[addr >> VTLB_PAGE_BITS];
|
||||
uptr ppf = vmv.assumePtr(addr);
|
||||
int way;
|
||||
|
||||
pCache[index].data[way][0].b8._u64[0] = 0;
|
||||
pCache[index].data[way][0].b8._u64[1] = 0;
|
||||
if (!findInCache(set, ppf, &way))
|
||||
{
|
||||
CACHE_LOG("CACHE %s NO HIT addr %x, index %d, tag0 %zx tag1 %zx", name, addr, index, set.tags[0].rawValue, set.tags[1].rawValue);
|
||||
return;
|
||||
}
|
||||
|
||||
pCache[index].data[way][1].b8._u64[0] = 0;
|
||||
pCache[index].data[way][1].b8._u64[1] = 0;
|
||||
CACHE_LOG("CACHE %s addr %x, index %d, way %d, flags %x OP %x", name, addr, index, way, set.tags[way].flags(), cpuRegs.code);
|
||||
|
||||
pCache[index].data[way][2].b8._u64[0] = 0;
|
||||
pCache[index].data[way][2].b8._u64[1] = 0;
|
||||
|
||||
pCache[index].data[way][3].b8._u64[0] = 0;
|
||||
pCache[index].data[way][3].b8._u64[1] = 0;
|
||||
op(cache.lineAt(index, way));
|
||||
}
|
||||
|
||||
namespace R5900 {
|
||||
|
|
@ -286,137 +326,48 @@ void CACHE()
|
|||
switch (_Rt_)
|
||||
{
|
||||
case 0x1a: //DHIN (Data Cache Hit Invalidate)
|
||||
{
|
||||
const int index = (addr >> 6) & 0x3F;
|
||||
int way = 0;
|
||||
const u32 pfnaddr = addr;
|
||||
const auto vmv = vtlbdata.vmap[pfnaddr >> VTLB_PAGE_BITS];
|
||||
const u32 paddr = vmv.assumeHandlerGetPAddr(pfnaddr);
|
||||
|
||||
if ((paddr & ~0xFFF) == (pCache[index].tag[0] & ~0xfff) && (pCache[index].tag[0] & VALID_FLAG))
|
||||
doCacheHitOp(addr, "DHIN", [](CacheLine line)
|
||||
{
|
||||
way = 0;
|
||||
}
|
||||
else if ((paddr & ~0xFFF) == (pCache[index].tag[1] & ~0xfff) && (pCache[index].tag[1] & VALID_FLAG))
|
||||
{
|
||||
way = 1;
|
||||
}
|
||||
else
|
||||
{
|
||||
CACHE_LOG("CACHE DHIN NO HIT addr %x, index %d, phys %x tag0 %x tag1 %x", addr, index, paddr, pCache[index].tag[0], pCache[index].tag[1]);
|
||||
return;
|
||||
}
|
||||
|
||||
CACHE_LOG("CACHE DHIN addr %x, index %d, way %d, Flags %x OP %x", addr, index, way, pCache[index].tag[way] & 0x78, cpuRegs.code);
|
||||
|
||||
clear_cache(index, way);
|
||||
line.clear();
|
||||
});
|
||||
break;
|
||||
}
|
||||
|
||||
case 0x18: //DHWBIN (Data Cache Hit WriteBack with Invalidate)
|
||||
{
|
||||
const int index = (addr >> 6) & 0x3F;
|
||||
int way = 0;
|
||||
const u32 pfnaddr = addr;
|
||||
const auto vmv = vtlbdata.vmap[pfnaddr >> VTLB_PAGE_BITS];
|
||||
uptr ppf = vmv.assumePtr(pfnaddr) & ~0x3F;
|
||||
const u32 paddr = vmv.assumeHandlerGetPAddr(pfnaddr) & ~0x3f;
|
||||
|
||||
if ((pCache[index].tag[0] & ~0xFFF) == (paddr & ~0xFFF) && (pCache[index].tag[0] & VALID_FLAG))
|
||||
doCacheHitOp(addr, "DHWBIN", [](CacheLine line)
|
||||
{
|
||||
way = 0;
|
||||
}
|
||||
else if ((pCache[index].tag[1] & ~0xFFF) == (paddr & ~0xFFF) && (pCache[index].tag[1] & VALID_FLAG))
|
||||
{
|
||||
way = 1;
|
||||
}
|
||||
else
|
||||
{
|
||||
CACHE_LOG("CACHE DHWBIN NO HIT addr %x, index %d, phys %x tag0 %x tag1 %x", addr, index, paddr, pCache[index].tag[0], pCache[index].tag[1]);
|
||||
return;
|
||||
}
|
||||
|
||||
CACHE_LOG("CACHE DHWBIN addr %x, index %d, phys %x tag0 %x tag1 %x way %x", addr, index, paddr, pCache[index].tag[0], pCache[index].tag[1], way );
|
||||
|
||||
if ((pCache[index].tag[way] & (DIRTY_FLAG|VALID_FLAG)) == (DIRTY_FLAG|VALID_FLAG)) // Dirty
|
||||
{
|
||||
CACHE_LOG("DHWBIN Dirty WriteBack PPF %x", ppf);
|
||||
|
||||
*reinterpret_cast<mem64_t*>(ppf) = pCache[index].data[way][0].b8._u64[0];
|
||||
*reinterpret_cast<mem64_t*>(ppf+8) = pCache[index].data[way][0].b8._u64[1];
|
||||
*reinterpret_cast<mem64_t*>(ppf+16) = pCache[index].data[way][1].b8._u64[0];
|
||||
*reinterpret_cast<mem64_t*>(ppf+24) = pCache[index].data[way][1].b8._u64[1];
|
||||
*reinterpret_cast<mem64_t*>(ppf+32) = pCache[index].data[way][2].b8._u64[0];
|
||||
*reinterpret_cast<mem64_t*>(ppf+40) = pCache[index].data[way][2].b8._u64[1];
|
||||
*reinterpret_cast<mem64_t*>(ppf+48) = pCache[index].data[way][3].b8._u64[0];
|
||||
*reinterpret_cast<mem64_t*>(ppf+56) = pCache[index].data[way][3].b8._u64[1];
|
||||
}
|
||||
|
||||
clear_cache(index, way);
|
||||
line.writeBackIfNeeded();
|
||||
line.clear();
|
||||
});
|
||||
break;
|
||||
}
|
||||
|
||||
case 0x1c: //DHWOIN (Data Cache Hit WriteBack Without Invalidate)
|
||||
{
|
||||
const int index = (addr >> 6) & 0x3F;
|
||||
int way = 0;
|
||||
const u32 pfnaddr = (pCache[index].tag[way] & ~0x80000fff) | (addr & 0xfc0);
|
||||
const auto vmv = vtlbdata.vmap[pfnaddr >> VTLB_PAGE_BITS];
|
||||
uptr ppf = vmv.assumePtr(pfnaddr);
|
||||
const u32 paddr = vmv.assumeHandlerGetPAddr(pfnaddr);
|
||||
|
||||
CACHE_LOG("CACHE DHWOIN addr %x, index %d, way %d, Flags %x OP %x", addr, index, way, pCache[index].tag[way] & 0x78, cpuRegs.code);
|
||||
|
||||
if ((pCache[index].tag[0] & ~0xFFF) == (paddr & ~0xFFF) && (pCache[index].tag[0] & VALID_FLAG))
|
||||
doCacheHitOp(addr, "DHWOIN", [](CacheLine line)
|
||||
{
|
||||
way = 0;
|
||||
}
|
||||
else if ((pCache[index].tag[1] & ~0xFFF) == (paddr & ~0xFFF) && (pCache[index].tag[1] & VALID_FLAG))
|
||||
{
|
||||
way = 1;
|
||||
}
|
||||
else
|
||||
{
|
||||
CACHE_LOG("CACHE DHWOIN NO HIT addr %x, index %d, phys %x tag0 %x tag1 %x", addr, index, paddr, pCache[index].tag[0], pCache[index].tag[1]);
|
||||
return;
|
||||
}
|
||||
|
||||
if ((pCache[index].tag[way] & (DIRTY_FLAG|VALID_FLAG)) == (DIRTY_FLAG|VALID_FLAG)) // Dirty
|
||||
{
|
||||
CACHE_LOG("DHWOIN Dirty WriteBack! PPF %x", ppf);
|
||||
*reinterpret_cast<mem64_t*>(ppf) = pCache[index].data[way][0].b8._u64[0];
|
||||
*reinterpret_cast<mem64_t*>(ppf+8) = pCache[index].data[way][0].b8._u64[1];
|
||||
*reinterpret_cast<mem64_t*>(ppf+16) = pCache[index].data[way][1].b8._u64[0];
|
||||
*reinterpret_cast<mem64_t*>(ppf+24) = pCache[index].data[way][1].b8._u64[1];
|
||||
*reinterpret_cast<mem64_t*>(ppf+32) = pCache[index].data[way][2].b8._u64[0];
|
||||
*reinterpret_cast<mem64_t*>(ppf+40) = pCache[index].data[way][2].b8._u64[1];
|
||||
*reinterpret_cast<mem64_t*>(ppf+48) = pCache[index].data[way][3].b8._u64[0];
|
||||
*reinterpret_cast<mem64_t*>(ppf+56) = pCache[index].data[way][3].b8._u64[1];
|
||||
|
||||
pCache[index].tag[way] &= ~DIRTY_FLAG;
|
||||
}
|
||||
line.writeBackIfNeeded();
|
||||
});
|
||||
break;
|
||||
}
|
||||
|
||||
case 0x16: //DXIN (Data Cache Index Invalidate)
|
||||
{
|
||||
const int index = (addr >> 6) & 0x3F;
|
||||
const int index = cache.setIdxFor(addr);
|
||||
const int way = addr & 0x1;
|
||||
CacheLine line = cache.lineAt(index, way);
|
||||
|
||||
CACHE_LOG("CACHE DXIN addr %x, index %d, way %d, flag %x\n", addr, index, way, pCache[index].tag[way] & 0x78);
|
||||
CACHE_LOG("CACHE DXIN addr %x, index %d, way %d, flag %x", addr, index, way, line.tag.flags());
|
||||
|
||||
clear_cache(index, way);
|
||||
line.clear();
|
||||
break;
|
||||
}
|
||||
|
||||
case 0x11: //DXLDT (Data Cache Load Data into TagLo)
|
||||
{
|
||||
const int index = (addr >> 6) & 0x3F;
|
||||
const int index = cache.setIdxFor(addr);
|
||||
const int way = addr & 0x1;
|
||||
CacheLine line = cache.lineAt(index, way);
|
||||
|
||||
cpuRegs.CP0.n.TagLo = pCache[index].data[way][(addr >> 4) & 0x3].b8._u32[(addr & 0xf) >> 2];
|
||||
cpuRegs.CP0.n.TagLo = *reinterpret_cast<u32*>(&line.data.bytes[addr & 0x3C]);
|
||||
|
||||
CACHE_LOG("CACHE DXLDT addr %x, index %d, way %d, DATA %x OP %x", addr, index, way, cpuRegs.CP0.r[28], cpuRegs.code);
|
||||
CACHE_LOG("CACHE DXLDT addr %x, index %d, way %d, DATA %x OP %x", addr, index, way, cpuRegs.CP0.n.TagLo, cpuRegs.code);
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
@ -424,32 +375,17 @@ void CACHE()
|
|||
{
|
||||
const int index = (addr >> 6) & 0x3F;
|
||||
const int way = addr & 0x1;
|
||||
CacheLine line = cache.lineAt(index, way);
|
||||
|
||||
//DXLTG demands that SYNC.L is called before this command, which forces the cache to write back, so presumably games are checking the cache has updated the memory
|
||||
//For speed, we will do it here.
|
||||
const u32 pfnaddr = (pCache[index].tag[way] & ~0x80000fff) | (addr & 0xfc0);
|
||||
const auto vmv = vtlbdata.vmap[pfnaddr >> VTLB_PAGE_BITS];
|
||||
s32 ppf = vmv.assumePtr(pfnaddr);
|
||||
// DXLTG demands that SYNC.L is called before this command, which forces the cache to write back, so presumably games are checking the cache has updated the memory
|
||||
// For speed, we will do it here.
|
||||
line.writeBackIfNeeded();
|
||||
|
||||
if ((pCache[index].tag[way] & (DIRTY_FLAG | VALID_FLAG)) == (DIRTY_FLAG | VALID_FLAG)) // Dirty
|
||||
{
|
||||
CACHE_LOG("DXLTG Dirty WriteBack! PPF %x", ppf);
|
||||
ppf = (ppf & 0x7fffffff);
|
||||
*reinterpret_cast<mem64_t*>(ppf) = pCache[index].data[way][0].b8._u64[0];
|
||||
*reinterpret_cast<mem64_t*>(ppf + 8) = pCache[index].data[way][0].b8._u64[1];
|
||||
*reinterpret_cast<mem64_t*>(ppf + 16) = pCache[index].data[way][1].b8._u64[0];
|
||||
*reinterpret_cast<mem64_t*>(ppf + 24) = pCache[index].data[way][1].b8._u64[1];
|
||||
*reinterpret_cast<mem64_t*>(ppf + 32) = pCache[index].data[way][2].b8._u64[0];
|
||||
*reinterpret_cast<mem64_t*>(ppf + 40) = pCache[index].data[way][2].b8._u64[1];
|
||||
*reinterpret_cast<mem64_t*>(ppf + 48) = pCache[index].data[way][3].b8._u64[0];
|
||||
*reinterpret_cast<mem64_t*>(ppf + 56) = pCache[index].data[way][3].b8._u64[1];
|
||||
// Our tags don't contain PS2 paddrs (instead they contain x86 addrs)
|
||||
cpuRegs.CP0.n.TagLo = line.tag.flags();
|
||||
|
||||
pCache[index].tag[way] &= ~DIRTY_FLAG;
|
||||
}
|
||||
//DevCon.Warning("DXLTG way %x index %x addr %x tagdata=%x", way, index, addr, pCache[index].tag[way]);
|
||||
cpuRegs.CP0.n.TagLo = pCache[index].tag[way];
|
||||
|
||||
CACHE_LOG("CACHE DXLTG addr %x, index %d, way %d, DATA %x OP %x ", addr, index, way, cpuRegs.CP0.r[28], cpuRegs.code);
|
||||
CACHE_LOG("CACHE DXLTG addr %x, index %d, way %d, DATA %x OP %x ", addr, index, way, cpuRegs.CP0.n.TagLo, cpuRegs.code);
|
||||
CACHE_LOG("WARNING: DXLTG emulation supports flags only, things could break");
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
@ -457,10 +393,11 @@ void CACHE()
|
|||
{
|
||||
const int index = (addr >> 6) & 0x3F;
|
||||
const int way = addr & 0x1;
|
||||
CacheLine line = cache.lineAt(index, way);
|
||||
|
||||
pCache[index].data[way][(addr >> 4) & 0x3].b8._u32[(addr & 0xf) >> 2] = cpuRegs.CP0.n.TagLo;
|
||||
*reinterpret_cast<u32*>(&line.data.bytes[addr & 0x3C]) = cpuRegs.CP0.n.TagLo;
|
||||
|
||||
CACHE_LOG("CACHE DXSDT addr %x, index %d, way %d, DATA %x OP %x", addr, index, way, cpuRegs.CP0.r[28], cpuRegs.code);
|
||||
CACHE_LOG("CACHE DXSDT addr %x, index %d, way %d, DATA %x OP %x", addr, index, way, cpuRegs.CP0.n.TagLo, cpuRegs.code);
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
@ -468,9 +405,13 @@ void CACHE()
|
|||
{
|
||||
const int index = (addr >> 6) & 0x3F;
|
||||
const int way = addr & 0x1;
|
||||
pCache[index].tag[way] = cpuRegs.CP0.n.TagLo;
|
||||
CacheLine line = cache.lineAt(index, way);
|
||||
|
||||
CACHE_LOG("CACHE DXSTG addr %x, index %d, way %d, DATA %x OP %x", addr, index, way, cpuRegs.CP0.r[28] & 0x6F, cpuRegs.code);
|
||||
line.tag.rawValue &= ~CacheTag::ALL_FLAGS;
|
||||
line.tag.rawValue |= (cpuRegs.CP0.n.TagLo & CacheTag::ALL_FLAGS);
|
||||
|
||||
CACHE_LOG("CACHE DXSTG addr %x, index %d, way %d, DATA %x OP %x", addr, index, way, cpuRegs.CP0.n.TagLo, cpuRegs.code);
|
||||
CACHE_LOG("WARNING: DXSTG emulation supports flags only, things will probably break");
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
@ -478,28 +419,11 @@ void CACHE()
|
|||
{
|
||||
const int index = (addr >> 6) & 0x3F;
|
||||
const int way = addr & 0x1;
|
||||
const u32 pfnaddr = (pCache[index].tag[way] & ~0x80000fff) + (addr & 0xFC0);
|
||||
const auto vmv = vtlbdata.vmap[pfnaddr >> VTLB_PAGE_BITS];
|
||||
s32 ppf = vmv.assumePtr(pfnaddr);
|
||||
const u32 paddr = vmv.assumeHandlerGetPAddr(pfnaddr);
|
||||
CacheLine line = cache.lineAt(index, way);
|
||||
|
||||
CACHE_LOG("CACHE DXWBIN addr %x, index %d, way %d, Flags %x Paddr %x tag %x", addr, index, way, pCache[index].tag[way] & 0x78, paddr, pCache[index].tag[way]);
|
||||
if ((pCache[index].tag[way] & (DIRTY_FLAG|VALID_FLAG)) == (DIRTY_FLAG|VALID_FLAG)) // Dirty
|
||||
{
|
||||
ppf = (ppf & 0x7fffffff);
|
||||
CACHE_LOG("DXWBIN Dirty WriteBack! PPF %x", ppf);
|
||||
|
||||
*reinterpret_cast<mem64_t*>(ppf) = pCache[index].data[way][0].b8._u64[0];
|
||||
*reinterpret_cast<mem64_t*>(ppf+8) = pCache[index].data[way][0].b8._u64[1];
|
||||
*reinterpret_cast<mem64_t*>(ppf+16) = pCache[index].data[way][1].b8._u64[0];
|
||||
*reinterpret_cast<mem64_t*>(ppf+24) = pCache[index].data[way][1].b8._u64[1];
|
||||
*reinterpret_cast<mem64_t*>(ppf+32) = pCache[index].data[way][2].b8._u64[0];
|
||||
*reinterpret_cast<mem64_t*>(ppf+40) = pCache[index].data[way][2].b8._u64[1];
|
||||
*reinterpret_cast<mem64_t*>(ppf+48) = pCache[index].data[way][3].b8._u64[0];
|
||||
*reinterpret_cast<mem64_t*>(ppf+56) = pCache[index].data[way][3].b8._u64[1];
|
||||
}
|
||||
|
||||
clear_cache(index, way);
|
||||
CACHE_LOG("CACHE DXWBIN addr %x, index %d, way %d, flags %x paddr %zx", addr, index, way, line.tag.flags(), line.addr());
|
||||
line.writeBackIfNeeded();
|
||||
line.clear();
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -18,27 +18,7 @@
|
|||
|
||||
#include "Common.h"
|
||||
|
||||
|
||||
union _u8bit_128
|
||||
{
|
||||
u8 _u8[16];
|
||||
u16 _u16[8];
|
||||
u32 _u32[4];
|
||||
u64 _u64[2];
|
||||
};
|
||||
|
||||
struct u8bit_128 {
|
||||
_u8bit_128 b8;
|
||||
|
||||
};
|
||||
|
||||
struct _cacheS {
|
||||
u32 tag[2];
|
||||
u8bit_128 data[2][4];
|
||||
};
|
||||
|
||||
extern _cacheS pCache[64];
|
||||
|
||||
void resetCache();
|
||||
void writeCache8(u32 mem, u8 value);
|
||||
void writeCache16(u32 mem, u16 value);
|
||||
void writeCache32(u32 mem, u32 value);
|
||||
|
|
|
|||
|
|
@ -41,7 +41,7 @@ static void PreLoadPrep()
|
|||
|
||||
static void PostLoadPrep()
|
||||
{
|
||||
memzero(pCache);
|
||||
resetCache();
|
||||
// WriteCP0Status(cpuRegs.CP0.n.Status.val);
|
||||
for(int i=0; i<48; i++) MapTLB(i);
|
||||
if (EmuConfig.Gamefixes.GoemonTlbHack) GoemonPreloadTlb();
|
||||
|
|
|
|||
Loading…
Reference in New Issue