From 6ab6749a53326afbeb5201dd808b68d5dfe89ab5 Mon Sep 17 00:00:00 2001 From: cottonvibes Date: Fri, 28 Aug 2009 22:50:55 +0000 Subject: [PATCH] microVU: Removed the use of an offset-register for referencing VI regs. It didn't make any noticeable difference speedwise, and removing it will make mVU macro code simpler. git-svn-id: http://pcsx2.googlecode.com/svn/trunk@1703 96395faa-99c1-11dd-bbfe-3dabce05a288 --- pcsx2/x86/microVU_Alloc.inl | 9 ++++----- pcsx2/x86/microVU_Branch.inl | 2 +- pcsx2/x86/microVU_Compile.inl | 1 - pcsx2/x86/microVU_Execute.inl | 2 -- pcsx2/x86/microVU_Flags.inl | 5 ++--- pcsx2/x86/microVU_Lower.inl | 19 +++++++++---------- pcsx2/x86/microVU_Misc.h | 4 +--- pcsx2/x86/microVU_Misc.inl | 1 - 8 files changed, 17 insertions(+), 26 deletions(-) diff --git a/pcsx2/x86/microVU_Alloc.inl b/pcsx2/x86/microVU_Alloc.inl index d794fc0082..1db752045c 100644 --- a/pcsx2/x86/microVU_Alloc.inl +++ b/pcsx2/x86/microVU_Alloc.inl @@ -100,17 +100,16 @@ microVUt(void) mVUallocCFLAGb(mV, int reg, int fInstance) { microVUt(void) mVUallocVIa(mV, int GPRreg, int _reg_) { if (!_reg_) { XOR32RtoR(GPRreg, GPRreg); } - else { MOVZX32Rm16toR(GPRreg, gprR, (_reg_ - 9) * 16); } + else { MOVZX32M16toR(GPRreg, (uptr)&mVU->regs->VI[_reg_].UL); } } microVUt(void) mVUallocVIb(mV, int GPRreg, int _reg_) { if (mVUlow.backupVI) { // Backs up reg to memory (used when VI is modified b4 a branch) - MOVZX32M16toR(gprR, (uptr)&mVU->regs->VI[_reg_].UL); - MOV32RtoM((uptr)&mVU->VIbackup, gprR); - MOV32ItoR(gprR, Roffset); + MOVZX32M16toR(gprT3, (uptr)&mVU->regs->VI[_reg_].UL); + MOV32RtoM((uptr)&mVU->VIbackup, gprT3); } if (_reg_ == 0) { return; } - else if (_reg_ < 16) { MOV16RtoRm(gprR, GPRreg, (_reg_ - 9) * 16); } + else if (_reg_ < 16) { MOV16RtoM((uptr)&mVU->regs->VI[_reg_].UL, GPRreg); } } //------------------------------------------------------------------ diff --git a/pcsx2/x86/microVU_Branch.inl b/pcsx2/x86/microVU_Branch.inl index 3e574abd64..054446c567 100644 --- a/pcsx2/x86/microVU_Branch.inl +++ b/pcsx2/x86/microVU_Branch.inl @@ -104,7 +104,7 @@ void normJumpCompile(mV, microFlagCycles& mFC, bool isEvilJump) { if (isEvilJump) MOV32MtoR(gprT2, (uptr)&mVU->evilBranch); else MOV32MtoR(gprT2, (uptr)&mVU->branch); - MOV32ItoR(gprR, (u32)&mVUpBlock->pStateEnd); + MOV32ItoR(gprT3, (u32)&mVUpBlock->pStateEnd); if (!mVU->index) xCALL(mVUcompileJIT<0>); //(u32 startPC, uptr pState) else xCALL(mVUcompileJIT<1>); diff --git a/pcsx2/x86/microVU_Compile.inl b/pcsx2/x86/microVU_Compile.inl index cec2b5b6e4..88dcc1b255 100644 --- a/pcsx2/x86/microVU_Compile.inl +++ b/pcsx2/x86/microVU_Compile.inl @@ -295,7 +295,6 @@ microVUt(void) mVUtestCycles(mV) { MOV32ItoR(gprT2, (uptr)mVU); if (isVU1) CALLFunc((uptr)mVUwarning1); //else CALLFunc((uptr)mVUwarning0); // VU0 is allowed early exit for COP2 Interlock Simulation - MOV32ItoR(gprR, Roffset); // Restore gprR mVUendProgram(mVU, NULL, 0); if (!isVU1) x86SetJ32(vu0jmp); x86SetJ32(jmp32); diff --git a/pcsx2/x86/microVU_Execute.inl b/pcsx2/x86/microVU_Execute.inl index 76c0e4fb5d..1e4c105820 100644 --- a/pcsx2/x86/microVU_Execute.inl +++ b/pcsx2/x86/microVU_Execute.inl @@ -40,9 +40,7 @@ void mVUdispatcherA(mV) { SSE_LDMXCSR((uptr)&g_sseVUMXCSR); // Load Regs - MOV32ItoR(gprR, Roffset); // Load VI Reg Offset MOV32MtoR(gprF0, (uptr)&mVU->regs->VI[REG_STATUS_FLAG].UL); - MOV32RtoR(gprF1, gprF0); SHR32ItoR(gprF1, 3); AND32ItoR(gprF1, 0x18); diff --git a/pcsx2/x86/microVU_Flags.inl b/pcsx2/x86/microVU_Flags.inl index dd9ccfcb68..1401761c9e 100644 --- a/pcsx2/x86/microVU_Flags.inl +++ b/pcsx2/x86/microVU_Flags.inl @@ -197,12 +197,11 @@ microVUt(void) mVUsetupFlags(mV, microFlagCycles& mFC) { else { MOV32RtoR(gprT1, getFlagReg1(bStatus[0])); MOV32RtoR(gprT2, getFlagReg1(bStatus[1])); - MOV32RtoR(gprR, getFlagReg1(bStatus[2])); + MOV32RtoR(gprT3, getFlagReg1(bStatus[2])); MOV32RtoR(gprF3, getFlagReg1(bStatus[3])); MOV32RtoR(gprF0, gprT1); MOV32RtoR(gprF1, gprT2); - MOV32RtoR(gprF2, gprR); - MOV32ItoR(gprR, Roffset); // Restore gprR + MOV32RtoR(gprF2, gprT3); } } diff --git a/pcsx2/x86/microVU_Lower.inl b/pcsx2/x86/microVU_Lower.inl index cf51547bf5..1cbf0e0250 100644 --- a/pcsx2/x86/microVU_Lower.inl +++ b/pcsx2/x86/microVU_Lower.inl @@ -1030,23 +1030,22 @@ mVUop(mVU_RNEXT) { pass1 { mVUanalyzeR2(mVU, _Ft_, 0); } pass2 { // algorithm from www.project-fao.org - MOV32MtoR(gprR, Rmem); - MOV32RtoR(gprT1, gprR); + MOV32MtoR(gprT3, Rmem); + MOV32RtoR(gprT1, gprT3); SHR32ItoR(gprT1, 4); AND32ItoR(gprT1, 1); - MOV32RtoR(gprT2, gprR); + MOV32RtoR(gprT2, gprT3); SHR32ItoR(gprT2, 22); AND32ItoR(gprT2, 1); - SHL32ItoR(gprR, 1); + SHL32ItoR(gprT3, 1); XOR32RtoR(gprT1, gprT2); - XOR32RtoR(gprR, gprT1); - AND32ItoR(gprR, 0x007fffff); - OR32ItoR (gprR, 0x3f800000); - MOV32RtoM(Rmem, gprR); - mVU_RGET_(mVU, gprR); - MOV32ItoR(gprR, Roffset); // Restore gprR + XOR32RtoR(gprT3, gprT1); + AND32ItoR(gprT3, 0x007fffff); + OR32ItoR (gprT3, 0x3f800000); + MOV32RtoM(Rmem, gprT3); + mVU_RGET_(mVU, gprT3); } pass3 { mVUlog("RNEXT.%s vf%02d, R", _XYZW_String, _Ft_); } } diff --git a/pcsx2/x86/microVU_Misc.h b/pcsx2/x86/microVU_Misc.h index 1c203e10dc..e5fa9fadb3 100644 --- a/pcsx2/x86/microVU_Misc.h +++ b/pcsx2/x86/microVU_Misc.h @@ -128,7 +128,7 @@ declareAllVariables #define gprT1 0 // Temp Reg #define gprT2 1 // Temp Reg -#define gprR 2 // VI Reg Offset +#define gprT3 2 // Temp Reg #define gprF0 3 // Status Flag 0 #define gprESP 4 // Don't use? #define gprF1 5 // Status Flag 1 @@ -219,7 +219,6 @@ typedef u32 (__fastcall *mVUCall)(void*, void*); #define shufflePQ (((mVU->p) ? 0xb0 : 0xe0) | ((mVU->q) ? 0x01 : 0x04)) #define cmpOffset(x) ((u8*)&(((u8*)x)[mVUprogI.ranges.range[i][0]])) #define Rmem (uptr)&mVU->regs->VI[REG_R].UL -#define Roffset (uptr)&mVU->regs->VI[9].UL #define aWrap(x, m) ((x > m) ? 0 : x) #define shuffleSS(x) ((x==1)?(0x27):((x==2)?(0xc6):((x==4)?(0xe1):(0xe4)))) @@ -287,6 +286,5 @@ typedef u32 (__fastcall *mVUCall)(void*, void*); MOV32ItoR(gprT2, xPC); \ if (isEndPC) { CALLFunc((uptr)mVUprintPC2); } \ else { CALLFunc((uptr)mVUprintPC1); } \ - MOV32ItoR(gprR, Roffset); \ } \ } diff --git a/pcsx2/x86/microVU_Misc.inl b/pcsx2/x86/microVU_Misc.inl index 1e92a5dc44..5961ec14cb 100644 --- a/pcsx2/x86/microVU_Misc.inl +++ b/pcsx2/x86/microVU_Misc.inl @@ -317,7 +317,6 @@ microVUt(void) mVUbackupRegs(microVU* mVU) { // Restore Volatile Regs microVUt(void) mVUrestoreRegs(microVU* mVU) { SSE_MOVAPS_M128_to_XMM(xmmPQ, (uptr)&mVU->xmmPQb[0]); - MOV32ItoR(gprR, Roffset); // Restore gprR } //------------------------------------------------------------------