diff --git a/pcsx2/FiFo.cpp b/pcsx2/FiFo.cpp
index 38ab311757..52d271b204 100644
--- a/pcsx2/FiFo.cpp
+++ b/pcsx2/FiFo.cpp
@@ -59,13 +59,13 @@ void __fastcall ReadFIFO_page_5(u32 mem, u64 *out)
 
 	VIF_LOG("ReadFIFO/VIF1, addr=0x%08X", mem);
 
-	if( vif1Regs->stat & (VIF1_STAT_INT|VIF1_STAT_VSS|VIF1_STAT_VIS|VIF1_STAT_VFS) )
+	if( vif1Regs->stat._u32 & (VIF1_STAT_INT|VIF1_STAT_VSS|VIF1_STAT_VIS|VIF1_STAT_VFS) )
 		DevCon.Notice( "Reading from vif1 fifo when stalled" );
 
-	if (vif1Regs->stat & VIF1_STAT_FDR)
+	if (vif1Regs->stat.FDR)
 	{
 		if (--psHu32(D1_QWC) == 0)
-			vif1Regs->stat&= ~VIF1_STAT_FQC;
+			vif1Regs->stat.FQC = 0;
 	}
 
 	//out[0] = psHu64(mem  );
@@ -142,9 +142,9 @@ void __fastcall WriteFIFO_page_5(u32 mem, const mem128_t *value)
 	psHu64(0x5000) = value[0];
 	psHu64(0x5008) = value[1];
 
-	if(vif1Regs->stat & VIF1_STAT_FDR)
+	if (vif1Regs->stat.FDR)
 		DevCon.Notice("writing to fifo when fdr is set!");
-	if( vif1Regs->stat & (VIF1_STAT_INT | VIF1_STAT_VSS | VIF1_STAT_VIS | VIF1_STAT_VFS) )
+	if ( vif1Regs->stat._u32 & (VIF1_STAT_INT | VIF1_STAT_VSS | VIF1_STAT_VIS | VIF1_STAT_VFS) )
 		DevCon.Notice("writing to vif1 fifo when stalled");
 
 	vif1ch->qwc += 1;
diff --git a/pcsx2/Gif.cpp b/pcsx2/Gif.cpp
index 48152bee50..8cb5e045ed 100644
--- a/pcsx2/Gif.cpp
+++ b/pcsx2/Gif.cpp
@@ -62,7 +62,7 @@ __forceinline void gsInterrupt()
 
 	if ((vif1.cmd & 0x7f) == 0x51)
 	{
-		if (Path3progress != IMAGE_MODE) vif1Regs->stat &= ~VIF1_STAT_VGW;
+		if (Path3progress != IMAGE_MODE) vif1Regs->stat.VGW = 0;
 	}
 
 	if (Path3progress == STOPPED_MODE) gifRegs->stat._u32 &= ~(GIF_STAT_APATH3 | GIF_STAT_OPH); // OPH=0 | APATH=0
@@ -84,7 +84,7 @@ __forceinline void gsInterrupt()
 	gspath3done = false;
 	gscycles = 0;
 	gif->chcr.STR = 0;
-	vif1Regs->stat &= ~VIF1_STAT_VGW;
+	vif1Regs->stat.VGW = 0;
 	
 	gifRegs->stat._u32 &= ~(GIF_STAT_APATH3 | GIF_STAT_OPH | GIF_STAT_P3Q | GIF_STAT_FQC); 
 	
@@ -224,9 +224,9 @@ void GIFdma()
 			}
 		} 
 		 
-		if (Path3progress == STOPPED_MODE) /*|| (vif1Regs->stat |= VIF1_STAT_VGW) == 0*/
+		if (Path3progress == STOPPED_MODE) /*|| (vif1Regs->stat._u32 |= VIF1_STAT_VGW) == 0*/
 		{
-			vif1Regs->stat &= ~VIF1_STAT_VGW;
+			vif1Regs->stat.VGW = 0;
 			if (gif->qwc == 0) CPU_INT(2, 16);
 			return;
 		}
@@ -539,9 +539,9 @@ void gifMFIFOInterrupt()
 		if (gifqwc <= 0) 
 		{
 			//Console.WriteLn("Empty");
+			hwDmacIrq(DMAC_MFIFO_EMPTY);
 			gifstate |= GIF_STATE_EMPTY;
 			gifRegs->stat.IMT = 0; // OPH=0 | APATH=0
-			hwDmacIrq(DMAC_MFIFO_EMPTY);
 			return;
 		}
 		mfifoGIFtransfer(0);
@@ -563,7 +563,7 @@ void gifMFIFOInterrupt()
 	
 	gifRegs->stat._u32 &= ~(GIF_STAT_APATH3 | GIF_STAT_OPH | GIF_STAT_P3Q | GIF_STAT_FQC); // OPH, APATH, P3Q,  FQC = 0
 	
-	vif1Regs->stat &= ~VIF1_STAT_VGW;
+	vif1Regs->stat.VGW = 0;
 	gif->chcr.STR = 0;
 	gifstate = GIF_STATE_READY;
 	hwDmacIrq(DMAC_GIF);
diff --git a/pcsx2/Hw.h b/pcsx2/Hw.h
index 65b9b2ad97..8ab1da7d16 100644
--- a/pcsx2/Hw.h
+++ b/pcsx2/Hw.h
@@ -85,7 +85,7 @@ struct DMACh {
 };
 
 // HW defines
-enum HWaddress
+enum EERegisterAddresses
 {
 	RCNT0_COUNT		=	0x10000000,
 	RCNT0_MODE		=	0x10000010,
@@ -266,8 +266,12 @@ enum HWaddress
 	MCH_DRD			=	0x1000F440,
 
 	DMAC_ENABLER	=	0x1000F520,
-	DMAC_ENABLEW	=	0x1000F590,
+	DMAC_ENABLEW	=	0x1000F590
+};
 
+
+enum GSRegisterAddresses
+{
 	GS_PMODE		=	0x12000000,
 	GS_SMODE1		=	0x12000010,
 	GS_SMODE2		=	0x12000020,
@@ -289,8 +293,8 @@ enum HWaddress
 	GS_SIGLBLID		=	0x12001080
 };
 
-#define SBFLG_IOPALIVE 0x10000
-#define SBFLG_IOPSYNC 0x40000
+//#define SBFLG_IOPALIVE 0x10000
+//#define SBFLG_IOPSYNC 0x40000
 
 enum INTCIrqs
 {
@@ -335,24 +339,24 @@ enum DMACIrqs
 
 	// We're setting error conditions through hwDmacIrq, so these correspond to the conditions above.
 	DMAC_STALL_SIS		= 13,
-	DMAC_MFIFO_EMPTY		= 14, // Transfer?
+	DMAC_MFIFO_EMPTY	= 14,
 	DMAC_BUS_ERROR	= 15
 };
 
 //DMA interrupts & masks
 enum DMAInter
 {
-	BEISintr = 0x8000,
-	VIF0intr = 0x10001,
-	VIF1intr = 0x20002,
-	GIFintr = 0x40004,
-	IPU0intr = 0x80008,
-	IPU1intr = 0x100010,
-	SIF0intr = 0x200020,
-	SIF1intr  =0x400040,
-	SIF2intr = 0x800080,
-	SPR0intr = 0x1000100,
-	SPR1intr = 0x2000200,
+	BEISintr = 0x00008000,
+	VIF0intr = 0x00010001,
+	VIF1intr = 0x00020002,
+	GIFintr =  0x00040004,
+	IPU0intr = 0x00080008,
+	IPU1intr = 0x00100010,
+	SIF0intr = 0x00200020,
+	SIF1intr  =0x00400040,
+	SIF2intr = 0x00800080,
+	SPR0intr = 0x01000100,
+	SPR1intr = 0x02000200,
 	SISintr  = 0x20002000,
 	MEISintr = 0x40004000
 };
@@ -433,7 +437,6 @@ union tDMAC_STADR {
 
 struct DMACregisters
 {
-	// Note: not yet tested.
 	tDMAC_CTRL	ctrl;
 	u32 padding[3];
 	tDMAC_STAT	stat;
@@ -573,13 +576,6 @@ extern void __fastcall hwWrite64_generic( u32 mem, const mem64_t* srcval );
 
 extern void __fastcall hwWrite128_generic(u32 mem, const mem128_t *srcval);
 
-// legacy - used for debugging sometimes
-//extern mem32_t __fastcall hwRead32(u32 mem);
-//extern void __fastcall hwWrite32(u32 mem, u32 value);
-
-//extern void hwWrite64(u32 mem, u64 value);
-//extern void hwWrite128(u32 mem, const u64 *value);
-
 void hwIntcIrq(int n);
 void hwDmacIrq(int n);
 
diff --git a/pcsx2/IopDma.cpp b/pcsx2/IopDma.cpp
index 9a62eed464..41d6541aa7 100644
--- a/pcsx2/IopDma.cpp
+++ b/pcsx2/IopDma.cpp
@@ -138,7 +138,6 @@ int psxDma7Interrupt()
 
 void psxDma8(u32 madr, u32 bcr, u32 chcr)
 {
-
 	const int size = (bcr >> 16) * (bcr & 0xFFFF) * 8;
 
 	switch (chcr & 0x01000201)
@@ -259,7 +258,6 @@ void iopIntcIrq(uint irqType)
 // Gigaherz's "Improved DMA Handling" Engine WIP...
 //
 
-// fixme: Is this in progress?
 #ifdef ENABLE_NEW_IOPDMA
 
 s32  spu2DmaRead(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed)
diff --git a/pcsx2/IopHw.h b/pcsx2/IopHw.h
index a6c16103fa..784e3d0e31 100644
--- a/pcsx2/IopHw.h
+++ b/pcsx2/IopHw.h
@@ -42,6 +42,7 @@ static const u32
 	HW_SIO_CTRL			= 0x1f80104a,
 	HW_SIO_BAUD			= 0x1f80104e,
 
+    HW_RAM_SIZE         = 0x1f801060,
 	HW_IREG				= 0x1f801070,
 	HW_IMASK			= 0x1f801074,
 	HW_ICTRL			= 0x1f801078,
@@ -74,9 +75,69 @@ static const u32
 	HW_SIO2_RECV1		= 0x1f80826c,
 	HW_SIO2_RECV2		= 0x1f808270,
 	HW_SIO2_RECV3		= 0x1f808274,
+	HW_SIO2_8278        = 0x1F808278, // May as well add defs
+	HW_SIO2_827C        = 0x1F80827C, // for these 2...
 	HW_SIO2_INTR		= 0x1f808280;
 
+enum DMAMadrAddresses
+{
+    HWx_DMA0_MADR  = 0x1f801080,
+    HWx_DMA1_MADR  = 0x1f801090,
+    HWx_DMA2_MADR  = 0x1f8010a0,
+    HWx_DMA3_MADR  = 0x1f8010b0,
+    HWx_DMA4_MADR  = 0x1f8010c0,
+    HWx_DMA5_MADR  = 0x1f8010d0,
+    HWx_DMA6_MADR  = 0x1f8010e0,
+    HWx_DMA7_MADR  = 0x1f801500,
+    HWx_DMA8_MADR  = 0x1f801510,
+    HWx_DMA9_MADR  = 0x1f801520,
+    HWx_DMA10_MADR = 0x1f801530,
+    HWx_DMA11_MADR = 0x1f801540,
+    HWx_DMA12_MADR = 0x1f801550
+};
 
+enum DMABcrAddresses
+{
+    HWx_DMA0_BCR  = 0x1f801084,
+    HWx_DMA1_BCR  = 0x1f801094,
+    HWx_DMA2_BCR  = 0x1f8010a4,
+    HWx_DMA3_BCR  = 0x1f8010b4,
+    HWx_DMA3_BCR_L16  = 0x1f8010b4,
+    HWx_DMA3_BCR_H16  = 0x1f8010b6,
+    HWx_DMA4_BCR  = 0x1f8010c4,
+    HWx_DMA5_BCR  = 0x1f8010d4,
+    HWx_DMA6_BCR  = 0x1f8010e4,
+    HWx_DMA7_BCR  = 0x1f801504,
+    HWx_DMA8_BCR  = 0x1f801514,
+    HWx_DMA9_BCR  = 0x1f801524,
+    HWx_DMA10_BCR = 0x1f801534,
+    HWx_DMA11_BCR = 0x1f801544,
+    HWx_DMA12_BCR = 0x1f801554
+};
+
+enum DMAChcrAddresses
+{
+    HWx_DMA0_CHCR  = 0x1f801088,
+    HWx_DMA1_CHCR  = 0x1f801098,
+    HWx_DMA2_CHCR  = 0x1f8010a8,
+    HWx_DMA3_CHCR  = 0x1f8010b8,
+    HWx_DMA4_CHCR  = 0x1f8010c8,
+    HWx_DMA5_CHCR  = 0x1f8010d8,
+    HWx_DMA6_CHCR  = 0x1f8010e8,
+    HWx_DMA7_CHCR  = 0x1f801508,
+    HWx_DMA8_CHCR  = 0x1f801518,
+    HWx_DMA9_CHCR  = 0x1f801528,
+    HWx_DMA10_CHCR = 0x1f801538,
+    HWx_DMA11_CHCR = 0x1f801548,
+    HWx_DMA12_CHCR = 0x1f801558
+};
+
+enum DMATadrAddresses
+{
+    HWx_DMA2_TADR  = 0x1f8010ac,
+    HWx_DMA4_TADR  = 0x1f8010cc,
+    HWx_DMA9_TADR  = 0x1f80152c
+};
 /* Registers for the IOP Counters */
 enum IOPCountRegs
 {
diff --git a/pcsx2/Tags.h b/pcsx2/Tags.h
index cc9c3eee15..8a46c0fed2 100644
--- a/pcsx2/Tags.h
+++ b/pcsx2/Tags.h
@@ -14,10 +14,6 @@
  */
 
 // This is meant to be a collection of generic functions dealing with tags.
-// I kept seeing the same code over and over with different structure names
-// and the same members, and figured it'd be a good spot to use templates...
-
-// Actually, looks like I didn't need templates after all... :)
 
 enum mfd_type
 {
diff --git a/pcsx2/VU0micro.cpp b/pcsx2/VU0micro.cpp
index c2a5eaf6f3..7eba861ce5 100644
--- a/pcsx2/VU0micro.cpp
+++ b/pcsx2/VU0micro.cpp
@@ -41,7 +41,7 @@ void vu0ResetRegs()
 {
 	VU0.VI[REG_VPU_STAT].UL &= ~0xff; // stop vu0
 	VU0.VI[REG_FBRST].UL &= ~0xff; // stop vu0
-	vif0Regs->stat &= ~VIF0_STAT_VEW;
+	vif0Regs->stat.VEW = 0;
 }
 
 void VU0MI_XGKICK() {
diff --git a/pcsx2/VU0microInterp.cpp b/pcsx2/VU0microInterp.cpp
index 27ac602315..203364db4b 100644
--- a/pcsx2/VU0microInterp.cpp
+++ b/pcsx2/VU0microInterp.cpp
@@ -167,7 +167,7 @@ static void _vu0Exec(VURegs* VU)
 		if( VU->ebit-- == 1 ) {
 			_vuFlushAll(VU);
 			VU0.VI[REG_VPU_STAT].UL&= ~0x1; /* E flag */ 
-			vif0Regs->stat&= ~VIF0_STAT_VEW;
+			vif0Regs->stat.VEW = 0;
 		}
 	}
 }
diff --git a/pcsx2/VU1micro.cpp b/pcsx2/VU1micro.cpp
index 380c72e415..9a95111596 100644
--- a/pcsx2/VU1micro.cpp
+++ b/pcsx2/VU1micro.cpp
@@ -41,7 +41,7 @@ void vu1ResetRegs()
 {
 	VU0.VI[REG_VPU_STAT].UL &= ~0xff00; // stop vu1
 	VU0.VI[REG_FBRST].UL &= ~0xff00; // stop vu1
-	vif1Regs->stat &= ~VIF1_STAT_VEW;
+	vif1Regs->stat.VEW = 0;
 }
 
 static int count;
@@ -59,7 +59,7 @@ void vu1ExecMicro(u32 addr)
 
 	VU0.VI[REG_VPU_STAT].UL|= 0x100;
 	VU0.VI[REG_VPU_STAT].UL&= ~0x7E000;
-	vif1Regs->stat|= VIF1_STAT_VEW;
+	vif1Regs->stat.VEW = 1;
 	if (addr != -1) VU1.VI[REG_TPC].UL = addr;
 	_vuExecMicroDebug(VU1);
 
diff --git a/pcsx2/VU1microInterp.cpp b/pcsx2/VU1microInterp.cpp
index c30ee20910..dd1bb4855e 100644
--- a/pcsx2/VU1microInterp.cpp
+++ b/pcsx2/VU1microInterp.cpp
@@ -159,8 +159,8 @@ static void _vu1Exec(VURegs* VU)
 	if( VU->ebit > 0 ) {
 		if( VU->ebit-- == 1 ) {
 			_vuFlushAll(VU);
-			VU0.VI[REG_VPU_STAT].UL&= ~0x100;
-			vif1Regs->stat&= ~VIF1_STAT_VEW;
+			VU0.VI[REG_VPU_STAT].UL &= ~0x100;
+			vif1Regs->stat.VEW = 0;
 		}
 	}
 }
diff --git a/pcsx2/VUmicroMem.cpp b/pcsx2/VUmicroMem.cpp
index 77b8f2fe33..a89dd44ca7 100644
--- a/pcsx2/VUmicroMem.cpp
+++ b/pcsx2/VUmicroMem.cpp
@@ -30,7 +30,7 @@ VUmicroCpu CpuVU1;		// contains a working copy of the VU1 cpu functions/API
 static void DummyExecuteVU1Block(void)
 {
 	VU0.VI[ REG_VPU_STAT ].UL &= ~0x100;
-	VU1.vifRegs->stat &= ~VIF1_STAT_VEW; // also reset the bit (grandia 3 works)
+	VU1.vifRegs->stat.VEW = 0; // also reset the bit (grandia 3 works)
 }
 
 void vuMicroCpuReset()
diff --git a/pcsx2/Vif.cpp b/pcsx2/Vif.cpp
index c73abaafbf..065e32677c 100644
--- a/pcsx2/Vif.cpp
+++ b/pcsx2/Vif.cpp
@@ -526,7 +526,7 @@ void mfifoVIF1transfer(int qwc)
 			else
 				CPU_INT(10, vif1ch->qwc * BIAS);
 
-			vif1Regs->stat |= 0x10000000; // FQC=16
+			vif1Regs->stat.FQC = 0x10; // FQC=16
 		}
 		vif1.inprogress &= ~0x10;
 		
@@ -615,7 +615,7 @@ void vifMFIFOInterrupt()
 	
 	if (schedulepath3msk) Vif1MskPath3();
 
-	if ((vif1Regs->stat & VIF1_STAT_VGW))
+	if ((vif1Regs->stat.VGW))
 	{
 		if (gif->chcr.STR)
 		{			
@@ -624,7 +624,7 @@ void vifMFIFOInterrupt()
 		} 
 		else 
 		{
-			vif1Regs->stat &= ~VIF1_STAT_VGW;
+			vif1Regs->stat.VGW = 0;
 		}
 	
 	}
@@ -637,12 +637,12 @@ void vifMFIFOInterrupt()
 
 	if (vif1.irq && vif1.tag.size == 0)
 	{
-		vif1Regs->stat |= VIF1_STAT_INT;
+		vif1Regs->stat.INT = 1;
 		hwIntcIrq(INTC_VIF1);
 		--vif1.irq;
-		if (vif1Regs->stat & (VIF1_STAT_VSS | VIF1_STAT_VIS | VIF1_STAT_VFS))
+		if (vif1Regs->stat._u32 & (VIF1_STAT_VSS | VIF1_STAT_VIS | VIF1_STAT_VFS))
 		{
-			vif1Regs->stat &= ~VIF1_STAT_FQC; // FQC=0
+			vif1Regs->stat.FQC = 0; // FQC=0
 			vif1ch->chcr.STR = 0;
 			return;
 		}
@@ -660,13 +660,13 @@ void vifMFIFOInterrupt()
 				//	Console.WriteLn("Empty 1");
 					vifqwc = 0;
 					vif1.inprogress |= 0x10;
-					vif1Regs->stat &= ~VIF1_STAT_FQC; // FQC=0
+					vif1Regs->stat.FQC = 0; // FQC=0
 					hwDmacIrq(DMAC_MFIFO_EMPTY);
 					return;
 				}
 
 				 mfifoVIF1transfer(0);
-				 if (vif1ch->madr >= dmacRegs->rbor.ADDR && vif1ch->madr <= (dmacRegs->rbor.ADDR + dmacRegs->rbsr.RMSK))
+				 if ((vif1ch->madr >= dmacRegs->rbor.ADDR) && (vif1ch->madr <= (dmacRegs->rbor.ADDR + dmacRegs->rbsr.RMSK)))
 					CPU_INT(10, 0);
 				else
 					CPU_INT(10, vif1ch->qwc * BIAS);
@@ -684,7 +684,7 @@ void vifMFIFOInterrupt()
 	{
 		//Console.WriteLn("Empty 2");
 		//vif1.inprogress |= 0x10;
-		vif1Regs->stat &= ~VIF1_STAT_FQC; // FQC=0
+		vif1Regs->stat.FQC = 0; // FQC=0
 		hwDmacIrq(DMAC_MFIFO_EMPTY);
 	}*/
 
@@ -694,6 +694,6 @@ void vifMFIFOInterrupt()
 	hwDmacIrq(DMAC_VIF1);
 	VIF_LOG("vif mfifo dma end");
 
-	vif1Regs->stat &= ~VIF1_STAT_FQC; // FQC=0
+	vif1Regs->stat.FQC = 0; // FQC=0
 
 }
diff --git a/pcsx2/Vif.h b/pcsx2/Vif.h
index 092cb23fa6..ea42ce22bc 100644
--- a/pcsx2/Vif.h
+++ b/pcsx2/Vif.h
@@ -73,6 +73,14 @@ enum vif_stat_flags
 	VIF_STAT_ER1		= (1<<13)
 };
 
+enum vif_status
+{
+    VPS_IDLE = 0,
+    VPS_WAITING = 1,
+    VPS_DECODING = 2,
+    VPS_TRANSFERRING = 3 // And decompressing.
+};
+
 //
 // Bitfield Structure
 //
@@ -124,7 +132,7 @@ struct vifCycle {
 };
 
 struct VIFregisters {
-	u32 stat;
+	tVIF_STAT stat;
 	u32 pad0[3];
 	u32 fbrst;
 	u32 pad1[3];
diff --git a/pcsx2/VifDma.cpp b/pcsx2/VifDma.cpp
index eb14fe587b..e7b7e8cfd8 100644
--- a/pcsx2/VifDma.cpp
+++ b/pcsx2/VifDma.cpp
@@ -892,17 +892,17 @@ static void vuExecMicro(u32 addr, const u32 VIFdmanum)
 		VU->vifRegs->top = VU->vifRegs->tops & 0x3ff;
 
 		/* is DBF flag set in VIF_STAT? */
-		if (VU->vifRegs->stat & VIF_STAT_DBF)
+		if (VU->vifRegs->stat.DBF)
 		{
-			/* it is, so set tops with base, and set the stat DBF flag */
+			/* it is, so set tops with base, and clear the stat DBF flag */
 			VU->vifRegs->tops = VU->vifRegs->base;
-			VU->vifRegs->stat &= ~VIF_STAT_DBF;
+			VU->vifRegs->stat.DBF = 0;
 		}
 		else
 		{
-			/* it is not, so set tops with base + ofst,  and clear stat DBF flag */
+			/* it is not, so set tops with base + offset,  and set stat DBF flag */
 			VU->vifRegs->tops = VU->vifRegs->base + VU->vifRegs->ofst;
-			VU->vifRegs->stat |= VIF_STAT_DBF;
+			VU->vifRegs->stat.DBF = 1;
 		}
 	}
 
@@ -1178,7 +1178,7 @@ static void Vif0CMDSTMod()  // STMOD
 static void Vif0CMDMark()  // MARK
 {
 	vif0Regs->mark = (u16)vif0Regs->code;
-	vif0Regs->stat |= VIF0_STAT_MRK;
+	vif0Regs->stat.MRK = 1;
 	vif0.cmd &= ~0x7f;
 }
 
@@ -1227,7 +1227,7 @@ static void Vif0CMDNull()  // invalid opcode
 	if (!(vif0Regs->err.ME1))    //Ignore vifcode and tag mismatch error
 	{
 		Console.WriteLn("UNKNOWN VifCmd: %x", vif0.cmd);
-		vif0Regs->stat |= VIF0_STAT_ER1;
+		vif0Regs->stat.ER1 = 1;
 		vif0.irq++;
 	}
 	vif0.cmd &= ~0x7f;
@@ -1247,12 +1247,12 @@ int VIF0transfer(u32 *data, int size, int istag)
 	{
 		if (vif0.cmd)
 		{
-			vif0Regs->stat |= VIF0_STAT_VPS_T; //Decompression has started
+			vif0Regs->stat.VPS = VPS_TRANSFERRING; //Decompression has started
 
 			ret = Vif0TransTLB[(vif0.cmd & 0x7f)](data);
 			data += ret;
 			vif0.vifpacketsize -= ret;
-			if (vif0.cmd == 0) vif0Regs->stat &= ~VIF0_STAT_VPS_T; //We are once again waiting for a new vifcode as the command has cleared
+			if (vif0.cmd == 0) vif0Regs->stat.VPS = VPS_IDLE; //We are once again waiting for a new vifcode as the command has cleared
 			continue;
 		}
 
@@ -1264,7 +1264,7 @@ int VIF0transfer(u32 *data, int size, int istag)
 		vif0.cmd = (data[0] >> 24);
 		vif0Regs->code = data[0];
 
-		vif0Regs->stat |= VIF0_STAT_VPS_D; //We need to set these (Onimusha needs it)
+		vif0Regs->stat.VPS |= VPS_DECODING; //We need to set these (Onimusha needs it)
 
 		if ((vif0.cmd & 0x60) == 0x60)
 		{
@@ -1279,7 +1279,7 @@ int VIF0transfer(u32 *data, int size, int istag)
 				if (!(vif0Regs->err.ME1))    //Ignore vifcode and tag mismatch error
 				{
 					Console.WriteLn("UNKNOWN VifCmd: %x", vif0.cmd);
-					vif0Regs->stat |= VIF0_STAT_ER1;
+					vif0Regs->stat.ER1 = 1;
 					vif0.irq++;
 				}
 				vif0.cmd = 0;
@@ -1318,7 +1318,7 @@ int VIF0transfer(u32 *data, int size, int istag)
 	{
 		vif0.vifstalled = true;
 
-		if (((vif0Regs->code >> 24) & 0x7f) != 0x7)vif0Regs->stat |= VIF0_STAT_VIS;
+		if (((vif0Regs->code >> 24) & 0x7f) != 0x7) vif0Regs->stat.VIS = 1;
 		//else Console.WriteLn("VIF0 IRQ on MARK");
 
 		// spiderman doesn't break on qw boundaries
@@ -1334,8 +1334,8 @@ int VIF0transfer(u32 *data, int size, int istag)
 		return -2;
 	}
 
-	vif0Regs->stat &= ~VIF0_STAT_VPS; //Vif goes idle as the stall happened between commands;
-	if (vif0.cmd) vif0Regs->stat |= VIF0_STAT_VPS_W;  //Otherwise we wait for the data
+	vif0Regs->stat.VPS = 0; //Vif goes idle as the stall happened between commands;
+	if (vif0.cmd) vif0Regs->stat.VPS |= VPS_WAITING;  //Otherwise we wait for the data
 
 	if (!istag)
 	{
@@ -1421,13 +1421,13 @@ void  vif0Interrupt()
 
 	if (vif0.irq && (vif0.tag.size == 0))
 	{
-		vif0Regs->stat |= VIF0_STAT_INT;
+		vif0Regs->stat.INT = 1;
 		hwIntcIrq(VIF0intc);
 		--vif0.irq;
 
-		if (vif0Regs->stat & (VIF0_STAT_VSS | VIF0_STAT_VIS | VIF0_STAT_VFS))
+		if (vif0Regs->stat._u32 & (VIF0_STAT_VSS | VIF0_STAT_VIS | VIF0_STAT_VFS))
 		{
-			vif0Regs->stat &= ~VIF0_STAT_FQC; // FQC=0
+			vif0Regs->stat.FQC = 0; // FQC=0
 			vif0ch->chcr.STR = 0;
 			return;
 		}
@@ -1469,7 +1469,7 @@ void  vif0Interrupt()
 
 	vif0ch->chcr.STR = 0;
 	hwDmacIrq(DMAC_VIF0);
-	vif0Regs->stat &= ~VIF0_STAT_FQC; // FQC=0
+	vif0Regs->stat.FQC = 0; // FQC=0
 }
 
 //  Vif1 Data Transfer Table
@@ -1517,13 +1517,14 @@ void dmaVIF0()
 
 	g_vifCycles = 0;
 
-	vif0Regs->stat |= 0x8000000; // FQC=8
+	vif0Regs->stat.FQC = 0x8; // FQC=8
 
 	if (!(vif0ch->chcr.MOD & 0x1) || vif0ch->qwc > 0)   // Normal Mode
 	{
 		if (_VIF0chain() == -2)
 		{
-			Console.WriteLn("Stall on normal %x", vif0Regs->stat);
+			Console.WriteLn("Stall on normal %x", vif0Regs->stat._u32);
+			
 			vif0.vifstalled = true;
 			return;
 		}
@@ -1546,7 +1547,7 @@ void vif0Write32(u32 mem, u32 value)
 			VIF_LOG("VIF0_MARK write32 0x%8.8x", value);
 
 			/* Clear mark flag in VIF0_STAT and set mark with 'value' */
-			vif0Regs->stat &= ~VIF0_STAT_MRK;
+			vif0Regs->stat.MRK = 0;
 			vif0Regs->mark = value;
 			break;
 
@@ -1556,7 +1557,9 @@ void vif0Write32(u32 mem, u32 value)
 			if (value & 0x1)
 			{
 				/* Reset VIF */
-				//Console.WriteLn("Vif0 Reset %x", vif0Regs->stat);
+				
+				//Console.WriteLn("Vif0 Reset %x", vif0Regs->stat._u32);
+				
 				memzero(vif0);
 				vif0ch->qwc = 0; //?
 				cpuRegs.interrupt &= ~1; //Stop all vif0 DMA's
@@ -1564,7 +1567,7 @@ void vif0Write32(u32 mem, u32 value)
 				psHu64(VIF0_FIFO + 8) = 0; // VIF0_FIFO + 8
 				vif0.done = true;
 				vif0Regs->err._u32 = 0;
-				vif0Regs->stat &= ~(VIF0_STAT_FQC | VIF0_STAT_INT | VIF0_STAT_VSS | VIF0_STAT_VIS | VIF0_STAT_VFS | VIF0_STAT_VPS); // FQC=0
+				vif0Regs->stat._u32 &= ~(VIF0_STAT_FQC | VIF0_STAT_INT | VIF0_STAT_VSS | VIF0_STAT_VIS | VIF0_STAT_VFS | VIF0_STAT_VPS); // FQC=0
 			}
 
 			if (value & 0x2)
@@ -1572,8 +1575,8 @@ void vif0Write32(u32 mem, u32 value)
 				/* Force Break the VIF */
 				/* I guess we should stop the VIF dma here, but not 100% sure (linuz) */
 				cpuRegs.interrupt &= ~1; //Stop all vif0 DMA's
-				vif0Regs->stat |= VIF0_STAT_VFS;
-				vif0Regs->stat &= ~VIF0_STAT_VPS;
+				vif0Regs->stat.VFS = 1;
+				vif0Regs->stat.VPS = 0;
 				vif0.vifstalled = true;
 				Console.WriteLn("vif0 force break");
 			}
@@ -1583,8 +1586,8 @@ void vif0Write32(u32 mem, u32 value)
 				/* Stop VIF */
 				// Not completely sure about this, can't remember what game, used this, but 'draining' the VIF helped it, instead of
 				//  just stoppin the VIF (linuz).
-				vif0Regs->stat |= VIF0_STAT_VSS;
-				vif0Regs->stat &= ~VIF0_STAT_VPS;
+				vif0Regs->stat.VSS = 1;
+				vif0Regs->stat.VPS = 0;
 				vif0.vifstalled = true;
 			}
 
@@ -1593,10 +1596,10 @@ void vif0Write32(u32 mem, u32 value)
 				bool cancel = false;
 
 				/* Cancel stall, first check if there is a stall to cancel, and then clear VIF0_STAT VSS|VFS|VIS|INT|ER0|ER1 bits */
-				if (vif0Regs->stat & (VIF0_STAT_VSS | VIF0_STAT_VIS | VIF0_STAT_VFS))
+				if (vif0Regs->stat._u32 & (VIF0_STAT_VSS | VIF0_STAT_VIS | VIF0_STAT_VFS))
 					cancel = true;
 
-				vif0Regs->stat &= ~(VIF0_STAT_VSS | VIF0_STAT_VFS | VIF0_STAT_VIS |
+				vif0Regs->stat._u32 &= ~(VIF0_STAT_VSS | VIF0_STAT_VFS | VIF0_STAT_VIS |
 						    VIF0_STAT_INT | VIF0_STAT_ER0 | VIF0_STAT_ER1);
 				if (cancel)
 				{
@@ -1657,9 +1660,9 @@ void vif0Reset()
 	SetNewMask(g_vif0Masks, g_vif0HasMask3, 0, 0xffffffff);
 	psHu64(VIF0_FIFO) = 0;
 	psHu64(VIF0_FIFO + 8) = 0;
-	vif0Regs->stat &= ~VIF0_STAT_VPS;
+	vif0Regs->stat.VPS = 0;
 	vif0.done = true;
-	vif0Regs->stat &= ~VIF0_STAT_FQC; // FQC=0
+	vif0Regs->stat.FQC = 0; // FQC=0
 }
 
 void SaveStateBase::vif0Freeze()
@@ -1869,7 +1872,7 @@ static int __fastcall Vif1TransDirectHL(u32 *data)
 	{
 		if (gif->chcr.STR && (!vif1Regs->mskpath3 && (Path3progress == IMAGE_MODE))) //PATH3 is in image mode, so wait for end of transfer
 		{
-			vif1Regs->stat |= VIF1_STAT_VGW;
+			vif1Regs->stat.VGW = 1;
 			return 0;
 		}
 	}
@@ -2013,7 +2016,7 @@ static void Vif1CMDSTCycl()  // STCYCL
 static void Vif1CMDOffset()  // OFFSET
 {
 	vif1Regs->ofst  = vif1Regs->code & 0x3ff;
-	vif1Regs->stat &= ~VIF1_STAT_DBF;
+	vif1Regs->stat.DBF = 0;
 	vif1Regs->tops  = vif1Regs->base;
 	vif1.cmd &= ~0x7f;
 }
@@ -2076,7 +2079,7 @@ static void Vif1CMDMskPath3()  // MSKPATH3
 static void Vif1CMDMark()  // MARK
 {
 	vif1Regs->mark = (u16)vif1Regs->code;
-	vif1Regs->stat |= VIF1_STAT_MRK;
+	vif1Regs->stat.MRK = 1;
 	vif1.cmd &= ~0x7f;
 }
 
@@ -2089,7 +2092,7 @@ static void Vif1CMDFlush()  // FLUSH/E/A
 		// Gif is already transferring so wait for it.
 		if (((Path3progress != STOPPED_MODE) || !vif1Regs->mskpath3) && gif->chcr.STR)
 		{
-			vif1Regs->stat |= VIF1_STAT_VGW;
+			vif1Regs->stat.VGW = 1;
 			CPU_INT(2, 4);
 		}
 	}
@@ -2151,7 +2154,7 @@ static void Vif1CMDNull()  // invalid opcode
 	if (!(vif1Regs->err.ME1))   //Ignore vifcode and tag mismatch error
 	{
 		Console.WriteLn("UNKNOWN VifCmd: %x\n", vif1.cmd);
-		vif1Regs->stat |= VIF1_STAT_ER1;
+		vif1Regs->stat.ER1 = 1;
 		vif1.irq++;
 	}
 	vif1.cmd = 0;
@@ -2213,18 +2216,18 @@ int VIF1transfer(u32 *data, int size, int istag)
 
 	while (vif1.vifpacketsize > 0)
 	{
-		if(vif1Regs->stat & VIF1_STAT_VGW) break;
+		if(vif1Regs->stat.VGW) break;
 
 		if (vif1.cmd)
 		{
-			vif1Regs->stat |= VIF1_STAT_VPS_T; //Decompression has started
+			vif1Regs->stat.VPS = VPS_TRANSFERRING; //Decompression has started
 
 			ret = Vif1TransTLB[vif1.cmd](data);
 			data += ret;
 			vif1.vifpacketsize -= ret;
 
 			//We are once again waiting for a new vifcode as the command has cleared
-			if (vif1.cmd == 0) vif1Regs->stat &= ~VIF1_STAT_VPS_T;
+			if (vif1.cmd == 0) vif1Regs->stat.VPS = VPS_IDLE;
 			continue;
 		}
 
@@ -2235,7 +2238,7 @@ int VIF1transfer(u32 *data, int size, int istag)
 		vif1.cmd = (data[0] >> 24);
 		vif1Regs->code = data[0];
 
-		vif1Regs->stat |= VIF1_STAT_VPS_D;
+		vif1Regs->stat.VPS |= VPS_DECODING;
 		if ((vif1.cmd & 0x60) == 0x60)
 		{
 			vif1UNPACK(data);
@@ -2249,7 +2252,7 @@ int VIF1transfer(u32 *data, int size, int istag)
 				if (!(vif0Regs->err.ME1))    //Ignore vifcode and tag mismatch error
 				{
 					Console.WriteLn("UNKNOWN VifCmd: %x", vif1.cmd);
-					vif1Regs->stat |= VIF1_STAT_ER1;
+					vif1Regs->stat.ER1 = 1;
 					vif1.irq++;
 				}
 				vif1.cmd = 0;
@@ -2276,9 +2279,9 @@ int VIF1transfer(u32 *data, int size, int istag)
 			}
 		}
 
-		if(!vif1.cmd) vif1Regs->stat &= ~VIF1_STAT_VPS_D;
+		if(!vif1.cmd) vif1Regs->stat.VPS = VPS_IDLE;
 
-		if((vif1Regs->stat & VIF1_STAT_VGW) || vif1.vifstalled == true) break;
+		if((vif1Regs->stat.VGW) || vif1.vifstalled == true) break;
 	} // End of Transfer loop
 
 	transferred += size - vif1.vifpacketsize;
@@ -2289,7 +2292,7 @@ int VIF1transfer(u32 *data, int size, int istag)
 	{
 		vif1.vifstalled = true;
 
-		if (((vif1Regs->code >> 24) & 0x7f) != 0x7) vif1Regs->stat |= VIF1_STAT_VIS; // Note: commenting this out fixes WALL-E
+		if (((vif1Regs->code >> 24) & 0x7f) != 0x7) vif1Regs->stat.VIS = 1; // Note: commenting this out fixes WALL-E
 
 		if (vif1ch->qwc == 0 && (vif1.irqoffset == 0 || istag == 1)) vif1.inprogress &= ~0x1;
 
@@ -2305,8 +2308,8 @@ int VIF1transfer(u32 *data, int size, int istag)
 		return -2;
 	}
 
-	vif1Regs->stat &= ~VIF1_STAT_VPS; //Vif goes idle as the stall happened between commands;
-	if (vif1.cmd) vif1Regs->stat |= VIF1_STAT_VPS_W;  //Otherwise we wait for the data
+	vif1Regs->stat.VPS = 0; //Vif goes idle as the stall happened between commands;
+	if (vif1.cmd) vif1Regs->stat.VPS |= VPS_WAITING;  //Otherwise we wait for the data
 
 	if (!istag)
 	{
@@ -2315,7 +2318,7 @@ int VIF1transfer(u32 *data, int size, int istag)
 		vif1ch->qwc -= transferred;
 	}
 
-	if(vif1Regs->stat & VIF1_STAT_VGW)
+	if (vif1Regs->stat.VGW)
 	{
 		vif1.vifstalled = true;
 	}
@@ -2337,7 +2340,7 @@ void vif1TransferFromMemory()
 		Console.WriteLn("Vif1 Tag BUSERR");
 		dmacRegs->stat.BEIS = 1;      //If yes, set BEIS (BUSERR) in DMAC_STAT register
 		vif1.done = true;
-		vif1Regs->stat &= ~VIF1_STAT_FQC;
+		vif1Regs->stat.FQC = 0;
 		vif1ch->qwc = 0;
 		CPU_INT(1, 0);
 
@@ -2501,29 +2504,31 @@ __forceinline void vif1Interrupt()
 
 	g_vifCycles = 0;
 
-	if(schedulepath3msk) Vif1MskPath3();
+	if (schedulepath3msk) Vif1MskPath3();
 
-	if((vif1Regs->stat & VIF1_STAT_VGW))
+	if ((vif1Regs->stat.VGW))
 	{
 		if (gif->chcr.STR)
 		{
 			CPU_INT(1, gif->qwc * BIAS);
 			return;
 		}
-		else vif1Regs->stat &= ~VIF1_STAT_VGW;
-
+		else 
+		{
+		    vif1Regs->stat.VGW = 0;
+		}
 	}
 
 	if (!(vif1ch->chcr.STR)) Console.WriteLn("Vif1 running when CHCR == %x", vif1ch->chcr._u32);
 
 	if (vif1.irq && vif1.tag.size == 0)
 	{
-		vif1Regs->stat |= VIF1_STAT_INT;
+		vif1Regs->stat.INT = 1;
 		hwIntcIrq(VIF1intc);
 		--vif1.irq;
-		if (vif1Regs->stat & (VIF1_STAT_VSS | VIF1_STAT_VIS | VIF1_STAT_VFS))
+		if (vif1Regs->stat._u32 & (VIF1_STAT_VSS | VIF1_STAT_VIS | VIF1_STAT_VFS))
 		{
-			vif1Regs->stat &= ~VIF1_STAT_FQC; // FQC=0
+			vif1Regs->stat.FQC = 0; // FQC=0
 
 			// One game doesnt like vif stalling at end, cant remember what. Spiderman isnt keen on it tho
 			vif1ch->chcr.STR = 0;
@@ -2570,7 +2575,7 @@ __forceinline void vif1Interrupt()
 	if (vif1.cmd != 0) Console.WriteLn("vif1.cmd still set %x tag size %x", vif1.cmd, vif1.tag.size);
 #endif
 
-	vif1Regs->stat &= ~VIF1_STAT_VPS; //Vif goes idle as the stall happened between commands;
+	vif1Regs->stat.VPS = 0; //Vif goes idle as the stall happened between commands;
 	vif1ch->chcr.STR = 0;
 	g_vifCycles = 0;
 	hwDmacIrq(DMAC_VIF1);
@@ -2579,7 +2584,7 @@ __forceinline void vif1Interrupt()
 	//Games effected by setting, Fatal Frame, KH2, Shox, Crash N Burn, GT3/4 possibly
 	//Im guessing due to the full gs fifo before the reverse? (Refraction)
 	//Note also this is only the condition for reverse fifo mode, normal direction clears it as normal
-	if (!vif1Regs->mskpath3 || vif1ch->chcr.DIR) vif1Regs->stat &= ~0x1F000000; // FQC=0
+	if (!vif1Regs->mskpath3 || vif1ch->chcr.DIR) vif1Regs->stat.FQC = 0; // FQC=0
 }
 
 void dmaVIF1()
@@ -2625,9 +2630,9 @@ void dmaVIF1()
 	}
 
 	if (vif1.dmamode != VIF_NORMAL_FROM_MEM_MODE)
-		vif1Regs->stat |= 0x10000000; // FQC=16
+		vif1Regs->stat.FQC = 0x10; // FQC=16
 	else
-		vif1Regs->stat |= min((u16)16, vif1ch->qwc) << 24; // FQC=16
+		vif1Regs->stat._u32 |= min((u16)16, vif1ch->qwc) << 24; // FQC=16
 
 	// Chain Mode
 	vif1.done = false;
@@ -2642,7 +2647,7 @@ void vif1Write32(u32 mem, u32 value)
 			VIF_LOG("VIF1_MARK write32 0x%8.8x", value);
 
 			/* Clear mark flag in VIF1_STAT and set mark with 'value' */
-			vif1Regs->stat &= ~VIF1_STAT_MRK;
+			vif1Regs->stat.MRK = 0;
 			vif1Regs->mark = value;
 			break;
 
@@ -2668,15 +2673,15 @@ void vif1Write32(u32 mem, u32 value)
 
 				vif1Regs->err._u32 = 0;
 				vif1.inprogress = 0;
-				vif1Regs->stat &= ~(VIF1_STAT_FQC | VIF1_STAT_FDR | VIF1_STAT_INT | VIF1_STAT_VSS | VIF1_STAT_VIS | VIF1_STAT_VFS | VIF1_STAT_VPS); // FQC=0
+				vif1Regs->stat._u32 &= ~(VIF1_STAT_FQC | VIF1_STAT_FDR | VIF1_STAT_INT | VIF1_STAT_VSS | VIF1_STAT_VIS | VIF1_STAT_VFS | VIF1_STAT_VPS); // FQC=0
 			}
 
 			if (value & 0x2)
 			{
 				/* Force Break the VIF */
 				/* I guess we should stop the VIF dma here, but not 100% sure (linuz) */
-				vif1Regs->stat |= VIF1_STAT_VFS;
-				vif1Regs->stat &= ~VIF1_STAT_VPS;
+				vif1Regs->stat.VFS = 1;
+				vif1Regs->stat.VPS = 0;
 				cpuRegs.interrupt &= ~((1 << 1) | (1 << 10)); //Stop all vif1 DMA's
 				vif1.vifstalled = true;
 				Console.WriteLn("vif1 force break");
@@ -2687,8 +2692,8 @@ void vif1Write32(u32 mem, u32 value)
 				/* Stop VIF */
 				// Not completely sure about this, can't remember what game used this, but 'draining' the VIF helped it, instead of
 				//   just stoppin the VIF (linuz).
-				vif1Regs->stat |= VIF1_STAT_VSS;
-				vif1Regs->stat &= ~VIF1_STAT_VPS;
+				vif1Regs->stat.VSS = 1;
+				vif1Regs->stat.VPS = 0;
 				cpuRegs.interrupt &= ~((1 << 1) | (1 << 10)); //Stop all vif1 DMA's
 				vif1.vifstalled = true;
 			}
@@ -2698,12 +2703,12 @@ void vif1Write32(u32 mem, u32 value)
 				bool cancel = false;
 
 				/* Cancel stall, first check if there is a stall to cancel, and then clear VIF1_STAT VSS|VFS|VIS|INT|ER0|ER1 bits */
-				if (vif1Regs->stat & (VIF1_STAT_VSS | VIF1_STAT_VIS | VIF1_STAT_VFS))
+				if (vif1Regs->stat._u32 & (VIF1_STAT_VSS | VIF1_STAT_VIS | VIF1_STAT_VFS))
 				{
 					cancel = true;
 				}
 
-				vif1Regs->stat &= ~(VIF1_STAT_VSS | VIF1_STAT_VFS | VIF1_STAT_VIS |
+				vif1Regs->stat._u32 &= ~(VIF1_STAT_VSS | VIF1_STAT_VFS | VIF1_STAT_VIS |
 						VIF1_STAT_INT | VIF1_STAT_ER0 | VIF1_STAT_ER1);
 
 				if (cancel)
@@ -2712,16 +2717,21 @@ void vif1Write32(u32 mem, u32 value)
 					{
 						g_vifCycles = 0;
 						// loop necessary for spiderman
-						if ((psHu32(DMAC_CTRL) & 0xC) == 0x8)
+						switch(dmacRegs->ctrl.MFD)
 						{
-							//Console.WriteLn("MFIFO Stall");
-							CPU_INT(10, vif1ch->qwc * BIAS);
-						}
-						else
-						{
-							// Gets the timing right - Flatout
-							CPU_INT(1, vif1ch->qwc * BIAS);
+						    case MFD_VIF1:
+                                //Console.WriteLn("MFIFO Stall");
+                                CPU_INT(10, vif1ch->qwc * BIAS);
+                                break;
+                            
+                            case NO_MFD:
+                            case MFD_RESERVED:
+                            case MFD_GIF: // Wonder if this should be with VIF?
+                                // Gets the timing right - Flatout
+                                CPU_INT(1, vif1ch->qwc * BIAS);
+                                break;
 						}
+						
 						vif1ch->chcr.STR = 1;
 					}
 				}
@@ -2740,27 +2750,27 @@ void vif1Write32(u32 mem, u32 value)
 
 #ifdef PCSX2_DEVBUILD
 			/* Only FDR bit is writable, so mask the rest */
-			if ((vif1Regs->stat & VIF1_STAT_FDR) ^(value & VIF1_STAT_FDR))
+			if ((vif1Regs->stat.FDR) ^(value & VIF1_STAT_FDR))
 			{
 				// different so can't be stalled
-				if (vif1Regs->stat & (VIF1_STAT_INT | VIF1_STAT_VSS | VIF1_STAT_VIS | VIF1_STAT_VFS))
+				if (vif1Regs->stat._u32 & (VIF1_STAT_INT | VIF1_STAT_VSS | VIF1_STAT_VIS | VIF1_STAT_VFS))
 				{
 					DevCon.WriteLn("changing dir when vif1 fifo stalled");
 				}
 			}
 #endif
 
-			vif1Regs->stat = (vif1Regs->stat & ~VIF1_STAT_FDR) | (value & VIF1_STAT_FDR);
-			if (vif1Regs->stat & VIF1_STAT_FDR)
+			vif1Regs->stat._u32 = (vif1Regs->stat._u32 & ~VIF1_STAT_FDR) | (value & VIF1_STAT_FDR);
+			if (vif1Regs->stat.FDR)
 			{
-				vif1Regs->stat |= 0x01000000; // FQC=1 - hack but it checks this is true before transfer? (fatal frame)
+				vif1Regs->stat.FQC = 1; // FQC=1 - hack but it checks this is true before transfer? (fatal frame)
 			}
 			else
 			{
 				vif1ch->qwc = 0;
 				vif1.vifstalled = false;
 				vif1.done = true;
-				vif1Regs->stat &= ~VIF1_STAT_FQC; // FQC=0
+				vif1Regs->stat.FQC = 0; // FQC=0
 			}
 			break;
 
@@ -2799,12 +2809,15 @@ void vif1Reset()
 	memzero(vif1);
 	memzero(*vif1Regs);
 	SetNewMask(g_vif1Masks, g_vif1HasMask3, 0, 0xffffffff);
+	
 	psHu64(VIF1_FIFO) = 0;
 	psHu64(VIF1_FIFO + 8) = 0;
-	vif1Regs->stat &= ~VIF1_STAT_VPS;
+	
+	vif1Regs->stat.VPS = 0;
+	vif1Regs->stat.FQC = 0; // FQC=0
+	
 	vif1.done = true;
 	cpuRegs.interrupt &= ~((1 << 1) | (1 << 10)); //Stop all vif1 DMA's
-	vif1Regs->stat &= ~VIF1_STAT_FQC; // FQC=0
 }
 
 void SaveStateBase::vif1Freeze()
diff --git a/pcsx2/gui/Panels/BiosSelectorPanel.cpp b/pcsx2/gui/Panels/BiosSelectorPanel.cpp
index d9fec0ddee..2d35998edc 100644
--- a/pcsx2/gui/Panels/BiosSelectorPanel.cpp
+++ b/pcsx2/gui/Panels/BiosSelectorPanel.cpp
@@ -98,7 +98,7 @@ bool Panels::BiosSelectorPanel::ValidateEnumerationStatus()
 	ScopedPtr<wxArrayString> bioslist( new wxArrayString() );
 
 	if( m_FolderPicker.GetPath().Exists() )
-		wxDir::GetAllFiles( m_FolderPicker.GetPath().ToString(), bioslist, L"*.bin", wxDIR_FILES );
+		wxDir::GetAllFiles( m_FolderPicker.GetPath().ToString(), bioslist, L"*.*", wxDIR_FILES );
 
 	if( !m_BiosList || (*bioslist != *m_BiosList) )
 		validated = false;