mirror of https://github.com/PCSX2/pcsx2.git
common: remove old memcpy implementation
PCSX2 used standard memcpy now (thanks to xsacha)
This commit is contained in:
Gregory Hainaut
parent
4d818f6cd9
commit
69e88ffed0
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@ -32,10 +32,6 @@ extern u8 memcmp_mmx(const void* src1, const void* src2, int cmpsize);
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// Only used in the Windows version of memzero.h. But it's in Misc.cpp for some reason.
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void _memset16_unaligned( void* dest, u16 data, size_t size );
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// MemcpyVibes.cpp functions
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extern void memcpy_vibes(void * dest, const void * src, int size);
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extern void gen_memcpy_vibes();
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#define memcpy_fast memcpy
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#define memcpy_aligned(d,s,c) memcpy(d,s,c)
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#define memcpy_const memcpy
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@ -128,7 +128,6 @@ set(UtilitiesSources
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wxAppWithHelpers.cpp
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wxGuiTools.cpp
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wxHelpers.cpp
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x86/MemcpyVibes.cpp
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)
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# variable with all headers of this library
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@ -31,290 +31,19 @@
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3dsdk.support@amd.com
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******************************************************************************/
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// GH: AMD memcpy was removed. The remaining part (memcmp_mmx) is likely from Zerofrog.
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// Hopefully memcmp_mmx will be dropped in the future.
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#include "PrecompiledHeader.h"
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#ifdef _MSC_VER
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#pragma warning(disable:4414)
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#endif
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/*****************************************************************************
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MEMCPY_AMD.CPP
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******************************************************************************/
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// NOTE: Since this code uses MOVNTQ (also known as "Non-Temporal MOV" or
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// "Streaming Store"), and also uses the software prefetch instructions,
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// be sure you're running on P4/Core2/i7, Athlon/Phenom or newer CPUs before
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// calling!
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#define TINY_BLOCK_COPY 64 // upper limit for movsd type copy
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// The smallest copy uses the X86 "movsd" instruction, in an optimized
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// form which is an "unrolled loop".
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#define IN_CACHE_COPY 2 * 1024 // upper limit for movq/movq copy w/SW prefetch
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// Next is a copy that uses the MMX registers to copy 8 bytes at a time,
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// also using the "unrolled loop" optimization. This code uses
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// the software prefetch instruction to get the data into the cache.
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#define UNCACHED_COPY 4 * 1024 // upper limit for movq/movntq w/SW prefetch
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// For larger blocks, which will spill beyond the cache, it's faster to
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// use the Streaming Store instruction MOVNTQ. This write instruction
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// bypasses the cache and writes straight to main memory. This code also
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// uses the software prefetch instruction to pre-read the data.
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// USE 64 * 1024 FOR THIS VALUE IF YOU'RE ALWAYS FILLING A "CLEAN CACHE"
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// Inline assembly syntax for use with Visual C++
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#if defined(_MSC_VER)
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// Fast memcpy as coded by AMD, and then improved by air for PCSX2 needs.
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__declspec(naked) void __fastcall memcpy_amd_(void *dest, const void *src, size_t n)
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{
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__asm
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{
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push edi
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push esi
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mov edi, ecx ; destination
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mov esi, edx ; source
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mov ecx, [esp+12] ; number of bytes to copy
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mov eax, ecx ; keep a copy of count
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cld
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cmp eax, TINY_BLOCK_COPY
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jb $memcpy_ic_3 ; tiny? skip mmx copy
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cmp eax, 32*1024 ; dont align between 32k-64k because
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jbe $memcpy_do_align ; it appears to be slower
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cmp eax, 64*1024
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jbe $memcpy_align_done
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$memcpy_do_align:
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mov eax, 8 ; a trick that s faster than rep movsb...
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sub eax, edi ; align destination to qword
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and eax, 111b ; get the low bits
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sub ecx, eax ; update copy count
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neg eax ; set up to jump into the array
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add eax, offset $memcpy_align_done
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jmp eax ; jump to array of movsb s
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align 4
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movsb
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movsb
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movsb
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movsb
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movsb
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movsb
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movsb
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movsb
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$memcpy_align_done: ; destination is dword aligned
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mov eax, ecx ; number of bytes left to copy
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shr eax, 6 ; get 64-byte block count
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jz $memcpy_ic_2 ; finish the last few bytes
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cmp eax, IN_CACHE_COPY/64 ; too big 4 cache? use uncached copy
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jae $memcpy_uc_test
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// This is small block copy that uses the MMX registers to copy 8 bytes
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// at a time. It uses the "unrolled loop" optimization, and also uses
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// the software prefetch instruction to get the data into the cache.
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align 16
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$memcpy_ic_1: ; 64-byte block copies, in-cache copy
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prefetchnta [esi + (200*64/34+192)] ; start reading ahead
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movq mm0, [esi+0] ; read 64 bits
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movq mm1, [esi+8]
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movq [edi+0], mm0 ; write 64 bits
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movq [edi+8], mm1 ; note: the normal movq writes the
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movq mm2, [esi+16] ; data to cache; a cache line will be
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movq mm3, [esi+24] ; allocated as needed, to store the data
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movq [edi+16], mm2
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movq [edi+24], mm3
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movq mm0, [esi+32]
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movq mm1, [esi+40]
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movq [edi+32], mm0
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movq [edi+40], mm1
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movq mm2, [esi+48]
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movq mm3, [esi+56]
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movq [edi+48], mm2
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movq [edi+56], mm3
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add esi, 64 ; update source pointer
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add edi, 64 ; update destination pointer
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sub eax, 1
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jnz $memcpy_ic_1 ; last 64-byte block?
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$memcpy_ic_2:
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mov eax, ecx ; has valid low 6 bits of the byte count
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$memcpy_ic_3:
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shr eax, 2 ; dword count
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and eax, 1111b ; only look at the "remainder" bits
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neg eax ; set up to jump into the array
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add eax, offset $memcpy_last_few
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jmp eax ; jump to array of movsd s
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$memcpy_uc_test:
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or eax, eax ; tail end of block prefetch will jump here
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jz $memcpy_ic_2 ; no more 64-byte blocks left
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// For larger blocks, which will spill beyond the cache, it's faster to
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// use the Streaming Store instruction MOVNTQ. This write instruction
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// bypasses the cache and writes straight to main memory. This code also
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// uses the software prefetch instruction to pre-read the data.
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align 16
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$memcpy_uc_1: ; 64-byte blocks, uncached copy
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prefetchnta [esi + (200*64/34+192)] ; start reading ahead
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movq mm0,[esi+0] ; read 64 bits
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add edi,64 ; update destination pointer
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movq mm1,[esi+8]
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add esi,64 ; update source pointer
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movq mm2,[esi-48]
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movntq [edi-64], mm0 ; write 64 bits, bypassing the cache
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movq mm0,[esi-40] ; note: movntq also prevents the CPU
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movntq [edi-56], mm1 ; from READING the destination address
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movq mm1,[esi-32] ; into the cache, only to be over-written
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movntq [edi-48], mm2 ; so that also helps performance
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movq mm2,[esi-24]
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movntq [edi-40], mm0
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movq mm0,[esi-16]
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movntq [edi-32], mm1
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movq mm1,[esi-8]
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movntq [edi-24], mm2
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movntq [edi-16], mm0
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movntq [edi-8], mm1
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sub eax, 1
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jnz $memcpy_uc_1 ; last 64-byte block?
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jmp $memcpy_ic_2 ; almost done (not needed because large copy below was removed)
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// Note: Pcsx2 rarely invokes large copies, so the large copy "block prefetch" mode has been
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// disabled to help keep the code cache footprint of memcpy_fast to a minimum.
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// The smallest copy uses the X86 "movsd" instruction, in an optimized
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// form which is an "unrolled loop". Then it handles the last few bytes.
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align 16
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movsd
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movsd ; perform last 1-15 dword copies
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movsd
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movsd
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movsd
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movsd
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movsd
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movsd
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movsd
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movsd ; perform last 1-7 dword copies
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movsd
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movsd
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movsd
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movsd
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movsd
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movsd
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$memcpy_last_few: ; dword aligned from before movsd s
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and ecx, 11b ; the last few cows must come home
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jz $memcpy_final ; no more, let s leave
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rep movsb ; the last 1, 2, or 3 bytes
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$memcpy_final:
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pop esi
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pop edi
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emms ; clean up the MMX state
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sfence ; flush the write buffer
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//mov eax, [dest] ; ret value = destination pointer
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ret 4
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}
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}
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// Quadword Copy! Count is in QWCs (128 bits). Neither source nor dest need to be aligned.
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__fi void memcpy_amd_qwc(void *dest, const void *src, size_t qwc)
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{
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// Optimization Analysis: This code is *nearly* optimal. Do not think that using XMM
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// registers will improve copy performance, because they won't. Use of XMMs is only
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// warranted in situations where both source and dest are guaranteed aligned to 16 bytes,
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// and even then the benefits are typically minimal (sometimes slower depending on the
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// amount of data being copied).
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//
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// Thus: MMX are alignment safe, fast, and widely available. Lets just stick with them.
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// --air
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// Linux Conversion note:
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// This code would benefit nicely from having inline-able GAS syntax, since it should
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// allow GCC to optimize the first 3 instructions out of existence in many scenarios.
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// And its called enough times to probably merit the extra effort to ensure proper
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// optimization. --air
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__asm
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{
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mov ecx, dest
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mov edx, src
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mov eax, qwc ; keep a copy of count
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shr eax, 1
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jz $memcpy_qwc_1 ; only one 16 byte block to copy?
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cmp eax, IN_CACHE_COPY/32
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jb $memcpy_qwc_loop1 ; small copies should be cached (definite speedup --air)
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$memcpy_qwc_loop2: ; 32-byte blocks, uncached copy
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prefetchnta [edx + 568] ; start reading ahead (tested: it helps! --air)
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movq mm0,[edx+0] ; read 64 bits
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movq mm1,[edx+8]
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movq mm2,[edx+16]
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movntq [ecx+0], mm0 ; write 64 bits, bypassing the cache
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movntq [ecx+8], mm1
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movq mm3,[edx+24]
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movntq [ecx+16], mm2
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movntq [ecx+24], mm3
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add edx,32 ; update source pointer
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add ecx,32 ; update destination pointer
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sub eax,1
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jnz $memcpy_qwc_loop2 ; last 64-byte block?
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sfence ; flush the write buffer
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jmp $memcpy_qwc_1
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; 32-byte blocks, cached!
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; This *is* important. Removing this and using exclusively non-temporal stores
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; results in noticable speed loss!
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$memcpy_qwc_loop1:
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prefetchnta [edx + 568] ; start reading ahead (tested: it helps! --air)
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movq mm0,[edx+0] ; read 64 bits
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movq mm1,[edx+8]
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movq mm2,[edx+16]
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movq [ecx+0], mm0 ; write 64 bits, bypassing the cache
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movq [ecx+8], mm1
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movq mm3,[edx+24]
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movq [ecx+16], mm2
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movq [ecx+24], mm3
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add edx,32 ; update source pointer
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add ecx,32 ; update destination pointer
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sub eax,1
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jnz $memcpy_qwc_loop1 ; last 64-byte block?
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$memcpy_qwc_1:
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test qwc,1
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jz $memcpy_qwc_final
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movq mm0,[edx]
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movq mm1,[edx+8]
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movq [ecx], mm0
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movq [ecx+8], mm1
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$memcpy_qwc_final:
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emms ; clean up the MMX state
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}
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}
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// mmx mem-compare implementation, size has to be a multiple of 8
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// returns 0 is equal, nonzero value if not equal
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// ~10 times faster than standard memcmp
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@ -489,112 +218,4 @@ End:
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}
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}
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// returns the xor of all elements, cmpsize has to be mult of 8
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void memxor_mmx(void* dst, const void* src1, int cmpsize)
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{
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pxAssert( (cmpsize&7) == 0 );
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__asm {
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mov ecx, cmpsize
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mov eax, src1
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mov edx, dst
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cmp ecx, 64
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jl Setup4
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movq mm0, [eax]
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movq mm1, [eax+8]
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movq mm2, [eax+16]
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movq mm3, [eax+24]
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movq mm4, [eax+32]
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movq mm5, [eax+40]
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movq mm6, [eax+48]
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movq mm7, [eax+56]
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sub ecx, 64
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add eax, 64
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cmp ecx, 64
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jl End8
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Cmp8:
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pxor mm0, [eax]
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pxor mm1, [eax+8]
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pxor mm2, [eax+16]
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pxor mm3, [eax+24]
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pxor mm4, [eax+32]
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pxor mm5, [eax+40]
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pxor mm6, [eax+48]
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pxor mm7, [eax+56]
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sub ecx, 64
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add eax, 64
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cmp ecx, 64
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jge Cmp8
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End8:
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pxor mm0, mm4
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pxor mm1, mm5
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pxor mm2, mm6
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pxor mm3, mm7
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cmp ecx, 32
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jl End4
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pxor mm0, [eax]
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pxor mm1, [eax+8]
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pxor mm2, [eax+16]
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pxor mm3, [eax+24]
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sub ecx, 32
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add eax, 32
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jmp End4
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Setup4:
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cmp ecx, 32
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jl Setup2
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movq mm0, [eax]
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movq mm1, [eax+8]
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movq mm2, [eax+16]
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movq mm3, [eax+24]
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sub ecx, 32
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add eax, 32
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End4:
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pxor mm0, mm2
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pxor mm1, mm3
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cmp ecx, 16
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jl End2
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pxor mm0, [eax]
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pxor mm1, [eax+8]
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sub ecx, 16
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add eax, 16
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jmp End2
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Setup2:
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cmp ecx, 16
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jl Setup1
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movq mm0, [eax]
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movq mm1, [eax+8]
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sub ecx, 16
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add eax, 16
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End2:
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pxor mm0, mm1
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cmp ecx, 8
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jl End1
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pxor mm0, [eax]
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End1:
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movq [edx], mm0
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jmp End
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Setup1:
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movq mm0, [eax]
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movq [edx], mm0
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End:
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emms
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}
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}
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#endif
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@ -1,250 +0,0 @@
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/* PCSX2 - PS2 Emulator for PCs
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* Copyright (C) 2002-2010 PCSX2 Dev Team
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*
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* PCSX2 is free software: you can redistribute it and/or modify it under the terms
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* of the GNU Lesser General Public License as published by the Free Software Found-
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* ation, either version 3 of the License, or (at your option) any later version.
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*
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* PCSX2 is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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* PURPOSE. See the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along with PCSX2.
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* If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "PrecompiledHeader.h"
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#include "x86emitter/x86emitter.h"
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#include <xmmintrin.h>
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using namespace x86Emitter;
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// Max Number of qwc supported
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#define _maxSize 0x400
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typedef void (__fastcall *_memCpyCall)(void*, void*);
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__aligned16 _memCpyCall _memcpy_vibes[_maxSize+1];
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#if 1
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// this version uses SSE intrinsics to perform an inline copy. MSVC disasm shows pretty
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// decent code generation on whole, but it hasn't been benchmarked at all yet --air
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__fi void memcpy_vibes(void * dest, const void * src, int size) {
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float (*destxmm)[4] = (float(*)[4])dest, (*srcxmm)[4] = (float(*)[4])src;
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size_t count = size & ~15, extra = size & 15;
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destxmm -= 8 - extra, srcxmm -= 8 - extra;
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switch (extra) {
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do {
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destxmm += 16, srcxmm += 16, count -= 16;
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_mm_store_ps(&destxmm[-8][0], _mm_load_ps(&srcxmm[-8][0]));
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case 15:
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_mm_store_ps(&destxmm[-7][0], _mm_load_ps(&srcxmm[-7][0]));
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case 14:
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_mm_store_ps(&destxmm[-6][0], _mm_load_ps(&srcxmm[-6][0]));
|
||||
case 13:
|
||||
_mm_store_ps(&destxmm[-5][0], _mm_load_ps(&srcxmm[-5][0]));
|
||||
case 12:
|
||||
_mm_store_ps(&destxmm[-4][0], _mm_load_ps(&srcxmm[-4][0]));
|
||||
case 11:
|
||||
_mm_store_ps(&destxmm[-3][0], _mm_load_ps(&srcxmm[-3][0]));
|
||||
case 10:
|
||||
_mm_store_ps(&destxmm[-2][0], _mm_load_ps(&srcxmm[-2][0]));
|
||||
case 9:
|
||||
_mm_store_ps(&destxmm[-1][0], _mm_load_ps(&srcxmm[-1][0]));
|
||||
case 8:
|
||||
_mm_store_ps(&destxmm[ 0][0], _mm_load_ps(&srcxmm[ 0][0]));
|
||||
case 7:
|
||||
_mm_store_ps(&destxmm[ 1][0], _mm_load_ps(&srcxmm[ 1][0]));
|
||||
case 6:
|
||||
_mm_store_ps(&destxmm[ 2][0], _mm_load_ps(&srcxmm[ 2][0]));
|
||||
case 5:
|
||||
_mm_store_ps(&destxmm[ 3][0], _mm_load_ps(&srcxmm[ 3][0]));
|
||||
case 4:
|
||||
_mm_store_ps(&destxmm[ 4][0], _mm_load_ps(&srcxmm[ 4][0]));
|
||||
case 3:
|
||||
_mm_store_ps(&destxmm[ 5][0], _mm_load_ps(&srcxmm[ 5][0]));
|
||||
case 2:
|
||||
_mm_store_ps(&destxmm[ 6][0], _mm_load_ps(&srcxmm[ 6][0]));
|
||||
case 1:
|
||||
_mm_store_ps(&destxmm[ 7][0], _mm_load_ps(&srcxmm[ 7][0]));
|
||||
case 0: NULL;
|
||||
} while (count);
|
||||
}
|
||||
}
|
||||
|
||||
#else
|
||||
#if 1
|
||||
// This version creates one function with a lot of movaps
|
||||
// It jumps to the correct movaps entry-point while adding
|
||||
// the proper offset for adjustment...
|
||||
|
||||
static __pagealigned u8 _memCpyExec[__pagesize*16];
|
||||
|
||||
void gen_memcpy_vibes() {
|
||||
HostSys::MemProtectStatic(_memCpyExec, Protect_ReadWrite, false);
|
||||
memset (_memCpyExec, 0xcc, sizeof(_memCpyExec));
|
||||
xSetPtr(_memCpyExec);
|
||||
|
||||
int off =-(((_maxSize & 0xf) - 7) << 4);
|
||||
for (int i = _maxSize, x = 0; i > 0; i--, x=(x+1)&7, off+=16) {
|
||||
|
||||
_memcpy_vibes[i] = (_memCpyCall)xGetPtr();
|
||||
|
||||
if (off >= 128) {
|
||||
off = -128;
|
||||
xADD(edx, 256);
|
||||
xADD(ecx, 256);
|
||||
}
|
||||
const xRegisterSSE xmm_t(x);
|
||||
xMOVAPS (xmm_t, ptr32[edx+off]);
|
||||
xMOVNTPS(ptr32[ecx+off], xmm_t);
|
||||
}
|
||||
|
||||
_memcpy_vibes[0] = (_memCpyCall)xGetPtr();
|
||||
|
||||
xRET();
|
||||
pxAssert(((uptr)xGetPtr() - (uptr)_memCpyExec) < sizeof(_memCpyExec));
|
||||
|
||||
HostSys::MemProtectStatic(_memCpyExec, Protect_ReadOnly, true);
|
||||
}
|
||||
|
||||
__fi void memcpy_vibes(void * dest, const void * src, int size) {
|
||||
int offset = ((size & 0xf) - 7) << 4;
|
||||
_memcpy_vibes[size]((void*)((uptr)dest + offset), (void*)((uptr)src + offset));
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
// This version creates '_maxSize' number of different functions,
|
||||
// and calls the appropriate one...
|
||||
|
||||
static __pagealigned u8 _memCpyExec[__pagesize*_maxSize*2];
|
||||
|
||||
void gen_memcpy_vibes() {
|
||||
HostSys::MemProtectStatic(_memCpyExec, Protect_ReadWrite, false);
|
||||
memset (_memCpyExec, 0xcc, sizeof(_memCpyExec));
|
||||
xSetPtr(_memCpyExec);
|
||||
|
||||
for (int i = 0; i < _maxSize+1; i++)
|
||||
{
|
||||
int off = 0;
|
||||
_memcpy_vibes[i] = (_memCpyCall)xGetAlignedCallTarget();
|
||||
|
||||
for (int j = 0, x = 0; j < i; j++, x=(x+1)&7, off+=16) {
|
||||
if (off >= 128) {
|
||||
off = -128;
|
||||
xADD(edx, 256);
|
||||
xADD(ecx, 256);
|
||||
}
|
||||
const xRegisterSSE xmm_t(x);
|
||||
xMOVAPS(xmm_t, ptr32[edx+off]);
|
||||
xMOVAPS(ptr32[ecx+off], xmm_t);
|
||||
}
|
||||
|
||||
xRET();
|
||||
pxAssert(((uptr)xGetPtr() - (uptr)_memCpyExec) < sizeof(_memCpyExec));
|
||||
}
|
||||
|
||||
HostSys::MemProtectStatic(_memCpyExec, Protect_ReadOnly, true);
|
||||
}
|
||||
|
||||
__fi void memcpy_vibes(void * dest, const void * src, int size) {
|
||||
_memcpy_vibes[size](dest, src);
|
||||
}
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
||||
// Since MemcpyVibes is already in the project, I'll just tuck the Linux version of memcpy_amd_qwc here for the moment,
|
||||
// to get around compilation issues with having it in the headers.
|
||||
#ifdef __linux__
|
||||
|
||||
// This can be moved later, but Linux doesn't even compile memcpyFast.cpp, so I figured I'd stick it here for now.
|
||||
// Quadword Copy! Count is in QWCs (128 bits). Neither source nor dest need to be aligned.
|
||||
__fi void memcpy_amd_qwc(void *dest, const void *src, size_t qwc)
|
||||
{
|
||||
// Optimization Analysis: This code is *nearly* optimal. Do not think that using XMM
|
||||
// registers will improve copy performance, because they won't. Use of XMMs is only
|
||||
// warranted in situations where both source and dest are guaranteed aligned to 16 bytes,
|
||||
// and even then the benefits are typically minimal (sometimes slower depending on the
|
||||
// amount of data being copied).
|
||||
//
|
||||
// Thus: MMX are alignment safe, fast, and widely available. Lets just stick with them.
|
||||
// --air
|
||||
|
||||
// Linux Conversion note:
|
||||
// This code would benefit nicely from having inline-able GAS syntax, since it should
|
||||
// allow GCC to optimize the first 3 instructions out of existence in many scenarios.
|
||||
// And its called enough times to probably merit the extra effort to ensure proper
|
||||
// optimization. --air
|
||||
|
||||
__asm__ __volatile__
|
||||
(
|
||||
".intel_syntax noprefix\n"
|
||||
"sub %[qwc], 1\n" // dec the counter to ease the count of 16bytes block later (optimization)
|
||||
// Note after this line, real value of the counter is %[qwc] + 1
|
||||
"jle memcpy_qwc_1_%=\n" // only one 16 byte block to copy? Or nothing.
|
||||
|
||||
"cmp %[qwc], 127\n" // "IN_CACHE_COPY/16"
|
||||
"jb memcpy_qwc_loop1_%=\n" // small copies should be cached (definite speedup --air)
|
||||
|
||||
"memcpy_qwc_loop2_%=:\n" // 32-byte blocks, uncached copy
|
||||
"prefetchnta [%[src] + 568]\n" // start reading ahead (tested: it helps! --air)
|
||||
|
||||
"movq mm0,[%[src]+0]\n" // read 64 bits
|
||||
"movq mm1,[%[src]+8]\n"
|
||||
"movq mm2,[%[src]+16]\n"
|
||||
"movntq [%[dest]+0], mm0\n" // write 64 bits, bypassing the cache
|
||||
"movntq [%[dest]+8], mm1\n"
|
||||
"movq mm3,[%[src]+24]\n"
|
||||
"movntq [%[dest]+16], mm2\n"
|
||||
"movntq [%[dest]+24], mm3\n"
|
||||
|
||||
"add %[src],32\n" // update source pointer
|
||||
"add %[dest],32\n" // update destination pointer
|
||||
"sub %[qwc],2\n"
|
||||
"jg memcpy_qwc_loop2_%=\n" // last 64-byte block?
|
||||
"sfence\n" // flush the write buffer
|
||||
"jmp memcpy_qwc_1_%=\n"
|
||||
|
||||
// 32-byte blocks, cached!
|
||||
// This *is* important. Removing this and using exclusively non-temporal stores
|
||||
// results in noticeable speed loss!
|
||||
|
||||
"memcpy_qwc_loop1_%=:\n"
|
||||
"prefetchnta [%[src] + 568]\n" // start reading ahead (tested: it helps! --air)
|
||||
|
||||
"movq mm0,[%[src]+0]\n" // read 64 bits
|
||||
"movq mm1,[%[src]+8]\n"
|
||||
"movq mm2,[%[src]+16]\n"
|
||||
"movq [%[dest]+0], mm0\n" // write 64 bits, bypassing the cache
|
||||
"movq [%[dest]+8], mm1\n"
|
||||
"movq mm3,[%[src]+24]\n"
|
||||
"movq [%[dest]+16], mm2\n"
|
||||
"movq [%[dest]+24], mm3\n"
|
||||
|
||||
"add %[src],32\n" // update source pointer
|
||||
"add %[dest],32\n" // update destination pointer
|
||||
"sub %[qwc],2\n"
|
||||
"jg memcpy_qwc_loop2_%=\n" // last 64-byte block?
|
||||
|
||||
"memcpy_qwc_1_%=:\n"
|
||||
"cmp %[qwc],0\n"
|
||||
"jne memcpy_qwc_final_%=\n"
|
||||
"movq mm0,[%[src]]\n"
|
||||
"movq mm1,[%[src]+8]\n"
|
||||
"movq [%[dest]], mm0\n"
|
||||
"movq [%[dest]+8], mm1\n"
|
||||
|
||||
"memcpy_qwc_final_%=:\n"
|
||||
"emms\n" // clean up the MMX state
|
||||
".att_syntax\n"
|
||||
: "=&r"(dest), "=&r"(src), "=&r"(qwc)
|
||||
: [dest]"0"(dest), [src]"1"(src), [qwc]"2"(qwc)
|
||||
: "memory", "mm0", "mm1", "mm2", "mm3"
|
||||
);
|
||||
}
|
||||
#endif
|
||||
|
||||
Loading…
Reference in New Issue