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pcsx2
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Hack Hw.h in half and do a bit more header cleanup. Remove a header that's unused. 

git-svn-id: http://pcsx2.googlecode.com/svn/trunk@2203 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
arcum42 2009-11-16 13:49:56 +00:00
parent 40ed711445
commit 68c0e16ac0
16 changed files with 385 additions and 524 deletions
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1
pcsx2/Common.h
View File

@ -20,6 +20,7 @@
#include "System.h"
#include "Memory.h"
#include "Hw.h"
#include "Dmac.h"
#include "R5900.h"
#include "SaveState.h"

341
pcsx2/Dmac.h Normal file
View File

@ -0,0 +1,341 @@
/* PCSX2 - PS2 Emulator for PCs
* Copyright (C) 2002-2009 PCSX2 Dev Team
*
* PCSX2 is free software: you can redistribute it and/or modify it under the terms
* of the GNU Lesser General Public License as published by the Free Software Found-
* ation, either version 3 of the License, or (at your option) any later version.
*
* PCSX2 is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along with PCSX2.
* If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef __DMAC_H__
#define __DMAC_H__
extern u8 *psH; // hw mem
//
// --- DMA ---
//
union tDMA_CHCR {
struct {
u32 DIR : 1;
u32 reserved1 : 1;
u32 MOD : 2;
u32 ASP : 2;
u32 TTE : 1;
u32 TIE : 1;
u32 STR : 1;
u32 reserved2 : 7;
u32 TAG : 16;
};
u32 _u32;
};
union tDMA_SADR {
struct {
u32 ADDR : 14;
u32 reserved2 : 18;
};
u32 _u32;
};
struct DMACh {
tDMA_CHCR chcr;
u32 null0[3];
u32 madr;
u32 null1[3];
u16 qwc; u16 pad;
u32 null2[3];
u32 tadr;
u32 null3[3];
u32 asr0;
u32 null4[3];
u32 asr1;
u32 null5[11];
u32 sadr;
};
enum INTCIrqs
{
INTC_GS = 0,
INTC_SBUS,
INTC_VBLANK_S,
INTC_VBLANK_E,
INTC_VIF0,
INTC_VIF1,
INTC_VU0,
INTC_VU1,
INTC_IPU,
INTC_TIM0,
INTC_TIM1,
INTC_TIM2,
INTC_TIM3,
INTC_SFIFO,
INTVU0_WD
};
enum dmac_conditions
{
DMAC_STAT_SIS = (1<<13), // stall condition
DMAC_STAT_MEIS = (1<<14), // mfifo empty
DMAC_STAT_BEIS = (1<<15), // bus error
DMAC_STAT_SIM = (1<<29), // stall mask
DMAC_STAT_MEIM = (1<<30) // mfifo mask
};
enum DMACIrqs
{
DMAC_VIF0 = 0,
DMAC_VIF1,
DMAC_GIF,
DMAC_FROM_IPU,
DMAC_TO_IPU,
DMAC_SIF0,
DMAC_SIF1,
DMAC_SIF2,
DMAC_FROM_SPR,
DMAC_TO_SPR,
// We're setting error conditions through hwDmacIrq, so these correspond to the conditions above.
DMAC_STALL_SIS = 13, // SIS
DMAC_MFIFO_EMPTY = 14, // MEIS
DMAC_BUS_ERROR = 15 // BEIS
};
//DMA interrupts & masks
enum DMAInter
{
BEISintr = 0x00008000,
VIF0intr = 0x00010001,
VIF1intr = 0x00020002,
GIFintr = 0x00040004,
IPU0intr = 0x00080008,
IPU1intr = 0x00100010,
SIF0intr = 0x00200020,
SIF1intr =0x00400040,
SIF2intr = 0x00800080,
SPR0intr = 0x01000100,
SPR1intr = 0x02000200,
SISintr = 0x20002000,
MEISintr = 0x40004000
};
union tDMAC_CTRL {
struct {
u32 DMAE : 1;
u32 RELE : 1;
u32 MFD : 2;
u32 STS : 2;
u32 STD : 2;
u32 RCYC : 3;
u32 reserved1 : 21;
};
u32 _u32;
};
union tDMAC_STAT {
struct {
u32 CIS : 10;
u32 reserved1 : 3;
u32 SIS : 1;
u32 MEIS : 1;
u32 BEIS : 1;
u32 CIM : 10;
u32 reserved2 : 3;
u32 SIM : 1;
u32 MEIM : 1;
u32 reserved3 : 1;
};
u32 _u32;
bool test(u32 flags) { return !!(_u32 & flags); }
void set(u32 flags) { _u32 |= flags; }
void clear(u32 flags) { _u32 &= ~flags; }
};
union tDMAC_PCR {
struct {
u32 CPC : 10;
u32 reserved1 : 6;
u32 CDE : 10;
u32 reserved2 : 5;
u32 PCE : 1;
};
u32 _u32;
};
union tDMAC_SQWC {
struct {
u32 SQWC : 8;
u32 reserved1 : 8;
u32 TQWC : 8;
u32 reserved2 : 8;
};
u32 _u32;
};
union tDMAC_RBSR {
struct {
u32 RMSK : 31;
u32 reserved1 : 1;
};
u32 _u32;
};
union tDMAC_RBOR {
struct {
u32 ADDR : 31;
u32 reserved1 : 1;
};
u32 _u32;
};
union tDMAC_STADR {
struct {
u32 ADDR : 31;
u32 reserved1 : 1;
};
u32 _u32;
};
struct DMACregisters
{
tDMAC_CTRL ctrl;
u32 padding[3];
tDMAC_STAT stat;
u32 padding1[3];
tDMAC_PCR pcr;
u32 padding2[3];
tDMAC_SQWC sqwc;
u32 padding3[3];
tDMAC_RBSR rbsr;
u32 padding4[3];
tDMAC_RBOR rbor;
u32 padding5[3];
tDMAC_STADR stadr;
};
// Currently guesswork.
union tINTC_STAT {
struct {
u32 interrupts : 10;
u32 placeholder : 22;
};
u32 _u32;
bool test(u32 flags) { return !!(_u32 & flags); }
void set(u32 flags) { _u32 |= flags; }
void clear(u32 flags) { _u32 &= ~flags; }
};
union tINTC_MASK {
struct {
u32 int_mask : 10;
u32 placeholder:22;
};
u32 _u32;
};
struct INTCregisters
{
tINTC_STAT stat;
u32 padding[3];
tINTC_MASK mask;
};
#define dmacRegs ((DMACregisters*)(PS2MEM_HW+0xE000))
#define intcRegs ((INTCregisters*)(PS2MEM_HW+0xF000))
// Note: Dma addresses are guaranteed to be aligned to 16 bytes (128 bits)
static __forceinline void *dmaGetAddr(u32 addr) {
u8 *ptr;
// if (addr & 0xf) { DMA_LOG("*PCSX2*: DMA address not 128bit aligned: %8.8x", addr); }
// Need to check the physical address as well as just the "SPR" flag, as VTLB doesnt seem to handle it
if ((addr & 0x80000000) || (addr & 0x70000000) == 0x70000000) return (void*)&psS[addr & 0x3ff0];
ptr = (u8*)vtlb_GetPhyPtr(addr&0x1FFFFFF0);
if (ptr == NULL) {
Console.Error( "*PCSX2*: DMA error: %8.8x", addr);
return NULL;
}
return ptr;
}
static __forceinline u32 *_dmaGetAddr(DMACh *dma, u32 addr, u32 num)
{
u32 *ptr = (u32*)dmaGetAddr(addr);
if (ptr == NULL)
{
// DMA Error
dmacRegs->stat.BEIS = 1; // BUS Error
// DMA End
dmacRegs->stat.set(1 << num);
dma->chcr.STR = 0;
}
return ptr;
}
void hwIntcIrq(int n);
void hwDmacIrq(int n);
bool hwDmacSrcChainWithStack(DMACh *dma, int id);
bool hwDmacSrcChain(DMACh *dma, int id);
extern void intcInterrupt();
extern void dmacInterrupt();
#endif
// Everything after this comment is obsolete, and can be ignored.
#ifdef PCSX2_VIRTUAL_MEM
#define dmaGetAddrBase(addr) (((addr) & 0x80000000) ? (void*)&PS2MEM_SCRATCH[(addr) & 0x3ff0] : (void*)(PS2MEM_BASE+TRANSFORM_ADDR(addr)))
#ifdef _WIN32
extern PSMEMORYMAP* memLUT;
#endif
// VM-version of dmaGetAddr -- Left in for references purposes for now (air)
static __forceinline u8* dmaGetAddr(u32 mem)
{
u8* p, *pbase;
mem &= ~0xf;
if( (mem&0xffff0000) == 0x50000000 ) {// reserved scratch pad mem
Console.WriteLn("dmaGetAddr: reserved scratch pad mem");
return NULL;//(u8*)&PS2MEM_SCRATCH[(mem) & 0x3ff0];
}
p = (u8*)dmaGetAddrBase(mem);
#ifdef _WIN32
// do manual LUT since IPU/SPR seems to use addrs 0x3000xxxx quite often
// linux doesn't suffer from this because it has better vm support
if( memLUT[ (p-PS2MEM_BASE)>>12 ].aPFNs == NULL ) {
Console.WriteLn("dmaGetAddr: memLUT PFN warning");
return NULL;//p;
}
pbase = (u8*)memLUT[ (p-PS2MEM_BASE)>>12 ].aVFNs[0];
if( pbase != NULL ) p = pbase + ((u32)p&0xfff);
#endif
return p;
}
#endif

5
pcsx2/Hardware.h
View File

@ -13,6 +13,9 @@
* If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef __HARDWARE_H__
#define __HARDWARE_H__
// The full suite of hardware APIs:
#include "Counters.h"
#include "GS.h"
@ -23,3 +26,5 @@
#include "Sif.h"
#include "Vif.h"
#include "VifDma.h"
#endif

326
pcsx2/Hw.h
View File

@ -13,11 +13,10 @@
* If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef __HW_H__
#define __HW_H__
extern u8 *psH; // hw mem
extern void CPU_INT( u32 n, s32 ecycle );
//////////////////////////////////////////////////////////////////////////
@ -39,51 +38,6 @@ void __fastcall WriteFIFO_page_5(u32 mem, const mem128_t *value);
void __fastcall WriteFIFO_page_6(u32 mem, const mem128_t *value);
void __fastcall WriteFIFO_page_7(u32 mem, const mem128_t *value);
//
// --- DMA ---
//
union tDMA_CHCR {
struct {
u32 DIR : 1;
u32 reserved1 : 1;
u32 MOD : 2;
u32 ASP : 2;
u32 TTE : 1;
u32 TIE : 1;
u32 STR : 1;
u32 reserved2 : 7;
u32 TAG : 16;
};
u32 _u32;
};
union tDMA_SADR {
struct {
u32 ADDR : 14;
u32 reserved2 : 18;
};
u32 _u32;
};
struct DMACh {
tDMA_CHCR chcr;
u32 null0[3];
u32 madr;
u32 null1[3];
u16 qwc; u16 pad;
u32 null2[3];
u32 tadr;
u32 null3[3];
u32 asr0;
u32 null4[3];
u32 asr1;
u32 null5[11];
u32 sadr;
};
// HW defines
enum EERegisterAddresses
{
@ -292,276 +246,11 @@ enum GSRegisterAddresses
GS_SIGLBLID = 0x12001080
};
enum INTCIrqs
{
INTC_GS = 0,
INTC_SBUS,
INTC_VBLANK_S,
INTC_VBLANK_E,
INTC_VIF0,
INTC_VIF1,
INTC_VU0,
INTC_VU1,
INTC_IPU,
INTC_TIM0,
INTC_TIM1,
INTC_TIM2,
INTC_TIM3,
INTC_SFIFO,
INTVU0_WD
};
enum dmac_conditions
{
DMAC_STAT_SIS = (1<<13), // stall condition
DMAC_STAT_MEIS = (1<<14), // mfifo empty
DMAC_STAT_BEIS = (1<<15), // bus error
DMAC_STAT_SIM = (1<<29), // stall mask
DMAC_STAT_MEIM = (1<<30) // mfifo mask
};
enum DMACIrqs
{
DMAC_VIF0 = 0,
DMAC_VIF1,
DMAC_GIF,
DMAC_FROM_IPU,
DMAC_TO_IPU,
DMAC_SIF0,
DMAC_SIF1,
DMAC_SIF2,
DMAC_FROM_SPR,
DMAC_TO_SPR,
// We're setting error conditions through hwDmacIrq, so these correspond to the conditions above.
DMAC_STALL_SIS = 13, // SIS
DMAC_MFIFO_EMPTY = 14, // MEIS
DMAC_BUS_ERROR = 15 // BEIS
};
//DMA interrupts & masks
enum DMAInter
{
BEISintr = 0x00008000,
VIF0intr = 0x00010001,
VIF1intr = 0x00020002,
GIFintr = 0x00040004,
IPU0intr = 0x00080008,
IPU1intr = 0x00100010,
SIF0intr = 0x00200020,
SIF1intr =0x00400040,
SIF2intr = 0x00800080,
SPR0intr = 0x01000100,
SPR1intr = 0x02000200,
SISintr = 0x20002000,
MEISintr = 0x40004000
};
union tDMAC_CTRL {
struct {
u32 DMAE : 1;
u32 RELE : 1;
u32 MFD : 2;
u32 STS : 2;
u32 STD : 2;
u32 RCYC : 3;
u32 reserved1 : 21;
};
u32 _u32;
};
union tDMAC_STAT {
struct {
u32 CIS : 10;
u32 reserved1 : 3;
u32 SIS : 1;
u32 MEIS : 1;
u32 BEIS : 1;
u32 CIM : 10;
u32 reserved2 : 3;
u32 SIM : 1;
u32 MEIM : 1;
u32 reserved3 : 1;
};
u32 _u32;
bool test(u32 flags) { return !!(_u32 & flags); }
void set(u32 flags) { _u32 |= flags; }
void clear(u32 flags) { _u32 &= ~flags; }
};
union tDMAC_PCR {
struct {
u32 CPC : 10;
u32 reserved1 : 6;
u32 CDE : 10;
u32 reserved2 : 5;
u32 PCE : 1;
};
u32 _u32;
};
union tDMAC_SQWC {
struct {
u32 SQWC : 8;
u32 reserved1 : 8;
u32 TQWC : 8;
u32 reserved2 : 8;
};
u32 _u32;
};
union tDMAC_RBSR {
struct {
u32 RMSK : 31;
u32 reserved1 : 1;
};
u32 _u32;
};
union tDMAC_RBOR {
struct {
u32 ADDR : 31;
u32 reserved1 : 1;
};
u32 _u32;
};
union tDMAC_STADR {
struct {
u32 ADDR : 31;
u32 reserved1 : 1;
};
u32 _u32;
};
struct DMACregisters
{
tDMAC_CTRL ctrl;
u32 padding[3];
tDMAC_STAT stat;
u32 padding1[3];
tDMAC_PCR pcr;
u32 padding2[3];
tDMAC_SQWC sqwc;
u32 padding3[3];
tDMAC_RBSR rbsr;
u32 padding4[3];
tDMAC_RBOR rbor;
u32 padding5[3];
tDMAC_STADR stadr;
};
// Currently guesswork.
union tINTC_STAT {
struct {
u32 interrupts : 10;
u32 placeholder : 22;
};
u32 _u32;
bool test(u32 flags) { return !!(_u32 & flags); }
void set(u32 flags) { _u32 |= flags; }
void clear(u32 flags) { _u32 &= ~flags; }
};
union tINTC_MASK {
struct {
u32 int_mask : 10;
u32 placeholder:22;
};
u32 _u32;
};
struct INTCregisters
{
tINTC_STAT stat;
u32 padding[3];
tINTC_MASK mask;
};
#define dmacRegs ((DMACregisters*)(PS2MEM_HW+0xE000))
#define intcRegs ((INTCregisters*)(PS2MEM_HW+0xF000))
#ifdef PCSX2_VIRTUAL_MEM
#define dmaGetAddrBase(addr) (((addr) & 0x80000000) ? (void*)&PS2MEM_SCRATCH[(addr) & 0x3ff0] : (void*)(PS2MEM_BASE+TRANSFORM_ADDR(addr)))
#ifdef _WIN32
extern PSMEMORYMAP* memLUT;
#endif
// VM-version of dmaGetAddr -- Left in for references purposes for now (air)
static __forceinline u8* dmaGetAddr(u32 mem)
{
u8* p, *pbase;
mem &= ~0xf;
if( (mem&0xffff0000) == 0x50000000 ) {// reserved scratch pad mem
Console.WriteLn("dmaGetAddr: reserved scratch pad mem");
return NULL;//(u8*)&PS2MEM_SCRATCH[(mem) & 0x3ff0];
}
p = (u8*)dmaGetAddrBase(mem);
#ifdef _WIN32
// do manual LUT since IPU/SPR seems to use addrs 0x3000xxxx quite often
// linux doesn't suffer from this because it has better vm support
if( memLUT[ (p-PS2MEM_BASE)>>12 ].aPFNs == NULL ) {
Console.WriteLn("dmaGetAddr: memLUT PFN warning");
return NULL;//p;
}
pbase = (u8*)memLUT[ (p-PS2MEM_BASE)>>12 ].aVFNs[0];
if( pbase != NULL ) p = pbase + ((u32)p&0xfff);
#endif
return p;
}
#else
// Note: Dma addresses are guaranteed to be aligned to 16 bytes (128 bits)
static __forceinline void *dmaGetAddr(u32 addr) {
u8 *ptr;
// if (addr & 0xf) { DMA_LOG("*PCSX2*: DMA address not 128bit aligned: %8.8x", addr); }
// Need to check the physical address as well as just the "SPR" flag, as VTLB doesnt seem to handle it
if ((addr & 0x80000000) || (addr & 0x70000000) == 0x70000000) return (void*)&psS[addr & 0x3ff0];
ptr = (u8*)vtlb_GetPhyPtr(addr&0x1FFFFFF0);
if (ptr == NULL) {
Console.Error( "*PCSX2*: DMA error: %8.8x", addr);
return NULL;
}
return ptr;
}
#endif
static __forceinline u32 *_dmaGetAddr(DMACh *dma, u32 addr, u32 num)
{
u32 *ptr = (u32*)dmaGetAddr(addr);
if (ptr == NULL)
{
// DMA Error
dmacRegs->stat.BEIS = 1; // BUS Error
// DMA End
dmacRegs->stat.set(1 << num);
dma->chcr.STR = 0;
}
return ptr;
}
void hwReset();
// hw read functions
extern mem8_t hwRead8 (u32 mem);
extern mem16_t hwRead16(u32 mem);
extern mem8_t hwRead8 (u32 mem);
extern mem16_t hwRead16(u32 mem);
extern mem32_t __fastcall hwRead32_page_00(u32 mem);
extern mem32_t __fastcall hwRead32_page_01(u32 mem);
@ -603,17 +292,8 @@ extern void __fastcall hwWrite64_generic( u32 mem, const mem64_t* srcval );
extern void __fastcall hwWrite128_generic(u32 mem, const mem128_t *srcval);
void hwIntcIrq(int n);
void hwDmacIrq(int n);
bool hwMFIFOWrite(u32 addr, u8 *data, u32 size);
bool hwDmacSrcChainWithStack(DMACh *dma, int id);
bool hwDmacSrcChain(DMACh *dma, int id);
extern void intcInterrupt();
extern void dmacInterrupt();
extern const int rdram_devices;
extern int rdram_sdevid;

91
pcsx2/IopBios2.h
View File

@ -1,91 +0,0 @@
/* PCSX2 - PS2 Emulator for PCs
* Copyright (C) 2002-2009 PCSX2 Dev Team
*
* PCSX2 is free software: you can redistribute it and/or modify it under the terms
* of the GNU Lesser General Public License as published by the Free Software Found-
* ation, either version 3 of the License, or (at your option) any later version.
*
* PCSX2 is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along with PCSX2.
* If not, see <http://www.gnu.org/licenses/>.
*/
/***** sysmem imageInfo
00000800: 00 16 00 00 70 14 00 00 ¦ 01 01 00 00 01 00 00 00
0000 next: .word ? //00001600
0004 name: .word ? //00001470
0008 version: .half ? //0101
000A flags: .half ? //----
000C index: .half ? //0001
000E field_E: .half ? //----
00000810: 90 08 00 00 A0 94 00 00 ¦ 30 08 00 00 40 0C 00 00
0010 entry: .word ? //00000890
0014 gp_value: .word ? //000094A0
0018 p1_vaddr: .word ? //00000830
001C text_size: .word ? //00000C40
00000820: 40 00 00 00 10 00 00 00 ¦ 00 00 00 00 00 00 00 00
0020 data_size: .word ? //00000040
0024 bss_size: .word ? //00000010
0028 field_28: .word ? //--------
002C field_2C: .word ? //--------
*****/
#ifndef __PSX_BIOS_H__
#define __PSX_BIOS_H__
struct irxImageInfo {
u32 next, //+00
name; //+04
u16 version, //+08
flags, //+0A
index, //+0C
_unkE; //+0E
u32 entry, //+10
_gp, //+14
vaddr, //+18
text_size, //+1C
data_size, //+20
bss_size, //+24
_pad28, //+28
_pad2C; //+2C
}; //=30
struct _sifServer {
int active;
u32 server;
u32 fhandler;
};
#define SIF_SERVERS 32
_sifServer sifServer[SIF_SERVERS];
// max modules/funcs
#define IRX_MODULES 64
#define IRX_FUNCS 256
struct irxFunc {
u32 num;
u32 entry;
};
struct irxModule {
int active;
u32 name[2];
irxFunc funcs[IRX_FUNCS];
};
irxModule irxMod[IRX_MODULES];
void iopModulesInit();
int iopSetImportFunc(u32 *ptr);
int iopSetExportFunc(u32 *ptr);
void sifServerCall(u32 server, u32 num, char *bin, int insize, char *bout, int outsize);
void sifAddServer(u32 server, u32 fhandler);
#endif

3
pcsx2/IopCounters.h
View File

@ -34,7 +34,6 @@ extern psxCounter psxCounters[NUM_COUNTERS];
extern void psxRcntInit();
extern void psxRcntUpdate();
extern void cntspu2async();
extern void psxRcntWcount16(int index, u16 value);
extern void psxRcntWcount32(int index, u32 value);
extern void psxRcntWmode16(int index, u32 value);
@ -49,7 +48,5 @@ extern void psxVBlankStart();
extern void psxVBlankEnd();
extern void psxCheckStartGate16(int i);
extern void psxCheckEndGate16(int i);
//static void psxCheckStartGate32(int i);
//static void psxCheckEndGate32(int i);
#endif /* __PSXCOUNTERS_H__ */

36
pcsx2/IopDma.h
View File

@ -48,8 +48,8 @@ struct DmaStatusInfo
#define DMA_CHANNEL_MAX 16 /* ? */
// WARNING: CALLER ****[MUST]**** CALL IopDmaUpdate RIGHT AFTER THIS!
void IopDmaStart(int channel, u32 chcr, u32 madr, u32 bcr);
void IopDmaUpdate(u32 elapsed);
extern void IopDmaStart(int channel, u32 chcr, u32 madr, u32 bcr);
extern void IopDmaUpdate(u32 elapsed);
// external dma handlers
extern s32 cdvdDmaRead(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed);
@ -58,23 +58,23 @@ extern void cdvdDmaInterrupt(s32 channel);
//#else
#endif
void psxDma2(u32 madr, u32 bcr, u32 chcr);
void psxDma3(u32 madr, u32 bcr, u32 chcr);
void psxDma4(u32 madr, u32 bcr, u32 chcr);
void psxDma6(u32 madr, u32 bcr, u32 chcr);
void psxDma7(u32 madr, u32 bcr, u32 chcr);
void psxDma8(u32 madr, u32 bcr, u32 chcr);
void psxDma9(u32 madr, u32 bcr, u32 chcr);
void psxDma10(u32 madr, u32 bcr, u32 chcr);
extern void psxDma2(u32 madr, u32 bcr, u32 chcr);
extern void psxDma3(u32 madr, u32 bcr, u32 chcr);
extern void psxDma4(u32 madr, u32 bcr, u32 chcr);
extern void psxDma6(u32 madr, u32 bcr, u32 chcr);
extern void psxDma7(u32 madr, u32 bcr, u32 chcr);
extern void psxDma8(u32 madr, u32 bcr, u32 chcr);
extern void psxDma9(u32 madr, u32 bcr, u32 chcr);
extern void psxDma10(u32 madr, u32 bcr, u32 chcr);
int psxDma4Interrupt();
int psxDma7Interrupt();
void dev9Interrupt();
void dev9Irq(int cycles);
void usbInterrupt();
void usbIrq(int cycles);
void fwIrq();
void spu2Irq();
extern int psxDma4Interrupt();
extern int psxDma7Interrupt();
extern void dev9Interrupt();
extern void dev9Irq(int cycles);
extern void usbInterrupt();
extern void usbIrq(int cycles);
extern void fwIrq();
extern void spu2Irq();
extern void iopIntcIrq( uint irqType );
extern void iopTestIntc();

10
pcsx2/IopMem.h
View File

@ -86,14 +86,6 @@ extern void __fastcall iopMemWrite8 (u32 mem, u8 value);
extern void __fastcall iopMemWrite16(u32 mem, u16 value);
extern void __fastcall iopMemWrite32(u32 mem, u32 value);
// x86reg and mmreg are always x86 regs
extern void psxRecMemRead8();
extern void psxRecMemRead16();
extern void psxRecMemRead32();
extern void psxRecMemWrite8();
extern void psxRecMemWrite16();
extern void psxRecMemWrite32();
namespace IopMemory
{
// Sif functions not made yet (will for future Iop improvements):
@ -132,4 +124,4 @@ namespace IopMemory
extern void __fastcall iopHwWrite32_Page1( u32 iopaddr, mem32_t data );
extern void __fastcall iopHwWrite32_Page3( u32 iopaddr, mem32_t data );
extern void __fastcall iopHwWrite32_Page8( u32 iopaddr, mem32_t data );
}
}

2
pcsx2/Linux/pcsx2.cbp
View File

@ -152,6 +152,7 @@
<Unit filename="../DebugTools/DisVU1Micro.cpp" />
<Unit filename="../DebugTools/DisVUmicro.h" />
<Unit filename="../DebugTools/DisVUops.h" />
<Unit filename="../Dmac.h" />
<Unit filename="../Docs/ChangeLog.txt" />
<Unit filename="../Docs/License.txt" />
<Unit filename="../Docs/devblog.txt" />
@ -186,7 +187,6 @@
<Unit filename="../Interpreter.cpp" />
<Unit filename="../IopBios.cpp" />
<Unit filename="../IopBios.h" />
<Unit filename="../IopBios2.h" />
<Unit filename="../IopCommon.h" />
<Unit filename="../IopCounters.cpp" />
<Unit filename="../IopCounters.h" />

58
pcsx2/R3000AInterpreter.cpp
View File

@ -230,18 +230,6 @@ void zeroEx()
psxRegs.GPR.n.a0, psxRegs.GPR.n.a1, psxRegs.GPR.n.a2, psxRegs.GPR.n.a3);
}
// Log=0;
// if (!strcmp(lib, "intrman") && code == 0x11) Log=1;
// if (!strcmp(lib, "sifman") && code == 0x5) Log=1;
// if (!strcmp(lib, "sifcmd") && code == 0x4) Log=1;
// if (!strcmp(lib, "thbase") && code == 0x6) Log=1;
/*
if (!strcmp(lib, "sifcmd") && code == 0xe) {
branchPC = psxRegs.GPR.n.ra;
psxRegs.GPR.n.v0 = 0;
return;
}
*/
if (!strncmp(lib, "ioman", 5) && code == 7) {
if (psxRegs.GPR.n.a0 == 1) {
pc = psxRegs.pc;
@ -281,54 +269,10 @@ void zeroEx()
}
}
/* psxRegs.pc = branchPC;
pc = psxRegs.GPR.n.ra;
while (psxRegs.pc != pc) psxCpu->ExecuteBlock();
PSXBIOS_LOG("%s: %s (%x) END", lib, fname == NULL ? "unknown" : fname, code);*/
#endif
}
/*/==========================================CALL LOG
char* getName(char *file, u32 addr){
FILE *f; u32 a;
static char name[100];
f=fopen(file, "r");
if (!f)
name[0]=0;
else{
while (!feof(f)){
fscanf(f, "%08X %s", &a, name);
if (a==addr)break;
}
fclose(f);
}
return name;
}
void spyFunctions(){
register irxImageInfo *iii;
if (psxRegs.pc >= 0x200000) return;
for (iii=(irxImageInfo*)PSXM(0x800); iii && iii->text_size;
iii=iii->next ? (irxImageInfo*)PSXM(iii->next) : NULL)
if (iii->vaddr<=psxRegs.pc && psxRegs.pc<iii->vaddr+iii->text_size+iii->data_size+iii->bss_size){
if (strcmp("secrman_for_cex", PSXM(iii->name))==0){
char *name=getName("secrman.fun", psxRegs.pc-iii->vaddr);
if (strncmp("__push_params", name, 13)==0){
PAD_LOG(PSXM(psxRegs.GPR.n.a0), psxRegs.GPR.n.a1, psxRegs.GPR.n.a2, psxRegs.GPR.n.a3);
}else{
PAD_LOG("secrman: %s (ra=%06X cycle=%d)", name, psxRegs.GPR.n.ra-iii->vaddr, psxRegs.cycle);}}else
if (strcmp("mcman", PSXM(iii->name))==0){
PAD_LOG("mcman: %s (ra=%06X cycle=%d)", getName("mcman.fun", psxRegs.pc-iii->vaddr), psxRegs.GPR.n.ra-iii->vaddr, psxRegs.cycle);}else
if (strcmp("padman", PSXM(iii->name))==0){
PAD_LOG("padman: %s (ra=%06X cycle=%d)", getName("padman.fun", psxRegs.pc-iii->vaddr), psxRegs.GPR.n.ra-iii->vaddr, psxRegs.cycle);}else
if (strcmp("sio2man", PSXM(iii->name))==0){
PAD_LOG("sio2man: %s (ra=%06X cycle=%d)", getName("sio2man.fun", psxRegs.pc-iii->vaddr), psxRegs.GPR.n.ra-iii->vaddr, psxRegs.cycle);}
break;
}
}
*/
/*********************************************************
* Register branch logic *
* Format: OP rs, offset *
@ -399,7 +343,6 @@ void psxJAL()
{
_SetLink(31);
doBranch(_JumpTarget_);
/*spyFunctions();*/
}
/*********************************************************
@ -427,7 +370,6 @@ static __forceinline void execI()
{
psxRegs.code = iopMemRead32(psxRegs.pc);
//if( (psxRegs.pc >= 0x1200 && psxRegs.pc <= 0x1400) || (psxRegs.pc >= 0x0b40 && psxRegs.pc <= 0x1000))
PSXCPU_LOG("%s", disR3000AF(psxRegs.code, psxRegs.pc));
psxRegs.pc+= 4;

13
pcsx2/SPR.h
View File

@ -13,14 +13,13 @@
* If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef __SPR_H__
#define __SPR_H__
#include "Common.h"
void sprInit();
void dmaSPR0();
void dmaSPR1();
void SPRFROMinterrupt();
void SPRTOinterrupt();
extern void sprInit();
extern void dmaSPR0();
extern void dmaSPR1();
extern void SPRFROMinterrupt();
extern void SPRTOinterrupt();
#endif /* __SPR_H__ */

5
pcsx2/VifDma_internal.h
View File

@ -57,10 +57,7 @@ extern __forceinline void vif1FLUSH();
static __forceinline u32 vif_size(u8 num)
{
if (num == 0)
return 0x1000;
else
return 0x4000;
return (num == 0) ? 0x1000 : 0x4000;
}
#endif

1
pcsx2/gui/Dialogs/ConfirmationDialogs.cpp
View File

@ -18,6 +18,7 @@
#include "App.h"
#include "ModalPopups.h"
#include "Utilities/StringHelpers.h"
using namespace wxHelpers;

2
pcsx2/windows/VCprojects/pcsx2.vcxproj
View File

@ -590,6 +590,7 @@
<ClInclude Include="..\..\DebugTools\DisASM.h" />
<ClInclude Include="..\..\DebugTools\DisVUmicro.h" />
<ClInclude Include="..\..\DebugTools\DisVUops.h" />
<ClInclude Include="..\..\Dmac.h" />
<ClInclude Include="..\..\Dump.h" />
<ClInclude Include="..\..\Elfheader.h" />
<ClInclude Include="..\..\Exceptions.h" />
@ -600,7 +601,6 @@
<ClInclude Include="..\..\Hw.h" />
<ClInclude Include="..\..\Hardware.h" />
<ClInclude Include="..\..\IopBios.h" />
<ClInclude Include="..\..\IopBios2.h" />
<ClInclude Include="..\..\IopCommon.h" />
<ClInclude Include="..\..\IopCounters.h" />
<ClInclude Include="..\..\IopDma.h" />

8
pcsx2/windows/VCprojects/pcsx2_2008.vcproj
View File

@ -549,6 +549,10 @@
<Filter
Name="Hardware"
>
<File
RelativePath="..\..\Dmac.h"
>
</File>
<File
RelativePath="..\..\FiFo.cpp"
>
@ -1074,10 +1078,6 @@
RelativePath="..\..\IopBios.h"
>
</File>
<File
RelativePath="..\..\IopBios2.h"
>
</File>
<File
RelativePath="..\..\IopCounters.cpp"
>

7
pcsx2/x86/iCore.h
View File

@ -126,10 +126,7 @@ int _checkX86reg(int type, int reg, int mode);
void _addNeededX86reg(int type, int reg);
void _clearNeededX86regs();
void _freeX86reg(int x86reg);
void _flushX86regs();
void _freeX86regs();
void _freeX86tempregs();
u8 _hasFreeX86reg();
void _flushCachedRegs();
void _flushConstRegs();
void _flushConstReg(int reg);
@ -177,11 +174,11 @@ void _addNeededFPACCtoXMMreg();
void _addNeededGPRtoXMMreg(int gprreg);
void _clearNeededXMMregs();
void _deleteVFtoXMMreg(int reg, int vu, int flush);
void _deleteACCtoXMMreg(int vu, int flush);
//void _deleteACCtoXMMreg(int vu, int flush);
void _deleteGPRtoXMMreg(int reg, int flush);
void _deleteFPtoXMMreg(int reg, int flush);
void _freeXMMreg(int xmmreg);
void _moveXMMreg(int xmmreg); // instead of freeing, moves it to a diff location
//void _moveXMMreg(int xmmreg); // instead of freeing, moves it to a diff location
void _flushXMMregs();
u8 _hasFreeXMMreg();
void _freeXMMregs();