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SPU2: Remove cycleptr and read the cycle directly 

Seemed like any chance of working without grabbing this straight out of
the iop was given up on anyway.
This commit is contained in:
Ziemas 2021-06-02 15:19:43 +02:00 committed by lightningterror
parent f5346129ae
commit 67cd7713b8
4 changed files with 22 additions and 42 deletions
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19
pcsx2/SPU2/Dma.cpp
View File

@ -154,8 +154,7 @@ void V_Core::StartADMAWrite(u16* pMem, u32 sz)
{ {
int size = sz; int size = sz;
if (cyclePtr != nullptr) TimeUpdate(psxRegs.cycle);
TimeUpdate(*cyclePtr);
if (MsgAutoDMA()) if (MsgAutoDMA())
ConLog("* SPU2: DMA%c AutoDMA Transfer of %d bytes to %x (%02x %x %04x).OutPos %x\n", ConLog("* SPU2: DMA%c AutoDMA Transfer of %d bytes to %x (%02x %x %04x).OutPos %x\n",
@ -167,7 +166,7 @@ void V_Core::StartADMAWrite(u16* pMem, u32 sz)
{ {
ActiveTSA = 0x2000 + (Index << 10); ActiveTSA = 0x2000 + (Index << 10);
DMAICounter = size * 4; DMAICounter = size * 4;
LastClock = *cyclePtr; LastClock = psxRegs.cycle;
} }
else if (size >= 256) else if (size >= 256)
{ {
@ -194,7 +193,7 @@ void V_Core::StartADMAWrite(u16* pMem, u32 sz)
ConLog("ADMA%c Error Size of %x too small\n", GetDmaIndexChar(), size); ConLog("ADMA%c Error Size of %x too small\n", GetDmaIndexChar(), size);
InputDataLeft = 0; InputDataLeft = 0;
DMAICounter = size * 4; DMAICounter = size * 4;
LastClock = *cyclePtr; LastClock = psxRegs.cycle;
} }
} }
@ -214,13 +213,12 @@ void V_Core::PlainDMAWrite(u16* pMem, u32 size)
} }
} }
if (cyclePtr != nullptr) TimeUpdate(psxRegs.cycle);
TimeUpdate(*cyclePtr);
ReadSize = size; ReadSize = size;
IsDMARead = false; IsDMARead = false;
DMAICounter = 0; DMAICounter = 0;
LastClock = *cyclePtr; LastClock = psxRegs.cycle;
Regs.STATX &= ~0x80; Regs.STATX &= ~0x80;
Regs.STATX |= 0x400; Regs.STATX |= 0x400;
TADR = MADR + (size << 1); TADR = MADR + (size << 1);
@ -462,14 +460,13 @@ void V_Core::FinishDMAread()
void V_Core::DoDMAread(u16* pMem, u32 size) void V_Core::DoDMAread(u16* pMem, u32 size)
{ {
if (cyclePtr != nullptr) TimeUpdate(psxRegs.cycle);
TimeUpdate(*cyclePtr);
DMARPtr = pMem; DMARPtr = pMem;
ActiveTSA = TSA & 0xfffff; ActiveTSA = TSA & 0xfffff;
ReadSize = size; ReadSize = size;
IsDMARead = true; IsDMARead = true;
LastClock = *cyclePtr; LastClock = psxRegs.cycle;
DMAICounter = std::min(ReadSize, (u32)0x100) * 4; DMAICounter = std::min(ReadSize, (u32)0x100) * 4;
Regs.STATX &= ~0x80; Regs.STATX &= ~0x80;
Regs.STATX |= 0x400; Regs.STATX |= 0x400;
@ -502,7 +499,7 @@ void V_Core::DoDMAwrite(u16* pMem, u32 size)
Regs.STATX &= ~0x80; Regs.STATX &= ~0x80;
//Regs.ATTR |= 0x30; //Regs.ATTR |= 0x30;
DMAICounter = 1 * 4; DMAICounter = 1 * 4;
LastClock = *cyclePtr; LastClock = psxRegs.cycle;
return; return;
} }

32
pcsx2/SPU2/spu2.cpp
View File

@ -43,7 +43,6 @@ static bool IsInitialized = false;
static u32 pClocks = 0; static u32 pClocks = 0;
u32* cyclePtr = nullptr;
u32 lClocks = 0; u32 lClocks = 0;
//static bool cpu_detected = false; //static bool cpu_detected = false;
@ -77,8 +76,7 @@ void SPU2setLogDir(const char* dir)
void SPU2readDMA4Mem(u16* pMem, u32 size) // size now in 16bit units void SPU2readDMA4Mem(u16* pMem, u32 size) // size now in 16bit units
{ {
if (cyclePtr != nullptr) TimeUpdate(psxRegs.cycle);
TimeUpdate(*cyclePtr);
FileLog("[%10d] SPU2 readDMA4Mem size %x\n", Cycles, size << 1); FileLog("[%10d] SPU2 readDMA4Mem size %x\n", Cycles, size << 1);
Cores[0].DoDMAread(pMem, size); Cores[0].DoDMAread(pMem, size);
@ -86,8 +84,7 @@ void SPU2readDMA4Mem(u16* pMem, u32 size) // size now in 16bit units
void SPU2writeDMA4Mem(u16* pMem, u32 size) // size now in 16bit units void SPU2writeDMA4Mem(u16* pMem, u32 size) // size now in 16bit units
{ {
if (cyclePtr != nullptr) TimeUpdate(psxRegs.cycle);
TimeUpdate(*cyclePtr);
FileLog("[%10d] SPU2 writeDMA4Mem size %x at address %x\n", Cycles, size << 1, Cores[0].TSA); FileLog("[%10d] SPU2 writeDMA4Mem size %x at address %x\n", Cycles, size << 1, Cores[0].TSA);
@ -114,8 +111,7 @@ void SPU2interruptDMA7()
void SPU2readDMA7Mem(u16* pMem, u32 size) void SPU2readDMA7Mem(u16* pMem, u32 size)
{ {
if (cyclePtr != nullptr) TimeUpdate(psxRegs.cycle);
TimeUpdate(*cyclePtr);
FileLog("[%10d] SPU2 readDMA7Mem size %x\n", Cycles, size << 1); FileLog("[%10d] SPU2 readDMA7Mem size %x\n", Cycles, size << 1);
Cores[1].DoDMAread(pMem, size); Cores[1].DoDMAread(pMem, size);
@ -123,8 +119,7 @@ void SPU2readDMA7Mem(u16* pMem, u32 size)
void SPU2writeDMA7Mem(u16* pMem, u32 size) void SPU2writeDMA7Mem(u16* pMem, u32 size)
{ {
if (cyclePtr != nullptr) TimeUpdate(psxRegs.cycle);
TimeUpdate(*cyclePtr);
FileLog("[%10d] SPU2 writeDMA7Mem size %x at address %x\n", Cycles, size << 1, Cores[1].TSA); FileLog("[%10d] SPU2 writeDMA7Mem size %x at address %x\n", Cycles, size << 1, Cores[1].TSA);
@ -329,7 +324,7 @@ s32 SPU2open(void* pDsp)
#endif #endif
IsOpened = true; IsOpened = true;
lClocks = (cyclePtr != nullptr) ? *cyclePtr : 0; lClocks = psxRegs.cycle;
try try
{ {
@ -347,7 +342,6 @@ s32 SPU2open(void* pDsp)
return -1; return -1;
} }
SPU2setDMABaseAddr((uptr)iopMem->Main); SPU2setDMABaseAddr((uptr)iopMem->Main);
SPU2setClockPtr(&psxRegs.cycle);
return 0; return 0;
} }
@ -418,15 +412,7 @@ void SPU2async(u32 cycles)
{ {
DspUpdate(); DspUpdate();
if (cyclePtr != nullptr) TimeUpdate(psxRegs.cycle);
{
TimeUpdate(*cyclePtr);
}
else
{
pClocks += cycles;
TimeUpdate(pClocks);
}
#ifdef DEBUG_KEYS #ifdef DEBUG_KEYS
u32 curTicks = GetTickCount(); u32 curTicks = GetTickCount();
@ -506,8 +492,7 @@ u16 SPU2read(u32 rmem)
} }
else else
{ {
if (cyclePtr != nullptr) TimeUpdate(psxRegs.cycle);
TimeUpdate(*cyclePtr);
if (rmem >> 16 == 0x1f80) if (rmem >> 16 == 0x1f80)
{ {
@ -535,8 +520,7 @@ void SPU2write(u32 rmem, u16 value)
// If the SPU2 isn't in in sync with the IOP, samples can end up playing at rather // If the SPU2 isn't in in sync with the IOP, samples can end up playing at rather
// incorrect pitches and loop lengths. // incorrect pitches and loop lengths.
if (cyclePtr != nullptr) TimeUpdate(psxRegs.cycle);
TimeUpdate(*cyclePtr);
if (rmem >> 16 == 0x1f80) if (rmem >> 16 == 0x1f80)
Cores[0].WriteRegPS1(rmem, value); Cores[0].WriteRegPS1(rmem, value);

1
pcsx2/SPU2/spu2.h
View File

@ -57,7 +57,6 @@ void SPU2writeDMA7Mem(u16* pMem, u32 size);
extern u8 callirq; extern u8 callirq;
extern u32 lClocks; extern u32 lClocks;
extern u32* cyclePtr;
extern void SPU2writeLog(const char* action, u32 rmem, u16 value); extern void SPU2writeLog(const char* action, u32 rmem, u16 value);
extern void TimeUpdate(u32 cClocks); extern void TimeUpdate(u32 cClocks);

12
pcsx2/SPU2/spu2sys.cpp
View File

@ -453,11 +453,11 @@ __forceinline void TimeUpdate(u32 cClocks)
} }
//Update DMA4 interrupt delay counter //Update DMA4 interrupt delay counter
if (Cores[0].DMAICounter > 0 && (*cyclePtr - Cores[0].LastClock) > 0) if (Cores[0].DMAICounter > 0 && (psxRegs.cycle - Cores[0].LastClock) > 0)
{ {
const u32 amt = std::min(*cyclePtr - Cores[0].LastClock, (u32)Cores[0].DMAICounter); const u32 amt = std::min(psxRegs.cycle - Cores[0].LastClock, (u32)Cores[0].DMAICounter);
Cores[0].DMAICounter -= amt; Cores[0].DMAICounter -= amt;
Cores[0].LastClock = *cyclePtr; Cores[0].LastClock = psxRegs.cycle;
if(!Cores[0].AdmaInProgress) if(!Cores[0].AdmaInProgress)
HW_DMA4_MADR += amt / 2; HW_DMA4_MADR += amt / 2;
@ -506,11 +506,11 @@ __forceinline void TimeUpdate(u32 cClocks)
} }
//Update DMA7 interrupt delay counter //Update DMA7 interrupt delay counter
if (Cores[1].DMAICounter > 0 && (*cyclePtr - Cores[1].LastClock) > 0) if (Cores[1].DMAICounter > 0 && (psxRegs.cycle - Cores[1].LastClock) > 0)
{ {
const u32 amt = std::min(*cyclePtr - Cores[1].LastClock, (u32)Cores[1].DMAICounter); const u32 amt = std::min(psxRegs.cycle - Cores[1].LastClock, (u32)Cores[1].DMAICounter);
Cores[1].DMAICounter -= amt; Cores[1].DMAICounter -= amt;
Cores[1].LastClock = *cyclePtr; Cores[1].LastClock = psxRegs.cycle;
if (!Cores[1].AdmaInProgress) if (!Cores[1].AdmaInProgress)
HW_DMA7_MADR += amt / 2; HW_DMA7_MADR += amt / 2;
if (Cores[1].DMAICounter <= 0) if (Cores[1].DMAICounter <= 0)