mirror of https://github.com/PCSX2/pcsx2.git
EE: vtlb handler for writes to IOP mem
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@ -436,7 +436,8 @@ static vtlbHandler
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iopHw_by_page_01,
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iopHw_by_page_01,
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iopHw_by_page_03,
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iopHw_by_page_03,
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iopHw_by_page_08;
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iopHw_by_page_08,
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iop_memory;
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void memMapVUmicro()
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void memMapVUmicro()
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@ -480,7 +481,7 @@ void memMapPhy()
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// IOP memory
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// IOP memory
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// (used by the EE Bios Kernel during initial hardware initialization, Apps/Games
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// (used by the EE Bios Kernel during initial hardware initialization, Apps/Games
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// are "supposed" to use the thread-safe SIF instead.)
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// are "supposed" to use the thread-safe SIF instead.)
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vtlb_MapBlock(iopMem->Main,0x1c000000,0x00800000);
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vtlb_MapHandler(iop_memory,0x1c000000,0x00800000);
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// Generic Handlers; These fallback to mem* stuff...
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// Generic Handlers; These fallback to mem* stuff...
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vtlb_MapHandler(tlb_fallback_7,0x14000000, _64kb);
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vtlb_MapHandler(tlb_fallback_7,0x14000000, _64kb);
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@ -586,6 +587,8 @@ static mem8_t _ext_memRead8 (u32 mem)
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Console.WriteLn("DEV9 read8 %8.8lx: %2.2lx", mem & ~0xa4000000, retval);
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Console.WriteLn("DEV9 read8 %8.8lx: %2.2lx", mem & ~0xa4000000, retval);
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return retval;
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return retval;
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}
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}
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case 9:
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return iopMemRead8(mem & ~0x1c000000);
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default: break;
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default: break;
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}
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}
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@ -617,6 +620,8 @@ static mem16_t _ext_memRead16(u32 mem)
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case 8: // spu2
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case 8: // spu2
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return SPU2read(mem);
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return SPU2read(mem);
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case 9:
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return iopMemRead16(mem & ~0x1c000000);
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default: break;
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default: break;
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}
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}
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@ -638,6 +643,8 @@ static mem32_t _ext_memRead32(u32 mem)
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Console.WriteLn("DEV9 read32 %8.8lx: %8.8lx", mem & ~0xa4000000, retval);
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Console.WriteLn("DEV9 read32 %8.8lx: %8.8lx", mem & ~0xa4000000, retval);
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return retval;
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return retval;
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}
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}
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case 9:
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return iopMemRead32(mem & ~0x1c000000);
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default: break;
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default: break;
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}
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}
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@ -653,6 +660,13 @@ static u64 _ext_memRead64(u32 mem)
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{
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{
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case 6: // gsm
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case 6: // gsm
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return gsRead64(mem);
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return gsRead64(mem);
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case 9:
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{
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u64 ret = 0;
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ret |= ((u64)(iopMemRead32((mem + 0) & ~0x1c000000)) << 0);
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ret |= ((u64)(iopMemRead32((mem + 4) & ~0x1c000000)) << 32);
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return ret;
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}
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default: break;
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default: break;
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}
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}
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@ -670,6 +684,15 @@ static RETURNS_R128 _ext_memRead128(u32 mem)
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// return hwRead128(mem & ~0xa0000000);
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// return hwRead128(mem & ~0xa0000000);
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case 6: // gsm
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case 6: // gsm
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return r128_load(PS2GS_BASE(mem));
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return r128_load(PS2GS_BASE(mem));
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case 9:
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{
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u128 ret = {};
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ret._u32[0] = iopMemRead32((mem + 0) & ~0x1c000000);
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ret._u32[1] = iopMemRead32((mem + 4) & ~0x1c000000);
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ret._u32[2] = iopMemRead32((mem + 8) & ~0x1c000000);
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ret._u32[3] = iopMemRead32((mem + 12) & ~0x1c000000);
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return r128_from_u128(ret);
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}
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default: break;
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default: break;
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}
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}
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@ -690,6 +713,9 @@ static void _ext_memWrite8 (u32 mem, mem8_t value)
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DEV9write8(mem & ~0xa4000000, value);
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DEV9write8(mem & ~0xa4000000, value);
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Console.WriteLn("DEV9 write8 %8.8lx: %2.2lx", mem & ~0xa4000000, value);
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Console.WriteLn("DEV9 write8 %8.8lx: %2.2lx", mem & ~0xa4000000, value);
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return;
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return;
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case 9:
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iopMemWrite8(mem & ~0x1c000000, value);
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return;
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default: break;
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default: break;
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}
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}
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@ -713,6 +739,9 @@ static void _ext_memWrite16(u32 mem, mem16_t value)
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return;
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return;
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case 8: // spu2
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case 8: // spu2
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SPU2write(mem, value); return;
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SPU2write(mem, value); return;
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case 9:
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iopMemWrite16(mem & ~0x1c000000, value);
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return;
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default: break;
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default: break;
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}
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}
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MEM_LOG("Unknown Memory write16 to address %x with data %4.4x", mem, value);
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MEM_LOG("Unknown Memory write16 to address %x with data %4.4x", mem, value);
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@ -729,6 +758,9 @@ static void _ext_memWrite32(u32 mem, mem32_t value)
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DEV9write32(mem & ~0xa4000000, value);
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DEV9write32(mem & ~0xa4000000, value);
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Console.WriteLn("DEV9 write32 %8.8lx: %8.8lx", mem & ~0xa4000000, value);
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Console.WriteLn("DEV9 write32 %8.8lx: %8.8lx", mem & ~0xa4000000, value);
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return;
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return;
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case 9:
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iopMemWrite32(mem & ~0x1c000000, value);
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return;
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default: break;
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default: break;
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}
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}
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MEM_LOG("Unknown Memory write32 to address %x with data %8.8x", mem, value);
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MEM_LOG("Unknown Memory write32 to address %x with data %8.8x", mem, value);
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@ -738,7 +770,15 @@ static void _ext_memWrite32(u32 mem, mem32_t value)
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template<int p>
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template<int p>
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static void _ext_memWrite64(u32 mem, mem64_t value)
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static void _ext_memWrite64(u32 mem, mem64_t value)
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{
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{
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switch (p)
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{
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case 9:
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iopMemWrite32((mem + 0) & ~0x1c000000, (value >> 0) & 0xffffffff);
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iopMemWrite32((mem + 4) & ~0x1c000000, (value >> 32) & 0xffffffff);
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return;
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default:
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break;
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}
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/*switch (p) {
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/*switch (p) {
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//case 1: // hwm
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//case 1: // hwm
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// hwWrite64(mem & ~0xa0000000, *value);
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// hwWrite64(mem & ~0xa0000000, *value);
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@ -754,6 +794,21 @@ static void _ext_memWrite64(u32 mem, mem64_t value)
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template<int p>
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template<int p>
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static void TAKES_R128 _ext_memWrite128(u32 mem, r128 value)
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static void TAKES_R128 _ext_memWrite128(u32 mem, r128 value)
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{
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{
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switch (p)
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{
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case 9:
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{
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u128 val = r128_to_u128(value);
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iopMemWrite32((mem + 0) & ~0x1c000000, val._u32[0] & 0xffffffff);
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iopMemWrite32((mem + 4) & ~0x1c000000, val._u32[1] & 0xffffffff);
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iopMemWrite32((mem + 8) & ~0x1c000000, val._u32[2] & 0xffffffff);
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iopMemWrite32((mem + 12) & ~0x1c000000, val._u32[3] & 0xffffffff);
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return;
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}
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default:
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break;
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}
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/*switch (p) {
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/*switch (p) {
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//case 1: // hwm
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//case 1: // hwm
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// hwWrite128(mem & ~0xa0000000, value);
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// hwWrite128(mem & ~0xa0000000, value);
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@ -1056,6 +1111,7 @@ void memReset()
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tlb_fallback_5 = vtlb_RegisterHandlerTempl1(_ext_mem,5);
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tlb_fallback_5 = vtlb_RegisterHandlerTempl1(_ext_mem,5);
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tlb_fallback_7 = vtlb_RegisterHandlerTempl1(_ext_mem,7);
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tlb_fallback_7 = vtlb_RegisterHandlerTempl1(_ext_mem,7);
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tlb_fallback_8 = vtlb_RegisterHandlerTempl1(_ext_mem,8);
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tlb_fallback_8 = vtlb_RegisterHandlerTempl1(_ext_mem,8);
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iop_memory = vtlb_RegisterHandlerTempl1(_ext_mem,9);
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// Dynarec versions of VUs
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// Dynarec versions of VUs
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vu0_micro_mem = vtlb_RegisterHandlerTempl1(vuMicro,0);
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vu0_micro_mem = vtlb_RegisterHandlerTempl1(vuMicro,0);
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@ -1090,7 +1146,6 @@ void memReset()
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iopHwWrite8_Page8, iopHwWrite16_Page8, iopHwWrite32_Page8, _ext_memWrite64<2>, _ext_memWrite128<2>
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iopHwWrite8_Page8, iopHwWrite16_Page8, iopHwWrite32_Page8, _ext_memWrite64<2>, _ext_memWrite128<2>
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);
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);
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// psHw Optimized Mappings
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// psHw Optimized Mappings
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// The HW Registers have been split into pages to improve optimization.
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// The HW Registers have been split into pages to improve optimization.
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