mirror of https://github.com/PCSX2/pcsx2.git
DEV9: fix wide char conversion & review fixes
This commit is contained in:
GovanifY
refractionpcsx2
parent
ba14536441
commit
667ccfad76
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@ -1,5 +1,5 @@
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/* PCSX2 - PS2 Emulator for PCs
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* Copyright (C) 2002-2010 PCSX2 Dev Team
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* Copyright (C) 2002-2020 PCSX2 Dev Team
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*
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* PCSX2 is free software: you can redistribute it and/or modify it under the terms
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* of the GNU Lesser General Public License as published by the Free Software Found-
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@ -1,5 +1,5 @@
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/* PCSX2 - PS2 Emulator for PCs
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* Copyright (C) 2002-2010 PCSX2 Dev Team
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* Copyright (C) 2002-2020 PCSX2 Dev Team
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*
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* PCSX2 is free software: you can redistribute it and/or modify it under the terms
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* of the GNU Lesser General Public License as published by the Free Software Found-
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@ -70,73 +70,19 @@ static __inline__ unsigned long long GetTickCount(void)
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#endif
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// clang-format off
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u8 eeprom[] = {
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//0x6D, 0x76, 0x63, 0x61, 0x31, 0x30, 0x08, 0x01,
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0x76,
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0x6D,
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0x61,
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0x63,
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0x30,
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0x31,
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0x07,
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0x02,
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0x00,
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0x00,
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0x00,
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0x00,
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0x00,
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0x00,
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0x00,
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0x00,
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0x00,
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0x00,
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0x10,
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0x00,
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0x00,
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0x00,
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0x00,
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0x00,
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0x00,
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0x00,
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0x00,
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0x00,
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0x00,
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0x00,
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0x00,
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0x00,
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0x00,
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0x10,
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0x00,
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0x00,
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0x00,
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0x00,
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0x00,
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0x00,
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0x00,
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0x00,
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0x00,
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0x00,
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0x00,
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0x00,
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0x00,
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0x00,
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0x10,
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0x00,
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0x00,
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0x00,
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0x00,
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0x00,
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0x00,
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0x00,
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0x00,
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0x00,
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0x00,
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0x00,
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0x00,
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0x00,
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0x00,
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0x00,
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0x76, 0x6D, 0x61, 0x63, 0x30, 0x31, 0x07, 0x02,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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};
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// clang-format on
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u32* iopPC;
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@ -1,5 +1,5 @@
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/* PCSX2 - PS2 Emulator for PCs
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* Copyright (C) 2002-2010 PCSX2 Dev Team
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* Copyright (C) 2002-2020 PCSX2 Dev Team
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*
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* PCSX2 is free software: you can redistribute it and/or modify it under the terms
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* of the GNU Lesser General Public License as published by the Free Software Found-
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@ -145,38 +145,40 @@ void SysMessage(char* fmt, ...);
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* * code included from the ps2smap iop driver, modified by linuzappz *
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*/
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#define SPD_REGBASE 0x10000000
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// clang-format off
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#define SPD_R_REV (SPD_REGBASE + 0x00)
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#define SPD_R_REV_1 (SPD_REGBASE + 0x02)
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// bit 0: smap
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// bit 1: hdd
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// bit 5: flash
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#define SPD_R_REV_3 (SPD_REGBASE + 0x04)
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#define SPD_R_0e (SPD_REGBASE + 0x0e)
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#define SPD_REGBASE 0x10000000
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#define SPD_R_DMA_CTRL (SPD_REGBASE + 0x24)
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#define SPD_R_INTR_STAT (SPD_REGBASE + 0x28)
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#define SPD_R_INTR_MASK (SPD_REGBASE + 0x2a)
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#define SPD_R_PIO_DIR (SPD_REGBASE + 0x2c)
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#define SPD_R_PIO_DATA (SPD_REGBASE + 0x2e)
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#define SPD_PP_DOUT (1 << 4) /* Data output, read port */
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#define SPD_PP_DIN (1 << 5) /* Data input, write port */
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#define SPD_PP_SCLK (1 << 6) /* Clock, write port */
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#define SPD_PP_CSEL (1 << 7) /* Chip select, write port */
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#define SPD_R_REV (SPD_REGBASE + 0x00)
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#define SPD_R_REV_1 (SPD_REGBASE + 0x02)
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// bit 0: smap
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// bit 1: hdd
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// bit 5: flash
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#define SPD_R_REV_3 (SPD_REGBASE + 0x04)
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#define SPD_R_0e (SPD_REGBASE + 0x0e)
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#define SPD_R_DMA_CTRL (SPD_REGBASE + 0x24)
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#define SPD_R_INTR_STAT (SPD_REGBASE + 0x28)
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#define SPD_R_INTR_MASK (SPD_REGBASE + 0x2a)
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#define SPD_R_PIO_DIR (SPD_REGBASE + 0x2c)
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#define SPD_R_PIO_DATA (SPD_REGBASE + 0x2e)
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#define SPD_PP_DOUT (1<<4) /* Data output, read port */
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#define SPD_PP_DIN (1<<5) /* Data input, write port */
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#define SPD_PP_SCLK (1<<6) /* Clock, write port */
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#define SPD_PP_CSEL (1<<7) /* Chip select, write port */
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/* Operation codes */
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#define SPD_PP_OP_READ 2
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#define SPD_PP_OP_WRITE 1
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#define SPD_PP_OP_EWEN 0
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#define SPD_PP_OP_EWDS 0
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#define SPD_PP_OP_READ 2
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#define SPD_PP_OP_WRITE 1
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#define SPD_PP_OP_EWEN 0
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#define SPD_PP_OP_EWDS 0
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#define SPD_R_XFR_CTRL (SPD_REGBASE + 0x32)
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#define SPD_R_IF_CTRL (SPD_REGBASE + 0x64)
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#define SPD_IF_ATA_RESET 0x80
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#define SPD_IF_DMA_ENABLE 0x04
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#define SPD_R_PIO_MODE (SPD_REGBASE + 0x70)
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#define SPD_R_MWDMA_MODE (SPD_REGBASE + 0x72)
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#define SPD_R_UDMA_MODE (SPD_REGBASE + 0x74)
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#define SPD_R_XFR_CTRL (SPD_REGBASE + 0x32)
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#define SPD_R_IF_CTRL (SPD_REGBASE + 0x64)
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#define SPD_IF_ATA_RESET 0x80
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#define SPD_IF_DMA_ENABLE 0x04
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#define SPD_R_PIO_MODE (SPD_REGBASE + 0x70)
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#define SPD_R_MWDMA_MODE (SPD_REGBASE + 0x72)
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#define SPD_R_UDMA_MODE (SPD_REGBASE + 0x74)
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/*
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@ -189,366 +191,367 @@ void SysMessage(char* fmt, ...);
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/* SMAP interrupt status bits (selected from the SPEED device). */
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#define SMAP_INTR_EMAC3 (1 << 6)
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#define SMAP_INTR_RXEND (1 << 5)
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#define SMAP_INTR_TXEND (1 << 4)
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#define SMAP_INTR_RXDNV (1 << 3) /* descriptor not valid */
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#define SMAP_INTR_TXDNV (1 << 2) /* descriptor not valid */
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#define SMAP_INTR_CLR_ALL (SMAP_INTR_RXEND | SMAP_INTR_TXEND | SMAP_INTR_RXDNV)
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#define SMAP_INTR_ENA_ALL (SMAP_INTR_EMAC3 | SMAP_INTR_CLR_ALL)
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#define SMAP_INTR_BITMSK 0x7C
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#define SMAP_INTR_EMAC3 (1<<6)
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#define SMAP_INTR_RXEND (1<<5)
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#define SMAP_INTR_TXEND (1<<4)
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#define SMAP_INTR_RXDNV (1<<3) /* descriptor not valid */
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#define SMAP_INTR_TXDNV (1<<2) /* descriptor not valid */
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#define SMAP_INTR_CLR_ALL (SMAP_INTR_RXEND|SMAP_INTR_TXEND|SMAP_INTR_RXDNV)
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#define SMAP_INTR_ENA_ALL (SMAP_INTR_EMAC3|SMAP_INTR_CLR_ALL)
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#define SMAP_INTR_BITMSK 0x7C
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/* SMAP Register Definitions. */
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#define SMAP_REGBASE (SPD_REGBASE + 0x100)
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#define SMAP_REGBASE (SPD_REGBASE + 0x100)
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#define SMAP_R_BD_MODE (SMAP_REGBASE + 0x02)
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#define SMAP_BD_SWAP (1 << 0)
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#define SMAP_R_BD_MODE (SMAP_REGBASE + 0x02)
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#define SMAP_BD_SWAP (1<<0)
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#define SMAP_R_INTR_CLR (SMAP_REGBASE + 0x28)
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#define SMAP_R_INTR_CLR (SMAP_REGBASE + 0x28)
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/* SMAP FIFO Registers. */
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#define SMAP_R_TXFIFO_CTRL (SMAP_REGBASE + 0xf00)
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#define SMAP_TXFIFO_RESET (1 << 0)
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#define SMAP_TXFIFO_DMAEN (1 << 1)
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#define SMAP_R_TXFIFO_WR_PTR (SMAP_REGBASE + 0xf04)
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#define SMAP_R_TXFIFO_SIZE (SMAP_REGBASE + 0xf08)
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#define SMAP_R_TXFIFO_FRAME_CNT (SMAP_REGBASE + 0xf0C)
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#define SMAP_R_TXFIFO_FRAME_INC (SMAP_REGBASE + 0xf10)
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#define SMAP_R_TXFIFO_DATA (SMAP_REGBASE + 0x1000)
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#define SMAP_R_TXFIFO_CTRL (SMAP_REGBASE + 0xf00)
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#define SMAP_TXFIFO_RESET (1<<0)
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#define SMAP_TXFIFO_DMAEN (1<<1)
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#define SMAP_R_TXFIFO_WR_PTR (SMAP_REGBASE + 0xf04)
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#define SMAP_R_TXFIFO_SIZE (SMAP_REGBASE + 0xf08)
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#define SMAP_R_TXFIFO_FRAME_CNT (SMAP_REGBASE + 0xf0C)
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#define SMAP_R_TXFIFO_FRAME_INC (SMAP_REGBASE + 0xf10)
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#define SMAP_R_TXFIFO_DATA (SMAP_REGBASE + 0x1000)
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#define SMAP_R_RXFIFO_CTRL (SMAP_REGBASE + 0xf30)
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#define SMAP_RXFIFO_RESET (1 << 0)
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#define SMAP_RXFIFO_DMAEN (1 << 1)
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#define SMAP_R_RXFIFO_RD_PTR (SMAP_REGBASE + 0xf34)
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#define SMAP_R_RXFIFO_SIZE (SMAP_REGBASE + 0xf38)
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#define SMAP_R_RXFIFO_FRAME_CNT (SMAP_REGBASE + 0xf3C)
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#define SMAP_R_RXFIFO_FRAME_DEC (SMAP_REGBASE + 0xf40)
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#define SMAP_R_RXFIFO_DATA (SMAP_REGBASE + 0x1100)
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#define SMAP_R_FIFO_ADDR (SMAP_REGBASE + 0x1200)
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#define SMAP_FIFO_CMD_READ (1 << 1)
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#define SMAP_FIFO_DATA_SWAP (1 << 0)
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#define SMAP_R_FIFO_DATA (SMAP_REGBASE + 0x1208)
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#define SMAP_R_RXFIFO_CTRL (SMAP_REGBASE + 0xf30)
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#define SMAP_RXFIFO_RESET (1<<0)
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#define SMAP_RXFIFO_DMAEN (1<<1)
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#define SMAP_R_RXFIFO_RD_PTR (SMAP_REGBASE + 0xf34)
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#define SMAP_R_RXFIFO_SIZE (SMAP_REGBASE + 0xf38)
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#define SMAP_R_RXFIFO_FRAME_CNT (SMAP_REGBASE + 0xf3C)
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#define SMAP_R_RXFIFO_FRAME_DEC (SMAP_REGBASE + 0xf40)
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#define SMAP_R_RXFIFO_DATA (SMAP_REGBASE + 0x1100)
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#define SMAP_R_FIFO_ADDR (SMAP_REGBASE + 0x1200)
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#define SMAP_FIFO_CMD_READ (1<<1)
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#define SMAP_FIFO_DATA_SWAP (1<<0)
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#define SMAP_R_FIFO_DATA (SMAP_REGBASE + 0x1208)
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/* EMAC3 Registers. */
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#define SMAP_EMAC3_REGBASE (SMAP_REGBASE + 0x1f00)
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#define SMAP_EMAC3_REGBASE (SMAP_REGBASE + 0x1f00)
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#define SMAP_R_EMAC3_MODE0_L (SMAP_EMAC3_REGBASE + 0x00)
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#define SMAP_E3_RXMAC_IDLE (1 << (15 + 16))
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#define SMAP_E3_TXMAC_IDLE (1 << (14 + 16))
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#define SMAP_E3_SOFT_RESET (1 << (13 + 16))
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#define SMAP_E3_TXMAC_ENABLE (1 << (12 + 16))
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#define SMAP_E3_RXMAC_ENABLE (1 << (11 + 16))
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#define SMAP_E3_WAKEUP_ENABLE (1 << (10 + 16))
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#define SMAP_R_EMAC3_MODE0_H (SMAP_EMAC3_REGBASE + 0x02)
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#define SMAP_R_EMAC3_MODE0_L (SMAP_EMAC3_REGBASE + 0x00)
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#define SMAP_E3_RXMAC_IDLE (1<<(15+16))
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#define SMAP_E3_TXMAC_IDLE (1<<(14+16))
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#define SMAP_E3_SOFT_RESET (1<<(13+16))
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#define SMAP_E3_TXMAC_ENABLE (1<<(12+16))
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#define SMAP_E3_RXMAC_ENABLE (1<<(11+16))
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#define SMAP_E3_WAKEUP_ENABLE (1<<(10+16))
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#define SMAP_R_EMAC3_MODE0_H (SMAP_EMAC3_REGBASE + 0x02)
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#define SMAP_R_EMAC3_MODE1 (SMAP_EMAC3_REGBASE + 0x04)
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#define SMAP_R_EMAC3_MODE1_L (SMAP_EMAC3_REGBASE + 0x04)
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#define SMAP_R_EMAC3_MODE1_H (SMAP_EMAC3_REGBASE + 0x06)
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#define SMAP_E3_FDX_ENABLE (1 << 31)
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#define SMAP_E3_INLPBK_ENABLE (1 << 30) /* internal loop back */
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#define SMAP_E3_VLAN_ENABLE (1 << 29)
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#define SMAP_E3_FLOWCTRL_ENABLE (1 << 28) /* integrated flow ctrl(pause frame) */
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#define SMAP_E3_ALLOW_PF (1 << 27) /* allow pause frame */
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#define SMAP_E3_ALLOW_EXTMNGIF (1 << 25) /* allow external management IF */
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#define SMAP_E3_IGNORE_SQE (1 << 24)
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#define SMAP_E3_MEDIA_FREQ_BITSFT (22)
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#define SMAP_E3_MEDIA_10M (0 << 22)
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#define SMAP_E3_MEDIA_100M (1 << 22)
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#define SMAP_E3_MEDIA_1000M (2 << 22)
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#define SMAP_E3_MEDIA_MSK (3 << 22)
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#define SMAP_E3_RXFIFO_SIZE_BITSFT (20)
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#define SMAP_E3_RXFIFO_512 (0 << 20)
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#define SMAP_E3_RXFIFO_1K (1 << 20)
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#define SMAP_E3_RXFIFO_2K (2 << 20)
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#define SMAP_E3_RXFIFO_4K (3 << 20)
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#define SMAP_E3_TXFIFO_SIZE_BITSFT (18)
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#define SMAP_E3_TXFIFO_512 (0 << 18)
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#define SMAP_E3_TXFIFO_1K (1 << 18)
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#define SMAP_E3_TXFIFO_2K (2 << 18)
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#define SMAP_E3_TXREQ0_BITSFT (15)
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#define SMAP_E3_TXREQ0_SINGLE (0 << 15)
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#define SMAP_E3_TXREQ0_MULTI (1 << 15)
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#define SMAP_E3_TXREQ0_DEPEND (2 << 15)
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#define SMAP_E3_TXREQ1_BITSFT (13)
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#define SMAP_E3_TXREQ1_SINGLE (0 << 13)
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#define SMAP_E3_TXREQ1_MULTI (1 << 13)
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#define SMAP_E3_TXREQ1_DEPEND (2 << 13)
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#define SMAP_E3_JUMBO_ENABLE (1 << 12)
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#define SMAP_R_EMAC3_MODE1 (SMAP_EMAC3_REGBASE + 0x04)
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#define SMAP_R_EMAC3_MODE1_L (SMAP_EMAC3_REGBASE + 0x04)
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#define SMAP_R_EMAC3_MODE1_H (SMAP_EMAC3_REGBASE + 0x06)
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#define SMAP_E3_FDX_ENABLE (1<<31)
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#define SMAP_E3_INLPBK_ENABLE (1<<30) /* internal loop back */
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#define SMAP_E3_VLAN_ENABLE (1<<29)
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#define SMAP_E3_FLOWCTRL_ENABLE (1<<28) /* integrated flow ctrl(pause frame) */
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#define SMAP_E3_ALLOW_PF (1<<27) /* allow pause frame */
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#define SMAP_E3_ALLOW_EXTMNGIF (1<<25) /* allow external management IF */
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#define SMAP_E3_IGNORE_SQE (1<<24)
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#define SMAP_E3_MEDIA_FREQ_BITSFT (22)
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#define SMAP_E3_MEDIA_10M (0<<22)
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#define SMAP_E3_MEDIA_100M (1<<22)
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#define SMAP_E3_MEDIA_1000M (2<<22)
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#define SMAP_E3_MEDIA_MSK (3<<22)
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#define SMAP_E3_RXFIFO_SIZE_BITSFT (20)
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#define SMAP_E3_RXFIFO_512 (0<<20)
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#define SMAP_E3_RXFIFO_1K (1<<20)
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#define SMAP_E3_RXFIFO_2K (2<<20)
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#define SMAP_E3_RXFIFO_4K (3<<20)
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#define SMAP_E3_TXFIFO_SIZE_BITSFT (18)
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#define SMAP_E3_TXFIFO_512 (0<<18)
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#define SMAP_E3_TXFIFO_1K (1<<18)
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#define SMAP_E3_TXFIFO_2K (2<<18)
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#define SMAP_E3_TXREQ0_BITSFT (15)
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#define SMAP_E3_TXREQ0_SINGLE (0<<15)
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#define SMAP_E3_TXREQ0_MULTI (1<<15)
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#define SMAP_E3_TXREQ0_DEPEND (2<<15)
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#define SMAP_E3_TXREQ1_BITSFT (13)
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#define SMAP_E3_TXREQ1_SINGLE (0<<13)
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#define SMAP_E3_TXREQ1_MULTI (1<<13)
|
||||
#define SMAP_E3_TXREQ1_DEPEND (2<<13)
|
||||
#define SMAP_E3_JUMBO_ENABLE (1<<12)
|
||||
|
||||
#define SMAP_R_EMAC3_TxMODE0_L (SMAP_EMAC3_REGBASE + 0x08)
|
||||
#define SMAP_E3_TX_GNP_0 (1 << (15 + 16)) /* get new packet */
|
||||
#define SMAP_E3_TX_GNP_1 (1 << (14 + 16)) /* get new packet */
|
||||
#define SMAP_E3_TX_GNP_DEPEND (1 << (13 + 16)) /* get new packet */
|
||||
#define SMAP_E3_TX_FIRST_CHANNEL (1 << (12 + 16))
|
||||
#define SMAP_R_EMAC3_TxMODE0_H (SMAP_EMAC3_REGBASE + 0x0A)
|
||||
#define SMAP_R_EMAC3_TxMODE0_L (SMAP_EMAC3_REGBASE + 0x08)
|
||||
#define SMAP_E3_TX_GNP_0 (1<<(15+16)) /* get new packet */
|
||||
#define SMAP_E3_TX_GNP_1 (1<<(14+16)) /* get new packet */
|
||||
#define SMAP_E3_TX_GNP_DEPEND (1<<(13+16)) /* get new packet */
|
||||
#define SMAP_E3_TX_FIRST_CHANNEL (1<<(12+16))
|
||||
#define SMAP_R_EMAC3_TxMODE0_H (SMAP_EMAC3_REGBASE + 0x0A)
|
||||
|
||||
#define SMAP_R_EMAC3_TxMODE1_L (SMAP_EMAC3_REGBASE + 0x0C)
|
||||
#define SMAP_R_EMAC3_TxMODE1_H (SMAP_EMAC3_REGBASE + 0x0E)
|
||||
#define SMAP_E3_TX_LOW_REQ_MSK (0x1F) /* low priority request */
|
||||
#define SMAP_E3_TX_LOW_REQ_BITSFT (27) /* low priority request */
|
||||
#define SMAP_E3_TX_URG_REQ_MSK (0xFF) /* urgent priority request */
|
||||
#define SMAP_E3_TX_URG_REQ_BITSFT (16) /* urgent priority request */
|
||||
#define SMAP_R_EMAC3_TxMODE1_L (SMAP_EMAC3_REGBASE + 0x0C)
|
||||
#define SMAP_R_EMAC3_TxMODE1_H (SMAP_EMAC3_REGBASE + 0x0E)
|
||||
#define SMAP_E3_TX_LOW_REQ_MSK (0x1F) /* low priority request */
|
||||
#define SMAP_E3_TX_LOW_REQ_BITSFT (27) /* low priority request */
|
||||
#define SMAP_E3_TX_URG_REQ_MSK (0xFF) /* urgent priority request */
|
||||
#define SMAP_E3_TX_URG_REQ_BITSFT (16) /* urgent priority request */
|
||||
|
||||
#define SMAP_R_EMAC3_RxMODE (SMAP_EMAC3_REGBASE + 0x10)
|
||||
#define SMAP_R_EMAC3_RxMODE_L (SMAP_EMAC3_REGBASE + 0x10)
|
||||
#define SMAP_R_EMAC3_RxMODE_H (SMAP_EMAC3_REGBASE + 0x12)
|
||||
#define SMAP_E3_RX_STRIP_PAD (1 << 31)
|
||||
#define SMAP_E3_RX_STRIP_FCS (1 << 30)
|
||||
#define SMAP_E3_RX_RX_RUNT_FRAME (1 << 29)
|
||||
#define SMAP_E3_RX_RX_FCS_ERR (1 << 28)
|
||||
#define SMAP_E3_RX_RX_TOO_LONG_ERR (1 << 27)
|
||||
#define SMAP_E3_RX_RX_IN_RANGE_ERR (1 << 26)
|
||||
#define SMAP_E3_RX_PROP_PF (1 << 25) /* propagate pause frame */
|
||||
#define SMAP_E3_RX_PROMISC (1 << 24)
|
||||
#define SMAP_E3_RX_PROMISC_MCAST (1 << 23)
|
||||
#define SMAP_E3_RX_INDIVID_ADDR (1 << 22)
|
||||
#define SMAP_E3_RX_INDIVID_HASH (1 << 21)
|
||||
#define SMAP_E3_RX_BCAST (1 << 20)
|
||||
#define SMAP_E3_RX_MCAST (1 << 19)
|
||||
#define SMAP_R_EMAC3_RxMODE (SMAP_EMAC3_REGBASE + 0x10)
|
||||
#define SMAP_R_EMAC3_RxMODE_L (SMAP_EMAC3_REGBASE + 0x10)
|
||||
#define SMAP_R_EMAC3_RxMODE_H (SMAP_EMAC3_REGBASE + 0x12)
|
||||
#define SMAP_E3_RX_STRIP_PAD (1<<31)
|
||||
#define SMAP_E3_RX_STRIP_FCS (1<<30)
|
||||
#define SMAP_E3_RX_RX_RUNT_FRAME (1<<29)
|
||||
#define SMAP_E3_RX_RX_FCS_ERR (1<<28)
|
||||
#define SMAP_E3_RX_RX_TOO_LONG_ERR (1<<27)
|
||||
#define SMAP_E3_RX_RX_IN_RANGE_ERR (1<<26)
|
||||
#define SMAP_E3_RX_PROP_PF (1<<25) /* propagate pause frame */
|
||||
#define SMAP_E3_RX_PROMISC (1<<24)
|
||||
#define SMAP_E3_RX_PROMISC_MCAST (1<<23)
|
||||
#define SMAP_E3_RX_INDIVID_ADDR (1<<22)
|
||||
#define SMAP_E3_RX_INDIVID_HASH (1<<21)
|
||||
#define SMAP_E3_RX_BCAST (1<<20)
|
||||
#define SMAP_E3_RX_MCAST (1<<19)
|
||||
|
||||
#define SMAP_R_EMAC3_INTR_STAT (SMAP_EMAC3_REGBASE + 0x14)
|
||||
#define SMAP_R_EMAC3_INTR_STAT_L (SMAP_EMAC3_REGBASE + 0x14)
|
||||
#define SMAP_R_EMAC3_INTR_STAT_H (SMAP_EMAC3_REGBASE + 0x16)
|
||||
#define SMAP_R_EMAC3_INTR_ENABLE (SMAP_EMAC3_REGBASE + 0x18)
|
||||
#define SMAP_R_EMAC3_INTR_ENABLE_L (SMAP_EMAC3_REGBASE + 0x18)
|
||||
#define SMAP_R_EMAC3_INTR_ENABLE_H (SMAP_EMAC3_REGBASE + 0x1A)
|
||||
#define SMAP_E3_INTR_OVERRUN (1 << 25) /* this bit does NOT WORKED */
|
||||
#define SMAP_E3_INTR_PF (1 << 24)
|
||||
#define SMAP_E3_INTR_BAD_FRAME (1 << 23)
|
||||
#define SMAP_E3_INTR_RUNT_FRAME (1 << 22)
|
||||
#define SMAP_E3_INTR_SHORT_EVENT (1 << 21)
|
||||
#define SMAP_E3_INTR_ALIGN_ERR (1 << 20)
|
||||
#define SMAP_E3_INTR_BAD_FCS (1 << 19)
|
||||
#define SMAP_E3_INTR_TOO_LONG (1 << 18)
|
||||
#define SMAP_E3_INTR_OUT_RANGE_ERR (1 << 17)
|
||||
#define SMAP_E3_INTR_IN_RANGE_ERR (1 << 16)
|
||||
#define SMAP_E3_INTR_DEAD_DEPEND (1 << 9)
|
||||
#define SMAP_E3_INTR_DEAD_0 (1 << 8)
|
||||
#define SMAP_E3_INTR_SQE_ERR_0 (1 << 7)
|
||||
#define SMAP_E3_INTR_TX_ERR_0 (1 << 6)
|
||||
#define SMAP_E3_INTR_DEAD_1 (1 << 5)
|
||||
#define SMAP_E3_INTR_SQE_ERR_1 (1 << 4)
|
||||
#define SMAP_E3_INTR_TX_ERR_1 (1 << 3)
|
||||
#define SMAP_E3_INTR_MMAOP_SUCCESS (1 << 1)
|
||||
#define SMAP_E3_INTR_MMAOP_FAIL (1 << 0)
|
||||
#define SMAP_E3_INTR_ALL \
|
||||
(SMAP_E3_INTR_OVERRUN | SMAP_E3_INTR_PF | SMAP_E3_INTR_BAD_FRAME | \
|
||||
SMAP_E3_INTR_RUNT_FRAME | SMAP_E3_INTR_SHORT_EVENT | \
|
||||
SMAP_E3_INTR_ALIGN_ERR | SMAP_E3_INTR_BAD_FCS | \
|
||||
SMAP_E3_INTR_TOO_LONG | SMAP_E3_INTR_OUT_RANGE_ERR | \
|
||||
SMAP_E3_INTR_IN_RANGE_ERR | \
|
||||
SMAP_E3_INTR_DEAD_DEPEND | SMAP_E3_INTR_DEAD_0 | \
|
||||
SMAP_E3_INTR_SQE_ERR_0 | SMAP_E3_INTR_TX_ERR_0 | \
|
||||
SMAP_E3_INTR_DEAD_1 | SMAP_E3_INTR_SQE_ERR_1 | \
|
||||
SMAP_E3_INTR_TX_ERR_1 | \
|
||||
SMAP_E3_INTR_MMAOP_SUCCESS | SMAP_E3_INTR_MMAOP_FAIL)
|
||||
#define SMAP_E3_DEAD_ALL \
|
||||
(SMAP_E3_INTR_DEAD_DEPEND | SMAP_E3_INTR_DEAD_0 | \
|
||||
#define SMAP_R_EMAC3_INTR_STAT (SMAP_EMAC3_REGBASE + 0x14)
|
||||
#define SMAP_R_EMAC3_INTR_STAT_L (SMAP_EMAC3_REGBASE + 0x14)
|
||||
#define SMAP_R_EMAC3_INTR_STAT_H (SMAP_EMAC3_REGBASE + 0x16)
|
||||
#define SMAP_R_EMAC3_INTR_ENABLE (SMAP_EMAC3_REGBASE + 0x18)
|
||||
#define SMAP_R_EMAC3_INTR_ENABLE_L (SMAP_EMAC3_REGBASE + 0x18)
|
||||
#define SMAP_R_EMAC3_INTR_ENABLE_H (SMAP_EMAC3_REGBASE + 0x1A)
|
||||
#define SMAP_E3_INTR_OVERRUN (1<<25) /* this bit does NOT WORKED */
|
||||
#define SMAP_E3_INTR_PF (1<<24)
|
||||
#define SMAP_E3_INTR_BAD_FRAME (1<<23)
|
||||
#define SMAP_E3_INTR_RUNT_FRAME (1<<22)
|
||||
#define SMAP_E3_INTR_SHORT_EVENT (1<<21)
|
||||
#define SMAP_E3_INTR_ALIGN_ERR (1<<20)
|
||||
#define SMAP_E3_INTR_BAD_FCS (1<<19)
|
||||
#define SMAP_E3_INTR_TOO_LONG (1<<18)
|
||||
#define SMAP_E3_INTR_OUT_RANGE_ERR (1<<17)
|
||||
#define SMAP_E3_INTR_IN_RANGE_ERR (1<<16)
|
||||
#define SMAP_E3_INTR_DEAD_DEPEND (1<<9)
|
||||
#define SMAP_E3_INTR_DEAD_0 (1<<8)
|
||||
#define SMAP_E3_INTR_SQE_ERR_0 (1<<7)
|
||||
#define SMAP_E3_INTR_TX_ERR_0 (1<<6)
|
||||
#define SMAP_E3_INTR_DEAD_1 (1<<5)
|
||||
#define SMAP_E3_INTR_SQE_ERR_1 (1<<4)
|
||||
#define SMAP_E3_INTR_TX_ERR_1 (1<<3)
|
||||
#define SMAP_E3_INTR_MMAOP_SUCCESS (1<<1)
|
||||
#define SMAP_E3_INTR_MMAOP_FAIL (1<<0)
|
||||
#define SMAP_E3_INTR_ALL \
|
||||
(SMAP_E3_INTR_OVERRUN|SMAP_E3_INTR_PF|SMAP_E3_INTR_BAD_FRAME| \
|
||||
SMAP_E3_INTR_RUNT_FRAME|SMAP_E3_INTR_SHORT_EVENT| \
|
||||
SMAP_E3_INTR_ALIGN_ERR|SMAP_E3_INTR_BAD_FCS| \
|
||||
SMAP_E3_INTR_TOO_LONG|SMAP_E3_INTR_OUT_RANGE_ERR| \
|
||||
SMAP_E3_INTR_IN_RANGE_ERR| \
|
||||
SMAP_E3_INTR_DEAD_DEPEND|SMAP_E3_INTR_DEAD_0| \
|
||||
SMAP_E3_INTR_SQE_ERR_0|SMAP_E3_INTR_TX_ERR_0| \
|
||||
SMAP_E3_INTR_DEAD_1|SMAP_E3_INTR_SQE_ERR_1| \
|
||||
SMAP_E3_INTR_TX_ERR_1| \
|
||||
SMAP_E3_INTR_MMAOP_SUCCESS|SMAP_E3_INTR_MMAOP_FAIL)
|
||||
#define SMAP_E3_DEAD_ALL \
|
||||
(SMAP_E3_INTR_DEAD_DEPEND|SMAP_E3_INTR_DEAD_0| \
|
||||
SMAP_E3_INTR_DEAD_1)
|
||||
|
||||
#define SMAP_R_EMAC3_ADDR_HI (SMAP_EMAC3_REGBASE + 0x1C)
|
||||
#define SMAP_R_EMAC3_ADDR_LO (SMAP_EMAC3_REGBASE + 0x20)
|
||||
#define SMAP_R_EMAC3_ADDR_HI_L (SMAP_EMAC3_REGBASE + 0x1C)
|
||||
#define SMAP_R_EMAC3_ADDR_HI_H (SMAP_EMAC3_REGBASE + 0x1E)
|
||||
#define SMAP_R_EMAC3_ADDR_LO_L (SMAP_EMAC3_REGBASE + 0x20)
|
||||
#define SMAP_R_EMAC3_ADDR_LO_H (SMAP_EMAC3_REGBASE + 0x22)
|
||||
#define SMAP_R_EMAC3_ADDR_HI (SMAP_EMAC3_REGBASE + 0x1C)
|
||||
#define SMAP_R_EMAC3_ADDR_LO (SMAP_EMAC3_REGBASE + 0x20)
|
||||
#define SMAP_R_EMAC3_ADDR_HI_L (SMAP_EMAC3_REGBASE + 0x1C)
|
||||
#define SMAP_R_EMAC3_ADDR_HI_H (SMAP_EMAC3_REGBASE + 0x1E)
|
||||
#define SMAP_R_EMAC3_ADDR_LO_L (SMAP_EMAC3_REGBASE + 0x20)
|
||||
#define SMAP_R_EMAC3_ADDR_LO_H (SMAP_EMAC3_REGBASE + 0x22)
|
||||
|
||||
#define SMAP_R_EMAC3_VLAN_TPID (SMAP_EMAC3_REGBASE + 0x24)
|
||||
#define SMAP_E3_VLAN_ID_MSK 0xFFFF
|
||||
#define SMAP_R_EMAC3_VLAN_TPID (SMAP_EMAC3_REGBASE + 0x24)
|
||||
#define SMAP_E3_VLAN_ID_MSK 0xFFFF
|
||||
|
||||
#define SMAP_R_EMAC3_VLAN_TCI (SMAP_EMAC3_REGBASE + 0x28)
|
||||
#define SMAP_E3_VLAN_TCITAG_MSK 0xFFFF
|
||||
#define SMAP_R_EMAC3_VLAN_TCI (SMAP_EMAC3_REGBASE + 0x28)
|
||||
#define SMAP_E3_VLAN_TCITAG_MSK 0xFFFF
|
||||
|
||||
#define SMAP_R_EMAC3_PAUSE_TIMER (SMAP_EMAC3_REGBASE + 0x2C)
|
||||
#define SMAP_R_EMAC3_PAUSE_TIMER_L (SMAP_EMAC3_REGBASE + 0x2C)
|
||||
#define SMAP_R_EMAC3_PAUSE_TIMER_H (SMAP_EMAC3_REGBASE + 0x2E)
|
||||
#define SMAP_E3_PTIMER_MSK 0xFFFF
|
||||
#define SMAP_R_EMAC3_PAUSE_TIMER (SMAP_EMAC3_REGBASE + 0x2C)
|
||||
#define SMAP_R_EMAC3_PAUSE_TIMER_L (SMAP_EMAC3_REGBASE + 0x2C)
|
||||
#define SMAP_R_EMAC3_PAUSE_TIMER_H (SMAP_EMAC3_REGBASE + 0x2E)
|
||||
#define SMAP_E3_PTIMER_MSK 0xFFFF
|
||||
|
||||
#define SMAP_R_EMAC3_INDIVID_HASH1 (SMAP_EMAC3_REGBASE + 0x30)
|
||||
#define SMAP_R_EMAC3_INDIVID_HASH2 (SMAP_EMAC3_REGBASE + 0x34)
|
||||
#define SMAP_R_EMAC3_INDIVID_HASH3 (SMAP_EMAC3_REGBASE + 0x38)
|
||||
#define SMAP_R_EMAC3_INDIVID_HASH4 (SMAP_EMAC3_REGBASE + 0x3C)
|
||||
#define SMAP_R_EMAC3_GROUP_HASH1 (SMAP_EMAC3_REGBASE + 0x40)
|
||||
#define SMAP_R_EMAC3_GROUP_HASH2 (SMAP_EMAC3_REGBASE + 0x44)
|
||||
#define SMAP_R_EMAC3_GROUP_HASH3 (SMAP_EMAC3_REGBASE + 0x48)
|
||||
#define SMAP_R_EMAC3_GROUP_HASH4 (SMAP_EMAC3_REGBASE + 0x4C)
|
||||
#define SMAP_E3_HASH_MSK 0xFFFF
|
||||
#define SMAP_R_EMAC3_INDIVID_HASH1 (SMAP_EMAC3_REGBASE + 0x30)
|
||||
#define SMAP_R_EMAC3_INDIVID_HASH2 (SMAP_EMAC3_REGBASE + 0x34)
|
||||
#define SMAP_R_EMAC3_INDIVID_HASH3 (SMAP_EMAC3_REGBASE + 0x38)
|
||||
#define SMAP_R_EMAC3_INDIVID_HASH4 (SMAP_EMAC3_REGBASE + 0x3C)
|
||||
#define SMAP_R_EMAC3_GROUP_HASH1 (SMAP_EMAC3_REGBASE + 0x40)
|
||||
#define SMAP_R_EMAC3_GROUP_HASH2 (SMAP_EMAC3_REGBASE + 0x44)
|
||||
#define SMAP_R_EMAC3_GROUP_HASH3 (SMAP_EMAC3_REGBASE + 0x48)
|
||||
#define SMAP_R_EMAC3_GROUP_HASH4 (SMAP_EMAC3_REGBASE + 0x4C)
|
||||
#define SMAP_E3_HASH_MSK 0xFFFF
|
||||
|
||||
#define SMAP_R_EMAC3_LAST_SA_HI (SMAP_EMAC3_REGBASE + 0x50)
|
||||
#define SMAP_R_EMAC3_LAST_SA_LO (SMAP_EMAC3_REGBASE + 0x54)
|
||||
#define SMAP_R_EMAC3_LAST_SA_HI (SMAP_EMAC3_REGBASE + 0x50)
|
||||
#define SMAP_R_EMAC3_LAST_SA_LO (SMAP_EMAC3_REGBASE + 0x54)
|
||||
|
||||
#define SMAP_R_EMAC3_INTER_FRAME_GAP (SMAP_EMAC3_REGBASE + 0x58)
|
||||
#define SMAP_R_EMAC3_INTER_FRAME_GAP_L (SMAP_EMAC3_REGBASE + 0x58)
|
||||
#define SMAP_R_EMAC3_INTER_FRAME_GAP_H (SMAP_EMAC3_REGBASE + 0x5A)
|
||||
#define SMAP_E3_IFGAP_MSK 0x3F
|
||||
#define SMAP_R_EMAC3_INTER_FRAME_GAP (SMAP_EMAC3_REGBASE + 0x58)
|
||||
#define SMAP_R_EMAC3_INTER_FRAME_GAP_L (SMAP_EMAC3_REGBASE + 0x58)
|
||||
#define SMAP_R_EMAC3_INTER_FRAME_GAP_H (SMAP_EMAC3_REGBASE + 0x5A)
|
||||
#define SMAP_E3_IFGAP_MSK 0x3F
|
||||
|
||||
|
||||
#define SMAP_R_EMAC3_STA_CTRL_L (SMAP_EMAC3_REGBASE + 0x5C)
|
||||
#define SMAP_R_EMAC3_STA_CTRL_H (SMAP_EMAC3_REGBASE + 0x5E)
|
||||
#define SMAP_E3_PHY_DATA_MSK (0xFFFF)
|
||||
#define SMAP_E3_PHY_DATA_BITSFT (16)
|
||||
#define SMAP_E3_PHY_OP_COMP (1 << 15) /* operation complete */
|
||||
#define SMAP_E3_PHY_ERR_READ (1 << 14)
|
||||
#define SMAP_E3_PHY_STA_CMD_BITSFT (12)
|
||||
#define SMAP_E3_PHY_READ (1 << 12)
|
||||
#define SMAP_E3_PHY_WRITE (2 << 12)
|
||||
#define SMAP_E3_PHY_OPBCLCK_BITSFT (10)
|
||||
#define SMAP_E3_PHY_50M (0 << 10)
|
||||
#define SMAP_E3_PHY_66M (1 << 10)
|
||||
#define SMAP_E3_PHY_83M (2 << 10)
|
||||
#define SMAP_E3_PHY_100M (3 << 10)
|
||||
#define SMAP_E3_PHY_ADDR_MSK (0x1F)
|
||||
#define SMAP_E3_PHY_ADDR_BITSFT (5)
|
||||
#define SMAP_E3_PHY_REG_ADDR_MSK (0x1F)
|
||||
#define SMAP_R_EMAC3_STA_CTRL_L (SMAP_EMAC3_REGBASE + 0x5C)
|
||||
#define SMAP_R_EMAC3_STA_CTRL_H (SMAP_EMAC3_REGBASE + 0x5E)
|
||||
#define SMAP_E3_PHY_DATA_MSK (0xFFFF)
|
||||
#define SMAP_E3_PHY_DATA_BITSFT (16)
|
||||
#define SMAP_E3_PHY_OP_COMP (1<<15) /* operation complete */
|
||||
#define SMAP_E3_PHY_ERR_READ (1<<14)
|
||||
#define SMAP_E3_PHY_STA_CMD_BITSFT (12)
|
||||
#define SMAP_E3_PHY_READ (1<<12)
|
||||
#define SMAP_E3_PHY_WRITE (2<<12)
|
||||
#define SMAP_E3_PHY_OPBCLCK_BITSFT (10)
|
||||
#define SMAP_E3_PHY_50M (0<<10)
|
||||
#define SMAP_E3_PHY_66M (1<<10)
|
||||
#define SMAP_E3_PHY_83M (2<<10)
|
||||
#define SMAP_E3_PHY_100M (3<<10)
|
||||
#define SMAP_E3_PHY_ADDR_MSK (0x1F)
|
||||
#define SMAP_E3_PHY_ADDR_BITSFT (5)
|
||||
#define SMAP_E3_PHY_REG_ADDR_MSK (0x1F)
|
||||
|
||||
#define SMAP_R_EMAC3_TX_THRESHOLD (SMAP_EMAC3_REGBASE + 0x60)
|
||||
#define SMAP_R_EMAC3_TX_THRESHOLD_L (SMAP_EMAC3_REGBASE + 0x60)
|
||||
#define SMAP_R_EMAC3_TX_THRESHOLD_H (SMAP_EMAC3_REGBASE + 0x62)
|
||||
#define SMAP_E3_TX_THRESHLD_MSK (0x1F)
|
||||
#define SMAP_E3_TX_THRESHLD_BITSFT (27)
|
||||
#define SMAP_R_EMAC3_TX_THRESHOLD (SMAP_EMAC3_REGBASE + 0x60)
|
||||
#define SMAP_R_EMAC3_TX_THRESHOLD_L (SMAP_EMAC3_REGBASE + 0x60)
|
||||
#define SMAP_R_EMAC3_TX_THRESHOLD_H (SMAP_EMAC3_REGBASE + 0x62)
|
||||
#define SMAP_E3_TX_THRESHLD_MSK (0x1F)
|
||||
#define SMAP_E3_TX_THRESHLD_BITSFT (27)
|
||||
|
||||
#define SMAP_R_EMAC3_RX_WATERMARK (SMAP_EMAC3_REGBASE + 0x64)
|
||||
#define SMAP_R_EMAC3_RX_WATERMARK_L (SMAP_EMAC3_REGBASE + 0x64)
|
||||
#define SMAP_R_EMAC3_RX_WATERMARK_H (SMAP_EMAC3_REGBASE + 0x66)
|
||||
#define SMAP_E3_RX_LO_WATER_MSK (0x1FF)
|
||||
#define SMAP_E3_RX_LO_WATER_BITSFT (23)
|
||||
#define SMAP_E3_RX_HI_WATER_MSK (0x1FF)
|
||||
#define SMAP_E3_RX_HI_WATER_BITSFT (7)
|
||||
#define SMAP_R_EMAC3_RX_WATERMARK (SMAP_EMAC3_REGBASE + 0x64)
|
||||
#define SMAP_R_EMAC3_RX_WATERMARK_L (SMAP_EMAC3_REGBASE + 0x64)
|
||||
#define SMAP_R_EMAC3_RX_WATERMARK_H (SMAP_EMAC3_REGBASE + 0x66)
|
||||
#define SMAP_E3_RX_LO_WATER_MSK (0x1FF)
|
||||
#define SMAP_E3_RX_LO_WATER_BITSFT (23)
|
||||
#define SMAP_E3_RX_HI_WATER_MSK (0x1FF)
|
||||
#define SMAP_E3_RX_HI_WATER_BITSFT (7)
|
||||
|
||||
#define SMAP_R_EMAC3_TX_OCTETS (SMAP_EMAC3_REGBASE + 0x68)
|
||||
#define SMAP_R_EMAC3_RX_OCTETS (SMAP_EMAC3_REGBASE + 0x6C)
|
||||
#define SMAP_EMAC3_REGEND (SMAP_EMAC3_REGBASE + 0x6C + 4)
|
||||
#define SMAP_R_EMAC3_TX_OCTETS (SMAP_EMAC3_REGBASE + 0x68)
|
||||
#define SMAP_R_EMAC3_RX_OCTETS (SMAP_EMAC3_REGBASE + 0x6C)
|
||||
#define SMAP_EMAC3_REGEND (SMAP_EMAC3_REGBASE + 0x6C + 4)
|
||||
|
||||
/* Buffer descriptors. */
|
||||
|
||||
typedef struct _smap_bd
|
||||
{
|
||||
u16 ctrl_stat;
|
||||
u16 reserved; /* must be zero */
|
||||
u16 length; /* number of bytes in pkt */
|
||||
u16 pointer;
|
||||
typedef struct _smap_bd {
|
||||
u16 ctrl_stat;
|
||||
u16 reserved; /* must be zero */
|
||||
u16 length; /* number of bytes in pkt */
|
||||
u16 pointer;
|
||||
} smap_bd_t;
|
||||
|
||||
#define SMAP_BD_REGBASE (SMAP_REGBASE + 0x2f00)
|
||||
#define SMAP_BD_TX_BASE (SMAP_BD_REGBASE + 0x0000)
|
||||
#define SMAP_BD_RX_BASE (SMAP_BD_REGBASE + 0x0200)
|
||||
#define SMAP_BD_SIZE 512
|
||||
#define SMAP_BD_MAX_ENTRY 64
|
||||
#define SMAP_BD_REGBASE (SMAP_REGBASE + 0x2f00)
|
||||
#define SMAP_BD_TX_BASE (SMAP_BD_REGBASE + 0x0000)
|
||||
#define SMAP_BD_RX_BASE (SMAP_BD_REGBASE + 0x0200)
|
||||
#define SMAP_BD_SIZE 512
|
||||
#define SMAP_BD_MAX_ENTRY 64
|
||||
|
||||
#define SMAP_TX_BASE (SMAP_REGBASE + 0x1000)
|
||||
#define SMAP_TX_BUFSIZE 4096
|
||||
#define SMAP_TX_BASE (SMAP_REGBASE + 0x1000)
|
||||
#define SMAP_TX_BUFSIZE 4096
|
||||
|
||||
/* TX Control */
|
||||
#define SMAP_BD_TX_READY (1 << 15) /* set:driver, clear:HW */
|
||||
#define SMAP_BD_TX_GENFCS (1 << 9) /* generate FCS */
|
||||
#define SMAP_BD_TX_GENPAD (1 << 8) /* generate padding */
|
||||
#define SMAP_BD_TX_INSSA (1 << 7) /* insert source address */
|
||||
#define SMAP_BD_TX_RPLSA (1 << 6) /* replace source address */
|
||||
#define SMAP_BD_TX_INSVLAN (1 << 5) /* insert VLAN Tag */
|
||||
#define SMAP_BD_TX_RPLVLAN (1 << 4) /* replace VLAN Tag */
|
||||
#define SMAP_BD_TX_READY (1<<15) /* set:driver, clear:HW */
|
||||
#define SMAP_BD_TX_GENFCS (1<<9) /* generate FCS */
|
||||
#define SMAP_BD_TX_GENPAD (1<<8) /* generate padding */
|
||||
#define SMAP_BD_TX_INSSA (1<<7) /* insert source address */
|
||||
#define SMAP_BD_TX_RPLSA (1<<6) /* replace source address */
|
||||
#define SMAP_BD_TX_INSVLAN (1<<5) /* insert VLAN Tag */
|
||||
#define SMAP_BD_TX_RPLVLAN (1<<4) /* replace VLAN Tag */
|
||||
|
||||
/* TX Status */
|
||||
#define SMAP_BD_TX_READY (1 << 15) /* set:driver, clear:HW */
|
||||
#define SMAP_BD_TX_BADFCS (1 << 9) /* bad FCS */
|
||||
#define SMAP_BD_TX_BADPKT (1 << 8) /* bad previous pkt in dependent mode */
|
||||
#define SMAP_BD_TX_LOSSCR (1 << 7) /* loss of carrior sense */
|
||||
#define SMAP_BD_TX_EDEFER (1 << 6) /* excessive deferal */
|
||||
#define SMAP_BD_TX_ECOLL (1 << 5) /* excessive collision */
|
||||
#define SMAP_BD_TX_LCOLL (1 << 4) /* late collision */
|
||||
#define SMAP_BD_TX_MCOLL (1 << 3) /* multiple collision */
|
||||
#define SMAP_BD_TX_SCOLL (1 << 2) /* single collision */
|
||||
#define SMAP_BD_TX_UNDERRUN (1 << 1) /* underrun */
|
||||
#define SMAP_BD_TX_SQE (1 << 0) /* SQE */
|
||||
#define SMAP_BD_TX_READY (1<<15) /* set:driver, clear:HW */
|
||||
#define SMAP_BD_TX_BADFCS (1<<9) /* bad FCS */
|
||||
#define SMAP_BD_TX_BADPKT (1<<8) /* bad previous pkt in dependent mode */
|
||||
#define SMAP_BD_TX_LOSSCR (1<<7) /* loss of carrior sense */
|
||||
#define SMAP_BD_TX_EDEFER (1<<6) /* excessive deferal */
|
||||
#define SMAP_BD_TX_ECOLL (1<<5) /* excessive collision */
|
||||
#define SMAP_BD_TX_LCOLL (1<<4) /* late collision */
|
||||
#define SMAP_BD_TX_MCOLL (1<<3) /* multiple collision */
|
||||
#define SMAP_BD_TX_SCOLL (1<<2) /* single collision */
|
||||
#define SMAP_BD_TX_UNDERRUN (1<<1) /* underrun */
|
||||
#define SMAP_BD_TX_SQE (1<<0) /* SQE */
|
||||
|
||||
#define SMAP_BD_TX_ERROR (SMAP_BD_TX_LOSSCR | SMAP_BD_TX_EDEFER | SMAP_BD_TX_ECOLL | \
|
||||
SMAP_BD_TX_LCOLL | SMAP_BD_TX_UNDERRUN)
|
||||
#define SMAP_BD_TX_ERROR (SMAP_BD_TX_LOSSCR|SMAP_BD_TX_EDEFER|SMAP_BD_TX_ECOLL| \
|
||||
SMAP_BD_TX_LCOLL|SMAP_BD_TX_UNDERRUN)
|
||||
|
||||
/* RX Control */
|
||||
#define SMAP_BD_RX_EMPTY (1 << 15) /* set:driver, clear:HW */
|
||||
#define SMAP_BD_RX_EMPTY (1<<15) /* set:driver, clear:HW */
|
||||
|
||||
/* RX Status */
|
||||
#define SMAP_BD_RX_EMPTY (1 << 15) /* set:driver, clear:HW */
|
||||
#define SMAP_BD_RX_OVERRUN (1 << 9) /* overrun */
|
||||
#define SMAP_BD_RX_PFRM (1 << 8) /* pause frame */
|
||||
#define SMAP_BD_RX_BADFRM (1 << 7) /* bad frame */
|
||||
#define SMAP_BD_RX_RUNTFRM (1 << 6) /* runt frame */
|
||||
#define SMAP_BD_RX_SHORTEVNT (1 << 5) /* short event */
|
||||
#define SMAP_BD_RX_ALIGNERR (1 << 4) /* alignment error */
|
||||
#define SMAP_BD_RX_BADFCS (1 << 3) /* bad FCS */
|
||||
#define SMAP_BD_RX_FRMTOOLONG (1 << 2) /* frame too long */
|
||||
#define SMAP_BD_RX_OUTRANGE (1 << 1) /* out of range error */
|
||||
#define SMAP_BD_RX_INRANGE (1 << 0) /* in range error */
|
||||
#define SMAP_BD_RX_EMPTY (1<<15) /* set:driver, clear:HW */
|
||||
#define SMAP_BD_RX_OVERRUN (1<<9) /* overrun */
|
||||
#define SMAP_BD_RX_PFRM (1<<8) /* pause frame */
|
||||
#define SMAP_BD_RX_BADFRM (1<<7) /* bad frame */
|
||||
#define SMAP_BD_RX_RUNTFRM (1<<6) /* runt frame */
|
||||
#define SMAP_BD_RX_SHORTEVNT (1<<5) /* short event */
|
||||
#define SMAP_BD_RX_ALIGNERR (1<<4) /* alignment error */
|
||||
#define SMAP_BD_RX_BADFCS (1<<3) /* bad FCS */
|
||||
#define SMAP_BD_RX_FRMTOOLONG (1<<2) /* frame too long */
|
||||
#define SMAP_BD_RX_OUTRANGE (1<<1) /* out of range error */
|
||||
#define SMAP_BD_RX_INRANGE (1<<0) /* in range error */
|
||||
|
||||
#define SMAP_BD_RX_ERROR (SMAP_BD_RX_OVERRUN | SMAP_BD_RX_RUNTFRM | SMAP_BD_RX_SHORTEVNT | \
|
||||
SMAP_BD_RX_ALIGNERR | SMAP_BD_RX_BADFCS | SMAP_BD_RX_FRMTOOLONG | \
|
||||
SMAP_BD_RX_OUTRANGE | SMAP_BD_RX_INRANGE)
|
||||
#define SMAP_BD_RX_ERROR (SMAP_BD_RX_OVERRUN|SMAP_BD_RX_RUNTFRM|SMAP_BD_RX_SHORTEVNT| \
|
||||
SMAP_BD_RX_ALIGNERR|SMAP_BD_RX_BADFCS|SMAP_BD_RX_FRMTOOLONG| \
|
||||
SMAP_BD_RX_OUTRANGE|SMAP_BD_RX_INRANGE)
|
||||
|
||||
/* PHY registers (National Semiconductor DP83846A). */
|
||||
|
||||
#define SMAP_NS_OUI 0x080017
|
||||
#define SMAP_DsPHYTER_ADDRESS 0x1
|
||||
#define SMAP_NS_OUI 0x080017
|
||||
#define SMAP_DsPHYTER_ADDRESS 0x1
|
||||
|
||||
#define SMAP_DsPHYTER_BMCR 0x00
|
||||
#define SMAP_PHY_BMCR_RST (1 << 15) /* ReSeT */
|
||||
#define SMAP_PHY_BMCR_LPBK (1 << 14) /* LooPBacK */
|
||||
#define SMAP_PHY_BMCR_100M (1 << 13) /* speed select, 1:100M, 0:10M */
|
||||
#define SMAP_PHY_BMCR_10M (0 << 13) /* speed select, 1:100M, 0:10M */
|
||||
#define SMAP_PHY_BMCR_ANEN (1 << 12) /* Auto-Negotiation ENable */
|
||||
#define SMAP_PHY_BMCR_PWDN (1 << 11) /* PoWer DowN */
|
||||
#define SMAP_PHY_BMCR_ISOL (1 << 10) /* ISOLate */
|
||||
#define SMAP_PHY_BMCR_RSAN (1 << 9) /* ReStart Auto-Negotiation */
|
||||
#define SMAP_PHY_BMCR_DUPM (1 << 8) /* DUPlex Mode, 1:FDX, 0:HDX */
|
||||
#define SMAP_PHY_BMCR_COLT (1 << 7) /* COLlision Test */
|
||||
#define SMAP_DsPHYTER_BMCR 0x00
|
||||
#define SMAP_PHY_BMCR_RST (1<<15) /* ReSeT */
|
||||
#define SMAP_PHY_BMCR_LPBK (1<<14) /* LooPBacK */
|
||||
#define SMAP_PHY_BMCR_100M (1<<13) /* speed select, 1:100M, 0:10M */
|
||||
#define SMAP_PHY_BMCR_10M (0<<13) /* speed select, 1:100M, 0:10M */
|
||||
#define SMAP_PHY_BMCR_ANEN (1<<12) /* Auto-Negotiation ENable */
|
||||
#define SMAP_PHY_BMCR_PWDN (1<<11) /* PoWer DowN */
|
||||
#define SMAP_PHY_BMCR_ISOL (1<<10) /* ISOLate */
|
||||
#define SMAP_PHY_BMCR_RSAN (1<<9) /* ReStart Auto-Negotiation */
|
||||
#define SMAP_PHY_BMCR_DUPM (1<<8) /* DUPlex Mode, 1:FDX, 0:HDX */
|
||||
#define SMAP_PHY_BMCR_COLT (1<<7) /* COLlision Test */
|
||||
|
||||
#define SMAP_DsPHYTER_BMSR 0x01
|
||||
#define SMAP_PHY_BMSR_ANCP (1 << 5) /* Auto-Negotiation ComPlete */
|
||||
#define SMAP_PHY_BMSR_LINK (1 << 2) /* LINK status */
|
||||
#define SMAP_DsPHYTER_BMSR 0x01
|
||||
#define SMAP_PHY_BMSR_ANCP (1<<5) /* Auto-Negotiation ComPlete */
|
||||
#define SMAP_PHY_BMSR_LINK (1<<2) /* LINK status */
|
||||
|
||||
#define SMAP_DsPHYTER_PHYIDR1 0x02
|
||||
#define SMAP_PHY_IDR1_VAL (((SMAP_NS_OUI << 2) >> 8) & 0xffff)
|
||||
#define SMAP_DsPHYTER_PHYIDR1 0x02
|
||||
#define SMAP_PHY_IDR1_VAL (((SMAP_NS_OUI<<2)>>8)&0xffff)
|
||||
|
||||
#define SMAP_DsPHYTER_PHYIDR2 0x03
|
||||
#define SMAP_PHY_IDR2_VMDL 0x2 /* Vendor MoDeL number */
|
||||
#define SMAP_PHY_IDR2_VAL \
|
||||
(((SMAP_NS_OUI << 10) & 0xFC00) | ((SMAP_PHY_IDR2_VMDL << 4) & 0x3F0))
|
||||
#define SMAP_PHY_IDR2_MSK 0xFFF0
|
||||
#define SMAP_PHY_IDR2_REV_MSK 0x000F
|
||||
#define SMAP_DsPHYTER_PHYIDR2 0x03
|
||||
#define SMAP_PHY_IDR2_VMDL 0x2 /* Vendor MoDeL number */
|
||||
#define SMAP_PHY_IDR2_VAL \
|
||||
(((SMAP_NS_OUI<<10)&0xFC00)|((SMAP_PHY_IDR2_VMDL<<4)&0x3F0))
|
||||
#define SMAP_PHY_IDR2_MSK 0xFFF0
|
||||
#define SMAP_PHY_IDR2_REV_MSK 0x000F
|
||||
|
||||
#define SMAP_DsPHYTER_ANAR 0x04
|
||||
#define SMAP_DsPHYTER_ANLPAR 0x05
|
||||
#define SMAP_DsPHYTER_ANLPARNP 0x05
|
||||
#define SMAP_DsPHYTER_ANER 0x06
|
||||
#define SMAP_DsPHYTER_ANNPTR 0x07
|
||||
#define SMAP_DsPHYTER_ANAR 0x04
|
||||
#define SMAP_DsPHYTER_ANLPAR 0x05
|
||||
#define SMAP_DsPHYTER_ANLPARNP 0x05
|
||||
#define SMAP_DsPHYTER_ANER 0x06
|
||||
#define SMAP_DsPHYTER_ANNPTR 0x07
|
||||
|
||||
/* Extended registers. */
|
||||
#define SMAP_DsPHYTER_PHYSTS 0x10
|
||||
#define SMAP_PHY_STS_REL (1 << 13) /* Receive Error Latch */
|
||||
#define SMAP_PHY_STS_POST (1 << 12) /* POlarity STatus */
|
||||
#define SMAP_PHY_STS_FCSL (1 << 11) /* False Carrier Sense Latch */
|
||||
#define SMAP_PHY_STS_SD (1 << 10) /* 100BT unconditional Signal Detect */
|
||||
#define SMAP_PHY_STS_DSL (1 << 9) /* 100BT DeScrambler Lock */
|
||||
#define SMAP_PHY_STS_PRCV (1 << 8) /* Page ReCeiVed */
|
||||
#define SMAP_PHY_STS_RFLT (1 << 6) /* Remote FauLT */
|
||||
#define SMAP_PHY_STS_JBDT (1 << 5) /* JaBber DetecT */
|
||||
#define SMAP_PHY_STS_ANCP (1 << 4) /* Auto-Negotiation ComPlete */
|
||||
#define SMAP_PHY_STS_LPBK (1 << 3) /* LooPBacK status */
|
||||
#define SMAP_PHY_STS_DUPS (1 << 2) /* DUPlex Status,1:FDX,0:HDX */
|
||||
#define SMAP_PHY_STS_FDX (1 << 2) /* Full Duplex */
|
||||
#define SMAP_PHY_STS_HDX (0 << 2) /* Half Duplex */
|
||||
#define SMAP_PHY_STS_SPDS (1 << 1) /* SPeeD Status */
|
||||
#define SMAP_PHY_STS_10M (1 << 1) /* 10Mbps */
|
||||
#define SMAP_PHY_STS_100M (0 << 1) /* 100Mbps */
|
||||
#define SMAP_PHY_STS_LINK (1 << 0) /* LINK status */
|
||||
#define SMAP_DsPHYTER_FCSCR 0x14
|
||||
#define SMAP_DsPHYTER_RECR 0x15
|
||||
#define SMAP_DsPHYTER_PCSR 0x16
|
||||
#define SMAP_DsPHYTER_PHYCTRL 0x19
|
||||
#define SMAP_DsPHYTER_10BTSCR 0x1A
|
||||
#define SMAP_DsPHYTER_CDCTRL 0x1B
|
||||
#define SMAP_DsPHYTER_PHYSTS 0x10
|
||||
#define SMAP_PHY_STS_REL (1<<13) /* Receive Error Latch */
|
||||
#define SMAP_PHY_STS_POST (1<<12) /* POlarity STatus */
|
||||
#define SMAP_PHY_STS_FCSL (1<<11) /* False Carrier Sense Latch */
|
||||
#define SMAP_PHY_STS_SD (1<<10) /* 100BT unconditional Signal Detect */
|
||||
#define SMAP_PHY_STS_DSL (1<<9) /* 100BT DeScrambler Lock */
|
||||
#define SMAP_PHY_STS_PRCV (1<<8) /* Page ReCeiVed */
|
||||
#define SMAP_PHY_STS_RFLT (1<<6) /* Remote FauLT */
|
||||
#define SMAP_PHY_STS_JBDT (1<<5) /* JaBber DetecT */
|
||||
#define SMAP_PHY_STS_ANCP (1<<4) /* Auto-Negotiation ComPlete */
|
||||
#define SMAP_PHY_STS_LPBK (1<<3) /* LooPBacK status */
|
||||
#define SMAP_PHY_STS_DUPS (1<<2) /* DUPlex Status,1:FDX,0:HDX */
|
||||
#define SMAP_PHY_STS_FDX (1<<2) /* Full Duplex */
|
||||
#define SMAP_PHY_STS_HDX (0<<2) /* Half Duplex */
|
||||
#define SMAP_PHY_STS_SPDS (1<<1) /* SPeeD Status */
|
||||
#define SMAP_PHY_STS_10M (1<<1) /* 10Mbps */
|
||||
#define SMAP_PHY_STS_100M (0<<1) /* 100Mbps */
|
||||
#define SMAP_PHY_STS_LINK (1<<0) /* LINK status */
|
||||
#define SMAP_DsPHYTER_FCSCR 0x14
|
||||
#define SMAP_DsPHYTER_RECR 0x15
|
||||
#define SMAP_DsPHYTER_PCSR 0x16
|
||||
#define SMAP_DsPHYTER_PHYCTRL 0x19
|
||||
#define SMAP_DsPHYTER_10BTSCR 0x1A
|
||||
#define SMAP_DsPHYTER_CDCTRL 0x1B
|
||||
|
||||
// clang-format on
|
||||
|
||||
/*
|
||||
* ATA hardware types and definitions.
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/* PCSX2 - PS2 Emulator for PCs
|
||||
* Copyright (C) 2002-2010 PCSX2 Dev Team
|
||||
* Copyright (C) 2002-2020 PCSX2 Dev Team
|
||||
*
|
||||
* PCSX2 is free software: you can redistribute it and/or modify it under the terms
|
||||
* of the GNU Lesser General Public License as published by the Free Software Found-
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/* PCSX2 - PS2 Emulator for PCs
|
||||
* Copyright (C) 2002-2010 PCSX2 Dev Team
|
||||
* Copyright (C) 2002-2020 PCSX2 Dev Team
|
||||
*
|
||||
* PCSX2 is free software: you can redistribute it and/or modify it under the terms
|
||||
* of the GNU Lesser General Public License as published by the Free Software Found-
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/* PCSX2 - PS2 Emulator for PCs
|
||||
* Copyright (C) 2002-2010 PCSX2 Dev Team
|
||||
* Copyright (C) 2002-2020 PCSX2 Dev Team
|
||||
*
|
||||
* PCSX2 is free software: you can redistribute it and/or modify it under the terms
|
||||
* of the GNU Lesser General Public License as published by the Free Software Found-
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/* PCSX2 - PS2 Emulator for PCs
|
||||
* Copyright (C) 2002-2010 PCSX2 Dev Team
|
||||
* Copyright (C) 2002-2020 PCSX2 Dev Team
|
||||
*
|
||||
* PCSX2 is free software: you can redistribute it and/or modify it under the terms
|
||||
* of the GNU Lesser General Public License as published by the Free Software Found-
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/* PCSX2 - PS2 Emulator for PCs
|
||||
* Copyright (C) 2002-2010 PCSX2 Dev Team
|
||||
* Copyright (C) 2002-2020 PCSX2 Dev Team
|
||||
*
|
||||
* PCSX2 is free software: you can redistribute it and/or modify it under the terms
|
||||
* of the GNU Lesser General Public License as published by the Free Software Found-
|
||||
|
|
@ -63,9 +63,11 @@ void OnInitDialog(HWND hW)
|
|||
vector<tap_adapter>* al = GetTapAdapters();
|
||||
for (size_t i = 0; i < al->size(); i++)
|
||||
{
|
||||
int itm = SendMessageA(GetDlgItem(hW, IDC_ETHDEV), CB_ADDSTRING, NULL, (LPARAM)(LPCTSTR)al[0][i].name.c_str());
|
||||
ComboBox_SetItemData(GetDlgItem(hW, IDC_ETHDEV), itm, _strdup(al[0][i].guid.c_str()));
|
||||
if (strcmp(al[0][i].guid.c_str(), config.Eth) == 0)
|
||||
int itm = ComboBox_AddString(GetDlgItem(hW, IDC_ETHDEV), al[0][i].name);
|
||||
char guid_char[256];
|
||||
wcstombs(guid_char, al[0][i].guid, wcslen(al[0][i].guid) + 1);
|
||||
ComboBox_SetItemData(GetDlgItem(hW, IDC_ETHDEV), itm, _strdup(guid_char));
|
||||
if (strcmp(guid_char, config.Eth) == 0)
|
||||
{
|
||||
ComboBox_SetCurSel(GetDlgItem(hW, IDC_ETHDEV), itm);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/* PCSX2 - PS2 Emulator for PCs
|
||||
* Copyright (C) 2002-2010 PCSX2 Dev Team
|
||||
* Copyright (C) 2002-2020 PCSX2 Dev Team
|
||||
*
|
||||
* PCSX2 is free software: you can redistribute it and/or modify it under the terms
|
||||
* of the GNU Lesser General Public License as published by the Free Software Found-
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/* PCSX2 - PS2 Emulator for PCs
|
||||
* Copyright (C) 2002-2010 PCSX2 Dev Team
|
||||
* Copyright (C) 2002-2020 PCSX2 Dev Team
|
||||
*
|
||||
* PCSX2 is free software: you can redistribute it and/or modify it under the terms
|
||||
* of the GNU Lesser General Public License as published by the Free Software Found-
|
||||
|
|
@ -29,15 +29,17 @@
|
|||
#define TAP_CONTROL_CODE(request, method) \
|
||||
CTL_CODE(FILE_DEVICE_UNKNOWN, request, method, FILE_ANY_ACCESS)
|
||||
|
||||
#define TAP_IOCTL_GET_MAC TAP_CONTROL_CODE(1, METHOD_BUFFERED)
|
||||
#define TAP_IOCTL_GET_VERSION TAP_CONTROL_CODE(2, METHOD_BUFFERED)
|
||||
#define TAP_IOCTL_GET_MTU TAP_CONTROL_CODE(3, METHOD_BUFFERED)
|
||||
#define TAP_IOCTL_GET_INFO TAP_CONTROL_CODE(4, METHOD_BUFFERED)
|
||||
// clang-format off
|
||||
#define TAP_IOCTL_GET_MAC TAP_CONTROL_CODE(1, METHOD_BUFFERED)
|
||||
#define TAP_IOCTL_GET_VERSION TAP_CONTROL_CODE(2, METHOD_BUFFERED)
|
||||
#define TAP_IOCTL_GET_MTU TAP_CONTROL_CODE(3, METHOD_BUFFERED)
|
||||
#define TAP_IOCTL_GET_INFO TAP_CONTROL_CODE(4, METHOD_BUFFERED)
|
||||
#define TAP_IOCTL_CONFIG_POINT_TO_POINT TAP_CONTROL_CODE(5, METHOD_BUFFERED)
|
||||
#define TAP_IOCTL_SET_MEDIA_STATUS TAP_CONTROL_CODE(6, METHOD_BUFFERED)
|
||||
#define TAP_IOCTL_CONFIG_DHCP_MASQ TAP_CONTROL_CODE(7, METHOD_BUFFERED)
|
||||
#define TAP_IOCTL_GET_LOG_LINE TAP_CONTROL_CODE(8, METHOD_BUFFERED)
|
||||
#define TAP_IOCTL_CONFIG_DHCP_SET_OPT TAP_CONTROL_CODE(9, METHOD_BUFFERED)
|
||||
#define TAP_IOCTL_SET_MEDIA_STATUS TAP_CONTROL_CODE(6, METHOD_BUFFERED)
|
||||
#define TAP_IOCTL_CONFIG_DHCP_MASQ TAP_CONTROL_CODE(7, METHOD_BUFFERED)
|
||||
#define TAP_IOCTL_GET_LOG_LINE TAP_CONTROL_CODE(8, METHOD_BUFFERED)
|
||||
#define TAP_IOCTL_CONFIG_DHCP_SET_OPT TAP_CONTROL_CODE(9, METHOD_BUFFERED)
|
||||
// clang-format on
|
||||
|
||||
//=================
|
||||
// Registry keys
|
||||
|
|
@ -181,11 +183,7 @@ vector<tap_adapter>* GetTapAdapters()
|
|||
{
|
||||
if (IsTAPDevice(enum_name))
|
||||
{
|
||||
std::wstring tmp(name_data);
|
||||
std::wstring tmp2(enum_name);
|
||||
std::string tmp3(tmp.begin(), tmp.end());
|
||||
std::string tmp4(tmp2.begin(), tmp2.end());
|
||||
tap_adapter t = {tmp3, tmp4};
|
||||
tap_adapter t = {_tcsdup(name_data), _tcsdup(enum_name)};
|
||||
tap_nic->push_back(t);
|
||||
}
|
||||
}
|
||||
|
|
@ -380,605 +378,4 @@ TAPAdapter::~TAPAdapter()
|
|||
TAPSetStatus(htap, FALSE);
|
||||
CloseHandle(htap);
|
||||
isActive = false;
|
||||
}
|
||||
|
||||
//i leave these for reference, in case we need msth :p
|
||||
#if 0 == 666
|
||||
//======================
|
||||
// Compile time configuration
|
||||
//======================
|
||||
|
||||
//#define DEBUG_TAP_WIN32 1
|
||||
|
||||
#define TUN_ASYNCHRONOUS_WRITES 1
|
||||
|
||||
#define TUN_BUFFER_SIZE 1560
|
||||
#define TUN_MAX_BUFFER_COUNT 32
|
||||
|
||||
/*
|
||||
* The data member "buffer" must be the first element in the tun_buffer
|
||||
* structure. See the function, tap_win32_free_buffer.
|
||||
*/
|
||||
typedef struct tun_buffer_s {
|
||||
unsigned char buffer [TUN_BUFFER_SIZE];
|
||||
unsigned long read_size;
|
||||
struct tun_buffer_s* next;
|
||||
} tun_buffer_t;
|
||||
|
||||
typedef struct tap_win32_overlapped {
|
||||
HANDLE handle;
|
||||
HANDLE read_event;
|
||||
HANDLE write_event;
|
||||
HANDLE output_queue_semaphore;
|
||||
HANDLE free_list_semaphore;
|
||||
HANDLE tap_semaphore;
|
||||
CRITICAL_SECTION output_queue_cs;
|
||||
CRITICAL_SECTION free_list_cs;
|
||||
OVERLAPPED read_overlapped;
|
||||
OVERLAPPED write_overlapped;
|
||||
tun_buffer_t buffers[TUN_MAX_BUFFER_COUNT];
|
||||
tun_buffer_t* free_list;
|
||||
tun_buffer_t* output_queue_front;
|
||||
tun_buffer_t* output_queue_back;
|
||||
} tap_win32_overlapped_t;
|
||||
|
||||
static tap_win32_overlapped_t tap_overlapped;
|
||||
|
||||
static tun_buffer_t* get_buffer_from_free_list(tap_win32_overlapped_t* const overlapped)
|
||||
{
|
||||
tun_buffer_t* buffer = NULL;
|
||||
WaitForSingleObject(overlapped->free_list_semaphore, INFINITE);
|
||||
EnterCriticalSection(&overlapped->free_list_cs);
|
||||
buffer = overlapped->free_list;
|
||||
// assert(buffer != NULL);
|
||||
overlapped->free_list = buffer->next;
|
||||
LeaveCriticalSection(&overlapped->free_list_cs);
|
||||
buffer->next = NULL;
|
||||
return buffer;
|
||||
}
|
||||
|
||||
static void put_buffer_on_free_list(tap_win32_overlapped_t* const overlapped, tun_buffer_t* const buffer)
|
||||
{
|
||||
EnterCriticalSection(&overlapped->free_list_cs);
|
||||
buffer->next = overlapped->free_list;
|
||||
overlapped->free_list = buffer;
|
||||
LeaveCriticalSection(&overlapped->free_list_cs);
|
||||
ReleaseSemaphore(overlapped->free_list_semaphore, 1, NULL);
|
||||
}
|
||||
|
||||
static tun_buffer_t* get_buffer_from_output_queue(tap_win32_overlapped_t* const overlapped, const int block)
|
||||
{
|
||||
tun_buffer_t* buffer = NULL;
|
||||
DWORD result, timeout = block ? INFINITE : 0L;
|
||||
|
||||
// Non-blocking call
|
||||
result = WaitForSingleObject(overlapped->output_queue_semaphore, timeout);
|
||||
|
||||
switch (result)
|
||||
{
|
||||
// The semaphore object was signaled.
|
||||
case WAIT_OBJECT_0:
|
||||
EnterCriticalSection(&overlapped->output_queue_cs);
|
||||
|
||||
buffer = overlapped->output_queue_front;
|
||||
overlapped->output_queue_front = buffer->next;
|
||||
|
||||
if(overlapped->output_queue_front == NULL) {
|
||||
overlapped->output_queue_back = NULL;
|
||||
}
|
||||
|
||||
LeaveCriticalSection(&overlapped->output_queue_cs);
|
||||
break;
|
||||
|
||||
// Semaphore was nonsignaled, so a time-out occurred.
|
||||
case WAIT_TIMEOUT:
|
||||
// Cannot open another window.
|
||||
break;
|
||||
}
|
||||
|
||||
return buffer;
|
||||
}
|
||||
|
||||
static tun_buffer_t* get_buffer_from_output_queue_immediate (tap_win32_overlapped_t* const overlapped)
|
||||
{
|
||||
return get_buffer_from_output_queue(overlapped, 0);
|
||||
}
|
||||
|
||||
static void put_buffer_on_output_queue(tap_win32_overlapped_t* const overlapped, tun_buffer_t* const buffer)
|
||||
{
|
||||
EnterCriticalSection(&overlapped->output_queue_cs);
|
||||
|
||||
if(overlapped->output_queue_front == NULL && overlapped->output_queue_back == NULL) {
|
||||
overlapped->output_queue_front = overlapped->output_queue_back = buffer;
|
||||
} else {
|
||||
buffer->next = NULL;
|
||||
overlapped->output_queue_back->next = buffer;
|
||||
overlapped->output_queue_back = buffer;
|
||||
}
|
||||
|
||||
LeaveCriticalSection(&overlapped->output_queue_cs);
|
||||
|
||||
ReleaseSemaphore(overlapped->output_queue_semaphore, 1, NULL);
|
||||
}
|
||||
|
||||
|
||||
static int is_tap_win32_dev(const char *guid)
|
||||
{
|
||||
HKEY netcard_key;
|
||||
LONG status;
|
||||
DWORD len;
|
||||
int i = 0;
|
||||
|
||||
status = RegOpenKeyEx(
|
||||
HKEY_LOCAL_MACHINE,
|
||||
ADAPTER_KEY,
|
||||
0,
|
||||
KEY_READ,
|
||||
&netcard_key);
|
||||
|
||||
if (status != ERROR_SUCCESS) {
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
for (;;) {
|
||||
char enum_name[256];
|
||||
char unit_string[256];
|
||||
HKEY unit_key;
|
||||
char component_id_string[] = "ComponentId";
|
||||
char component_id[256];
|
||||
char net_cfg_instance_id_string[] = "NetCfgInstanceId";
|
||||
char net_cfg_instance_id[256];
|
||||
DWORD data_type;
|
||||
|
||||
len = sizeof (enum_name);
|
||||
status = RegEnumKeyEx(
|
||||
netcard_key,
|
||||
i,
|
||||
enum_name,
|
||||
&len,
|
||||
NULL,
|
||||
NULL,
|
||||
NULL,
|
||||
NULL);
|
||||
|
||||
if (status == ERROR_NO_MORE_ITEMS)
|
||||
break;
|
||||
else if (status != ERROR_SUCCESS) {
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
_snprintf(unit_string, sizeof(unit_string), "%s\\%s",
|
||||
ADAPTER_KEY, enum_name);
|
||||
|
||||
status = RegOpenKeyEx(
|
||||
HKEY_LOCAL_MACHINE,
|
||||
unit_string,
|
||||
0,
|
||||
KEY_READ,
|
||||
&unit_key);
|
||||
|
||||
if (status != ERROR_SUCCESS) {
|
||||
return FALSE;
|
||||
} else {
|
||||
len = sizeof (component_id);
|
||||
status = RegQueryValueEx(
|
||||
unit_key,
|
||||
component_id_string,
|
||||
NULL,
|
||||
&data_type,
|
||||
(LPBYTE)component_id,
|
||||
&len);
|
||||
|
||||
if (!(status != ERROR_SUCCESS || data_type != REG_SZ)) {
|
||||
len = sizeof (net_cfg_instance_id);
|
||||
status = RegQueryValueEx(
|
||||
unit_key,
|
||||
net_cfg_instance_id_string,
|
||||
NULL,
|
||||
&data_type,
|
||||
(LPBYTE)net_cfg_instance_id,
|
||||
&len);
|
||||
|
||||
if (status == ERROR_SUCCESS && data_type == REG_SZ) {
|
||||
if (/* !strcmp (component_id, TAP_COMPONENT_ID) &&*/
|
||||
!strcmp (net_cfg_instance_id, guid)) {
|
||||
RegCloseKey (unit_key);
|
||||
RegCloseKey (netcard_key);
|
||||
return TRUE;
|
||||
}
|
||||
}
|
||||
}
|
||||
RegCloseKey (unit_key);
|
||||
}
|
||||
++i;
|
||||
}
|
||||
|
||||
RegCloseKey (netcard_key);
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
static int get_device_guid(
|
||||
char *name,
|
||||
int name_size,
|
||||
char *actual_name,
|
||||
int actual_name_size)
|
||||
{
|
||||
LONG status;
|
||||
HKEY control_net_key;
|
||||
DWORD len;
|
||||
int i = 0;
|
||||
int stop = 0;
|
||||
|
||||
status = RegOpenKeyEx(
|
||||
HKEY_LOCAL_MACHINE,
|
||||
NETWORK_CONNECTIONS_KEY,
|
||||
0,
|
||||
KEY_READ,
|
||||
&control_net_key);
|
||||
|
||||
if (status != ERROR_SUCCESS) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
while (!stop)
|
||||
{
|
||||
char enum_name[256];
|
||||
char connection_string[256];
|
||||
HKEY connection_key;
|
||||
char name_data[256];
|
||||
DWORD name_type;
|
||||
const char name_string[] = "Name";
|
||||
|
||||
len = sizeof (enum_name);
|
||||
status = RegEnumKeyEx(
|
||||
control_net_key,
|
||||
i,
|
||||
enum_name,
|
||||
&len,
|
||||
NULL,
|
||||
NULL,
|
||||
NULL,
|
||||
NULL);
|
||||
|
||||
if (status == ERROR_NO_MORE_ITEMS)
|
||||
break;
|
||||
else if (status != ERROR_SUCCESS) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
_snprintf(connection_string,
|
||||
sizeof(connection_string),
|
||||
"%s\\%s\\Connection",
|
||||
NETWORK_CONNECTIONS_KEY, enum_name);
|
||||
|
||||
status = RegOpenKeyEx(
|
||||
HKEY_LOCAL_MACHINE,
|
||||
connection_string,
|
||||
0,
|
||||
KEY_READ,
|
||||
&connection_key);
|
||||
|
||||
if (status == ERROR_SUCCESS) {
|
||||
len = sizeof (name_data);
|
||||
status = RegQueryValueEx(
|
||||
connection_key,
|
||||
name_string,
|
||||
NULL,
|
||||
&name_type,
|
||||
(LPBYTE)name_data,
|
||||
&len);
|
||||
|
||||
if (status != ERROR_SUCCESS || name_type != REG_SZ) {
|
||||
return -1;
|
||||
}
|
||||
else {
|
||||
if (is_tap_win32_dev(enum_name)) {
|
||||
_snprintf(name, name_size, "%s", enum_name);
|
||||
if (actual_name) {
|
||||
if (strcmp(actual_name, "") != 0) {
|
||||
if (strcmp(name_data, actual_name) != 0) {
|
||||
RegCloseKey (connection_key);
|
||||
++i;
|
||||
continue;
|
||||
}
|
||||
}
|
||||
else {
|
||||
_snprintf(actual_name, actual_name_size, "%s", name_data);
|
||||
}
|
||||
}
|
||||
stop = 1;
|
||||
}
|
||||
}
|
||||
|
||||
RegCloseKey (connection_key);
|
||||
}
|
||||
++i;
|
||||
}
|
||||
|
||||
RegCloseKey (control_net_key);
|
||||
|
||||
if (stop == 0)
|
||||
return -1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
|
||||
static void tap_win32_overlapped_init(tap_win32_overlapped_t* const overlapped, const HANDLE handle)
|
||||
{
|
||||
overlapped->handle = handle;
|
||||
|
||||
overlapped->read_event = CreateEvent(NULL, FALSE, FALSE, NULL);
|
||||
overlapped->write_event = CreateEvent(NULL, FALSE, FALSE, NULL);
|
||||
|
||||
overlapped->read_overlapped.Offset = 0;
|
||||
overlapped->read_overlapped.OffsetHigh = 0;
|
||||
overlapped->read_overlapped.hEvent = overlapped->read_event;
|
||||
|
||||
overlapped->write_overlapped.Offset = 0;
|
||||
overlapped->write_overlapped.OffsetHigh = 0;
|
||||
overlapped->write_overlapped.hEvent = overlapped->write_event;
|
||||
|
||||
InitializeCriticalSection(&overlapped->output_queue_cs);
|
||||
InitializeCriticalSection(&overlapped->free_list_cs);
|
||||
|
||||
overlapped->output_queue_semaphore = CreateSemaphore(
|
||||
NULL, // default security attributes
|
||||
0, // initial count
|
||||
TUN_MAX_BUFFER_COUNT, // maximum count
|
||||
NULL); // unnamed semaphore
|
||||
|
||||
if(!overlapped->output_queue_semaphore) {
|
||||
fprintf(stderr, "error creating output queue semaphore!\n");
|
||||
}
|
||||
|
||||
overlapped->free_list_semaphore = CreateSemaphore(
|
||||
NULL, // default security attributes
|
||||
TUN_MAX_BUFFER_COUNT, // initial count
|
||||
TUN_MAX_BUFFER_COUNT, // maximum count
|
||||
NULL); // unnamed semaphore
|
||||
|
||||
if(!overlapped->free_list_semaphore) {
|
||||
fprintf(stderr, "error creating free list semaphore!\n");
|
||||
}
|
||||
|
||||
overlapped->free_list = overlapped->output_queue_front = overlapped->output_queue_back = NULL;
|
||||
|
||||
{
|
||||
unsigned index;
|
||||
for(index = 0; index < TUN_MAX_BUFFER_COUNT; index++) {
|
||||
tun_buffer_t* element = &overlapped->buffers[index];
|
||||
element->next = overlapped->free_list;
|
||||
overlapped->free_list = element;
|
||||
}
|
||||
}
|
||||
/* To count buffers, initially no-signal. */
|
||||
overlapped->tap_semaphore = CreateSemaphore(NULL, 0, TUN_MAX_BUFFER_COUNT, NULL);
|
||||
if(!overlapped->tap_semaphore)
|
||||
fprintf(stderr, "error creating tap_semaphore.\n");
|
||||
}
|
||||
|
||||
static int tap_win32_write(tap_win32_overlapped_t *overlapped,
|
||||
const void *buffer, unsigned long size)
|
||||
{
|
||||
unsigned long write_size;
|
||||
BOOL result;
|
||||
DWORD error;
|
||||
|
||||
result = GetOverlappedResult( overlapped->handle, &overlapped->write_overlapped,
|
||||
&write_size, FALSE);
|
||||
|
||||
if (!result && GetLastError() == ERROR_IO_INCOMPLETE)
|
||||
WaitForSingleObject(overlapped->write_event, INFINITE);
|
||||
|
||||
result = WriteFile(overlapped->handle, buffer, size,
|
||||
&write_size, &overlapped->write_overlapped);
|
||||
|
||||
if (!result) {
|
||||
switch (error = GetLastError())
|
||||
{
|
||||
case ERROR_IO_PENDING:
|
||||
#ifndef TUN_ASYNCHRONOUS_WRITES
|
||||
WaitForSingleObject(overlapped->write_event, INFINITE);
|
||||
#endif
|
||||
break;
|
||||
default:
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static DWORD WINAPI tap_win32_thread_entry(LPVOID param)
|
||||
{
|
||||
tap_win32_overlapped_t *overlapped = (tap_win32_overlapped_t*)param;
|
||||
unsigned long read_size;
|
||||
BOOL result;
|
||||
DWORD dwError;
|
||||
tun_buffer_t* buffer = get_buffer_from_free_list(overlapped);
|
||||
|
||||
|
||||
for (;;) {
|
||||
result = ReadFile(overlapped->handle,
|
||||
buffer->buffer,
|
||||
sizeof(buffer->buffer),
|
||||
&read_size,
|
||||
&overlapped->read_overlapped);
|
||||
if (!result) {
|
||||
dwError = GetLastError();
|
||||
if (dwError == ERROR_IO_PENDING) {
|
||||
WaitForSingleObject(overlapped->read_event, INFINITE);
|
||||
result = GetOverlappedResult( overlapped->handle, &overlapped->read_overlapped,
|
||||
&read_size, FALSE);
|
||||
if (!result) {
|
||||
#if DEBUG_TAP_WIN32
|
||||
LPVOID lpBuffer;
|
||||
dwError = GetLastError();
|
||||
FormatMessage( FORMAT_MESSAGE_ALLOCATE_BUFFER | FORMAT_MESSAGE_FROM_SYSTEM,
|
||||
NULL, dwError, MAKELANGID(LANG_NEUTRAL, SUBLANG_DEFAULT),
|
||||
(LPTSTR) & lpBuffer, 0, NULL );
|
||||
fprintf(stderr, "Tap-Win32: Error GetOverlappedResult %d - %s\n", dwError, lpBuffer);
|
||||
LocalFree( lpBuffer );
|
||||
#endif
|
||||
}
|
||||
} else {
|
||||
#if DEBUG_TAP_WIN32
|
||||
LPVOID lpBuffer;
|
||||
FormatMessage( FORMAT_MESSAGE_ALLOCATE_BUFFER | FORMAT_MESSAGE_FROM_SYSTEM,
|
||||
NULL, dwError, MAKELANGID(LANG_NEUTRAL, SUBLANG_DEFAULT),
|
||||
(LPTSTR) & lpBuffer, 0, NULL );
|
||||
fprintf(stderr, "Tap-Win32: Error ReadFile %d - %s\n", dwError, lpBuffer);
|
||||
LocalFree( lpBuffer );
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
if(read_size > 0) {
|
||||
buffer->read_size = read_size;
|
||||
put_buffer_on_output_queue(overlapped, buffer);
|
||||
ReleaseSemaphore(overlapped->tap_semaphore, 1, NULL);
|
||||
buffer = get_buffer_from_free_list(overlapped);
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
typedef unsigned __int8 uint8_t;
|
||||
|
||||
static int tap_win32_read(tap_win32_overlapped_t *overlapped,
|
||||
uint8_t **pbuf, int max_size)
|
||||
{
|
||||
int size = 0;
|
||||
|
||||
tun_buffer_t* buffer = get_buffer_from_output_queue_immediate(overlapped);
|
||||
|
||||
if(buffer != NULL) {
|
||||
*pbuf = buffer->buffer;
|
||||
size = (int)buffer->read_size;
|
||||
if(size > max_size) {
|
||||
size = max_size;
|
||||
}
|
||||
}
|
||||
|
||||
return size;
|
||||
}
|
||||
|
||||
static void tap_win32_free_buffer(tap_win32_overlapped_t *overlapped,
|
||||
char* pbuf)
|
||||
{
|
||||
tun_buffer_t* buffer = (tun_buffer_t*)pbuf;
|
||||
put_buffer_on_free_list(overlapped, buffer);
|
||||
}
|
||||
|
||||
static int tap_win32_open(tap_win32_overlapped_t **phandle,
|
||||
const char *prefered_name)
|
||||
{
|
||||
char device_path[256];
|
||||
char device_guid[0x100];
|
||||
int rc;
|
||||
HANDLE handle;
|
||||
BOOL bret;
|
||||
char name_buffer[0x100] = {0, };
|
||||
struct {
|
||||
unsigned long major;
|
||||
unsigned long minor;
|
||||
unsigned long debug;
|
||||
} version;
|
||||
LONG version_len;
|
||||
DWORD idThread;
|
||||
HANDLE hThread;
|
||||
|
||||
if (prefered_name != NULL)
|
||||
_snprintf(name_buffer, sizeof(name_buffer), "%s", prefered_name);
|
||||
|
||||
rc = get_device_guid(device_guid, sizeof(device_guid), name_buffer, sizeof(name_buffer));
|
||||
if (rc)
|
||||
return -1;
|
||||
|
||||
_snprintf (device_path, sizeof(device_path), "%s%s%s",
|
||||
USERMODEDEVICEDIR,
|
||||
device_guid,
|
||||
TAPSUFFIX);
|
||||
|
||||
handle = CreateFile (
|
||||
device_path,
|
||||
GENERIC_READ | GENERIC_WRITE,
|
||||
0,
|
||||
0,
|
||||
OPEN_EXISTING,
|
||||
FILE_ATTRIBUTE_SYSTEM | FILE_FLAG_OVERLAPPED,
|
||||
0 );
|
||||
|
||||
if (handle == INVALID_HANDLE_VALUE) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
bret = DeviceIoControl(handle, TAP_IOCTL_GET_VERSION,
|
||||
&version, sizeof (version),
|
||||
&version, sizeof (version), (LPDWORD)&version_len, NULL);
|
||||
|
||||
if (bret == FALSE) {
|
||||
CloseHandle(handle);
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (!tap_win32_set_status(handle, TRUE)) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
tap_win32_overlapped_init(&tap_overlapped, handle);
|
||||
|
||||
*phandle = &tap_overlapped;
|
||||
|
||||
hThread = CreateThread(NULL, 0, tap_win32_thread_entry,
|
||||
(LPVOID)&tap_overlapped, 0, &idThread);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/********************************************/
|
||||
|
||||
typedef struct TAPState {
|
||||
tap_win32_overlapped_t *handle;
|
||||
} TAPState;
|
||||
|
||||
static void tap_receive(void *opaque, const uint8_t *buf, int size)
|
||||
{
|
||||
TAPState *s = (TAPState *)opaque;
|
||||
|
||||
tap_win32_write(s->handle, buf, size);
|
||||
}
|
||||
|
||||
static void tap_win32_send(void *opaque)
|
||||
{
|
||||
TAPState *s = (TAPState *)opaque;
|
||||
uint8_t *buf;
|
||||
int max_size = 4096;
|
||||
int size;
|
||||
|
||||
size = tap_win32_read(s->handle, &buf, max_size);
|
||||
if (size > 0) {
|
||||
//qemu_send_packet(s->vc, buf, size);
|
||||
tap_win32_free_buffer(s->handle, (char*)buf);
|
||||
}
|
||||
}
|
||||
|
||||
int tap_win32_init(const char *ifname)
|
||||
{
|
||||
TAPState *s = (TAPState *)malloc(sizeof(TAPState));
|
||||
if (!s)
|
||||
return -1;
|
||||
|
||||
memset(s,0,sizeof(TAPState));
|
||||
|
||||
if (tap_win32_open(&s->handle, ifname) < 0) {
|
||||
printf("tap: Could not open '%s'\n", ifname);
|
||||
return -1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif
|
||||
}
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/* PCSX2 - PS2 Emulator for PCs
|
||||
* Copyright (C) 2002-2010 PCSX2 Dev Team
|
||||
* Copyright (C) 2002-2020 PCSX2 Dev Team
|
||||
*
|
||||
* PCSX2 is free software: you can redistribute it and/or modify it under the terms
|
||||
* of the GNU Lesser General Public License as published by the Free Software Found-
|
||||
|
|
@ -21,8 +21,8 @@ using namespace std;
|
|||
|
||||
struct tap_adapter
|
||||
{
|
||||
string name;
|
||||
string guid;
|
||||
TCHAR *name;
|
||||
TCHAR *guid;
|
||||
};
|
||||
vector<tap_adapter>* GetTapAdapters();
|
||||
class TAPAdapter : public NetAdapter
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/* PCSX2 - PS2 Emulator for PCs
|
||||
* Copyright (C) 2002-2010 PCSX2 Dev Team
|
||||
* Copyright (C) 2002-2020 PCSX2 Dev Team
|
||||
*
|
||||
* PCSX2 is free software: you can redistribute it and/or modify it under the terms
|
||||
* of the GNU Lesser General Public License as published by the Free Software Found-
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/* PCSX2 - PS2 Emulator for PCs
|
||||
* Copyright (C) 2002-2010 PCSX2 Dev Team
|
||||
* Copyright (C) 2002-2020 PCSX2 Dev Team
|
||||
*
|
||||
* PCSX2 is free software: you can redistribute it and/or modify it under the terms
|
||||
* of the GNU Lesser General Public License as published by the Free Software Found-
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/* PCSX2 - PS2 Emulator for PCs
|
||||
* Copyright (C) 2002-2010 PCSX2 Dev Team
|
||||
* Copyright (C) 2002-2020 PCSX2 Dev Team
|
||||
*
|
||||
* PCSX2 is free software: you can redistribute it and/or modify it under the terms
|
||||
* of the GNU Lesser General Public License as published by the Free Software Found-
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/* PCSX2 - PS2 Emulator for PCs
|
||||
* Copyright (C) 2002-2010 PCSX2 Dev Team
|
||||
* Copyright (C) 2002-2020 PCSX2 Dev Team
|
||||
*
|
||||
* PCSX2 is free software: you can redistribute it and/or modify it under the terms
|
||||
* of the GNU Lesser General Public License as published by the Free Software Found-
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/* PCSX2 - PS2 Emulator for PCs
|
||||
* Copyright (C) 2002-2010 PCSX2 Dev Team
|
||||
* Copyright (C) 2002-2020 PCSX2 Dev Team
|
||||
*
|
||||
* PCSX2 is free software: you can redistribute it and/or modify it under the terms
|
||||
* of the GNU Lesser General Public License as published by the Free Software Found-
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/* PCSX2 - PS2 Emulator for PCs
|
||||
* Copyright (C) 2002-2010 PCSX2 Dev Team
|
||||
* Copyright (C) 2002-2020 PCSX2 Dev Team
|
||||
*
|
||||
* PCSX2 is free software: you can redistribute it and/or modify it under the terms
|
||||
* of the GNU Lesser General Public License as published by the Free Software Found-
|
||||
|
|
@ -694,35 +694,37 @@ smap_write16(u32 addr, u16 value)
|
|||
DEV9_LOG("SMAP: " #name " 16 bit write %x\n", value); \
|
||||
dev9Ru16(addr) = value; \
|
||||
return;
|
||||
//handle L writes
|
||||
EMAC3_L_WRITE(SMAP_R_EMAC3_MODE0_L)
|
||||
EMAC3_L_WRITE(SMAP_R_EMAC3_MODE1_L)
|
||||
EMAC3_L_WRITE(SMAP_R_EMAC3_TxMODE0_L)
|
||||
EMAC3_L_WRITE(SMAP_R_EMAC3_TxMODE1_L)
|
||||
EMAC3_L_WRITE(SMAP_R_EMAC3_RxMODE_L)
|
||||
EMAC3_L_WRITE(SMAP_R_EMAC3_INTR_STAT_L)
|
||||
EMAC3_L_WRITE(SMAP_R_EMAC3_INTR_ENABLE_L)
|
||||
EMAC3_L_WRITE(SMAP_R_EMAC3_ADDR_HI_L)
|
||||
EMAC3_L_WRITE(SMAP_R_EMAC3_ADDR_LO_L)
|
||||
EMAC3_L_WRITE(SMAP_R_EMAC3_VLAN_TPID)
|
||||
EMAC3_L_WRITE(SMAP_R_EMAC3_PAUSE_TIMER_L)
|
||||
EMAC3_L_WRITE(SMAP_R_EMAC3_INDIVID_HASH1)
|
||||
EMAC3_L_WRITE(SMAP_R_EMAC3_INDIVID_HASH2)
|
||||
EMAC3_L_WRITE(SMAP_R_EMAC3_INDIVID_HASH3)
|
||||
EMAC3_L_WRITE(SMAP_R_EMAC3_INDIVID_HASH4)
|
||||
EMAC3_L_WRITE(SMAP_R_EMAC3_GROUP_HASH1)
|
||||
EMAC3_L_WRITE(SMAP_R_EMAC3_GROUP_HASH2)
|
||||
EMAC3_L_WRITE(SMAP_R_EMAC3_GROUP_HASH3)
|
||||
EMAC3_L_WRITE(SMAP_R_EMAC3_GROUP_HASH4)
|
||||
// clang-format off
|
||||
//handle L writes
|
||||
EMAC3_L_WRITE(SMAP_R_EMAC3_MODE0_L)
|
||||
EMAC3_L_WRITE(SMAP_R_EMAC3_MODE1_L)
|
||||
EMAC3_L_WRITE(SMAP_R_EMAC3_TxMODE0_L)
|
||||
EMAC3_L_WRITE(SMAP_R_EMAC3_TxMODE1_L)
|
||||
EMAC3_L_WRITE(SMAP_R_EMAC3_RxMODE_L)
|
||||
EMAC3_L_WRITE(SMAP_R_EMAC3_INTR_STAT_L)
|
||||
EMAC3_L_WRITE(SMAP_R_EMAC3_INTR_ENABLE_L)
|
||||
EMAC3_L_WRITE(SMAP_R_EMAC3_ADDR_HI_L)
|
||||
EMAC3_L_WRITE(SMAP_R_EMAC3_ADDR_LO_L)
|
||||
EMAC3_L_WRITE(SMAP_R_EMAC3_VLAN_TPID)
|
||||
EMAC3_L_WRITE(SMAP_R_EMAC3_PAUSE_TIMER_L)
|
||||
EMAC3_L_WRITE(SMAP_R_EMAC3_INDIVID_HASH1)
|
||||
EMAC3_L_WRITE(SMAP_R_EMAC3_INDIVID_HASH2)
|
||||
EMAC3_L_WRITE(SMAP_R_EMAC3_INDIVID_HASH3)
|
||||
EMAC3_L_WRITE(SMAP_R_EMAC3_INDIVID_HASH4)
|
||||
EMAC3_L_WRITE(SMAP_R_EMAC3_GROUP_HASH1)
|
||||
EMAC3_L_WRITE(SMAP_R_EMAC3_GROUP_HASH2)
|
||||
EMAC3_L_WRITE(SMAP_R_EMAC3_GROUP_HASH3)
|
||||
EMAC3_L_WRITE(SMAP_R_EMAC3_GROUP_HASH4)
|
||||
|
||||
EMAC3_L_WRITE(SMAP_R_EMAC3_LAST_SA_HI)
|
||||
EMAC3_L_WRITE(SMAP_R_EMAC3_LAST_SA_LO)
|
||||
EMAC3_L_WRITE(SMAP_R_EMAC3_INTER_FRAME_GAP_L)
|
||||
EMAC3_L_WRITE(SMAP_R_EMAC3_STA_CTRL_L)
|
||||
EMAC3_L_WRITE(SMAP_R_EMAC3_TX_THRESHOLD_L)
|
||||
EMAC3_L_WRITE(SMAP_R_EMAC3_RX_WATERMARK_L)
|
||||
EMAC3_L_WRITE(SMAP_R_EMAC3_TX_OCTETS)
|
||||
EMAC3_L_WRITE(SMAP_R_EMAC3_RX_OCTETS)
|
||||
EMAC3_L_WRITE(SMAP_R_EMAC3_LAST_SA_HI)
|
||||
EMAC3_L_WRITE(SMAP_R_EMAC3_LAST_SA_LO)
|
||||
EMAC3_L_WRITE(SMAP_R_EMAC3_INTER_FRAME_GAP_L)
|
||||
EMAC3_L_WRITE(SMAP_R_EMAC3_STA_CTRL_L)
|
||||
EMAC3_L_WRITE(SMAP_R_EMAC3_TX_THRESHOLD_L)
|
||||
EMAC3_L_WRITE(SMAP_R_EMAC3_RX_WATERMARK_L)
|
||||
EMAC3_L_WRITE(SMAP_R_EMAC3_TX_OCTETS)
|
||||
EMAC3_L_WRITE(SMAP_R_EMAC3_RX_OCTETS)
|
||||
// clang-format on
|
||||
|
||||
#define EMAC3_H_WRITE(name) \
|
||||
case name: \
|
||||
|
|
@ -730,35 +732,37 @@ smap_write16(u32 addr, u16 value)
|
|||
dev9Ru16(addr) = value; \
|
||||
emac3_write(addr - 2); \
|
||||
return;
|
||||
//handle H writes
|
||||
EMAC3_H_WRITE(SMAP_R_EMAC3_MODE0_H)
|
||||
EMAC3_H_WRITE(SMAP_R_EMAC3_MODE1_H)
|
||||
EMAC3_H_WRITE(SMAP_R_EMAC3_TxMODE0_H)
|
||||
EMAC3_H_WRITE(SMAP_R_EMAC3_TxMODE1_H)
|
||||
EMAC3_H_WRITE(SMAP_R_EMAC3_RxMODE_H)
|
||||
EMAC3_H_WRITE(SMAP_R_EMAC3_INTR_STAT_H)
|
||||
EMAC3_H_WRITE(SMAP_R_EMAC3_INTR_ENABLE_H)
|
||||
EMAC3_H_WRITE(SMAP_R_EMAC3_ADDR_HI_H)
|
||||
EMAC3_H_WRITE(SMAP_R_EMAC3_ADDR_LO_H)
|
||||
EMAC3_H_WRITE(SMAP_R_EMAC3_VLAN_TPID + 2)
|
||||
EMAC3_H_WRITE(SMAP_R_EMAC3_PAUSE_TIMER_H)
|
||||
EMAC3_H_WRITE(SMAP_R_EMAC3_INDIVID_HASH1 + 2)
|
||||
EMAC3_H_WRITE(SMAP_R_EMAC3_INDIVID_HASH2 + 2)
|
||||
EMAC3_H_WRITE(SMAP_R_EMAC3_INDIVID_HASH3 + 2)
|
||||
EMAC3_H_WRITE(SMAP_R_EMAC3_INDIVID_HASH4 + 2)
|
||||
EMAC3_H_WRITE(SMAP_R_EMAC3_GROUP_HASH1 + 2)
|
||||
EMAC3_H_WRITE(SMAP_R_EMAC3_GROUP_HASH2 + 2)
|
||||
EMAC3_H_WRITE(SMAP_R_EMAC3_GROUP_HASH3 + 2)
|
||||
EMAC3_H_WRITE(SMAP_R_EMAC3_GROUP_HASH4 + 2)
|
||||
// clang-format off
|
||||
//handle H writes
|
||||
EMAC3_H_WRITE(SMAP_R_EMAC3_MODE0_H)
|
||||
EMAC3_H_WRITE(SMAP_R_EMAC3_MODE1_H)
|
||||
EMAC3_H_WRITE(SMAP_R_EMAC3_TxMODE0_H)
|
||||
EMAC3_H_WRITE(SMAP_R_EMAC3_TxMODE1_H)
|
||||
EMAC3_H_WRITE(SMAP_R_EMAC3_RxMODE_H)
|
||||
EMAC3_H_WRITE(SMAP_R_EMAC3_INTR_STAT_H)
|
||||
EMAC3_H_WRITE(SMAP_R_EMAC3_INTR_ENABLE_H)
|
||||
EMAC3_H_WRITE(SMAP_R_EMAC3_ADDR_HI_H)
|
||||
EMAC3_H_WRITE(SMAP_R_EMAC3_ADDR_LO_H)
|
||||
EMAC3_H_WRITE(SMAP_R_EMAC3_VLAN_TPID + 2)
|
||||
EMAC3_H_WRITE(SMAP_R_EMAC3_PAUSE_TIMER_H)
|
||||
EMAC3_H_WRITE(SMAP_R_EMAC3_INDIVID_HASH1 + 2)
|
||||
EMAC3_H_WRITE(SMAP_R_EMAC3_INDIVID_HASH2 + 2)
|
||||
EMAC3_H_WRITE(SMAP_R_EMAC3_INDIVID_HASH3 + 2)
|
||||
EMAC3_H_WRITE(SMAP_R_EMAC3_INDIVID_HASH4 + 2)
|
||||
EMAC3_H_WRITE(SMAP_R_EMAC3_GROUP_HASH1 + 2)
|
||||
EMAC3_H_WRITE(SMAP_R_EMAC3_GROUP_HASH2 + 2)
|
||||
EMAC3_H_WRITE(SMAP_R_EMAC3_GROUP_HASH3 + 2)
|
||||
EMAC3_H_WRITE(SMAP_R_EMAC3_GROUP_HASH4 + 2)
|
||||
|
||||
EMAC3_H_WRITE(SMAP_R_EMAC3_LAST_SA_HI + 2)
|
||||
EMAC3_H_WRITE(SMAP_R_EMAC3_LAST_SA_LO + 2)
|
||||
EMAC3_H_WRITE(SMAP_R_EMAC3_INTER_FRAME_GAP_H)
|
||||
EMAC3_H_WRITE(SMAP_R_EMAC3_STA_CTRL_H)
|
||||
EMAC3_H_WRITE(SMAP_R_EMAC3_TX_THRESHOLD_H)
|
||||
EMAC3_H_WRITE(SMAP_R_EMAC3_RX_WATERMARK_H)
|
||||
EMAC3_H_WRITE(SMAP_R_EMAC3_TX_OCTETS + 2)
|
||||
EMAC3_H_WRITE(SMAP_R_EMAC3_RX_OCTETS + 2)
|
||||
EMAC3_H_WRITE(SMAP_R_EMAC3_LAST_SA_HI + 2)
|
||||
EMAC3_H_WRITE(SMAP_R_EMAC3_LAST_SA_LO + 2)
|
||||
EMAC3_H_WRITE(SMAP_R_EMAC3_INTER_FRAME_GAP_H)
|
||||
EMAC3_H_WRITE(SMAP_R_EMAC3_STA_CTRL_H)
|
||||
EMAC3_H_WRITE(SMAP_R_EMAC3_TX_THRESHOLD_H)
|
||||
EMAC3_H_WRITE(SMAP_R_EMAC3_RX_WATERMARK_H)
|
||||
EMAC3_H_WRITE(SMAP_R_EMAC3_TX_OCTETS + 2)
|
||||
EMAC3_H_WRITE(SMAP_R_EMAC3_RX_OCTETS + 2)
|
||||
// clang-format on
|
||||
/*
|
||||
case SMAP_R_EMAC3_MODE0_L:
|
||||
DEV9_LOG("SMAP: SMAP_R_EMAC3_MODE0 write %x\n", value);
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/* PCSX2 - PS2 Emulator for PCs
|
||||
* Copyright (C) 2002-2010 PCSX2 Dev Team
|
||||
* Copyright (C) 2002-2020 PCSX2 Dev Team
|
||||
*
|
||||
* PCSX2 is free software: you can redistribute it and/or modify it under the terms
|
||||
* of the GNU Lesser General Public License as published by the Free Software Found-
|
||||
|
|
|
|||
Loading…
Reference in New Issue