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pcsx2
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Still messing with Sif, Vif, and SPR. 

git-svn-id: http://pcsx2.googlecode.com/svn/trunk@879 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
arcum42 2009-04-01 11:55:29 +00:00
parent a547ef4cea
commit 65a4061c3a
7 changed files with 266 additions and 257 deletions
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169
pcsx2/Hw.cpp
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@ -130,21 +130,17 @@ int hwMFIFOWrite(u32 addr, u8 *data, u32 size) {
/* it does, so first copy 's1' bytes from 'data' to 'addr' */ /* it does, so first copy 's1' bytes from 'data' to 'addr' */
dst = (u8*)PSM(addr); dst = (u8*)PSM(addr);
if (dst == NULL) return -1; if (dst == NULL) return -1;
//Cpu->Clear(addr, s1/4);
memcpy_fast(dst, data, s1); memcpy_fast(dst, data, s1);
/* and second copy 's2' bytes from '&data[s1]' to 'maddr' */ /* and second copy 's2' bytes from '&data[s1]' to 'maddr' */
dst = (u8*)PSM(psHu32(DMAC_RBOR)); dst = (u8*)PSM(psHu32(DMAC_RBOR));
if (dst == NULL) return -1; if (dst == NULL) return -1;
//Cpu->Clear(psHu32(DMAC_RBOR), s2/4);
memcpy_fast(dst, &data[s1], s2); memcpy_fast(dst, &data[s1], s2);
} else { }
//u32 * tempptr, * tempptr2; else {
/* it doesn't, so just copy 'size' bytes from 'data' to 'addr' */ /* it doesn't, so just copy 'size' bytes from 'data' to 'addr' */
dst = (u8*)PSM(addr); dst = (u8*)PSM(addr);
if (dst == NULL) return -1; if (dst == NULL) return -1;
//Cpu->Clear(addr, size/4);
memcpy_fast(dst, data, size); memcpy_fast(dst, data, size);
} }
@ -157,7 +153,6 @@ int hwDmacSrcChainWithStack(DMACh *dma, int id) {
switch (id) { switch (id) {
case 0: // Refe - Transfer Packet According to ADDR field case 0: // Refe - Transfer Packet According to ADDR field
//dma->tadr += 16;
return 1; //End Transfer return 1; //End Transfer
case 1: // CNT - Transfer QWC following the tag. case 1: // CNT - Transfer QWC following the tag.
@ -184,7 +179,8 @@ int hwDmacSrcChainWithStack(DMACh *dma, int id) {
if ((dma->chcr & 0x30) == 0x0) { //Check if ASR0 is empty if ((dma->chcr & 0x30) == 0x0) { //Check if ASR0 is empty
dma->asr0 = dma->madr + (dma->qwc << 4); //If yes store Succeeding tag dma->asr0 = dma->madr + (dma->qwc << 4); //If yes store Succeeding tag
dma->chcr = (dma->chcr & 0xffffffcf) | 0x10; //1 Address in call stack dma->chcr = (dma->chcr & 0xffffffcf) | 0x10; //1 Address in call stack
}else if((dma->chcr & 0x30) == 0x10){ }
else if((dma->chcr & 0x30) == 0x10){
dma->chcr = (dma->chcr & 0xffffffcf) | 0x20; //2 Addresses in call stack dma->chcr = (dma->chcr & 0xffffffcf) | 0x20; //2 Addresses in call stack
dma->asr1 = dma->madr + (dma->qwc << 4); //If no store Succeeding tag in ASR1 dma->asr1 = dma->madr + (dma->qwc << 4); //If no store Succeeding tag in ASR1
}else { }else {
@ -202,7 +198,8 @@ int hwDmacSrcChainWithStack(DMACh *dma, int id) {
dma->chcr = (dma->chcr & 0xffffffcf) | 0x10; //1 Address left in call stack dma->chcr = (dma->chcr & 0xffffffcf) | 0x10; //1 Address left in call stack
dma->tadr = dma->asr1; //Read ASR1 as next tag dma->tadr = dma->asr1; //Read ASR1 as next tag
dma->asr1 = 0; //Clear ASR1 dma->asr1 = 0; //Clear ASR1
} else { //If ASR1 is empty (No address held) }
else { //If ASR1 is empty (No address held)
if((dma->chcr & 0x30) == 0x10) { //Check if ASR0 is NOT equal to 0 (Contains address) if((dma->chcr & 0x30) == 0x10) { //Check if ASR0 is NOT equal to 0 (Contains address)
dma->chcr = (dma->chcr & 0xffffffcf); //No addresses left in call stack dma->chcr = (dma->chcr & 0xffffffcf); //No addresses left in call stack
dma->tadr = dma->asr0; //Read ASR0 as next tag dma->tadr = dma->asr0; //Read ASR0 as next tag
@ -216,8 +213,7 @@ int hwDmacSrcChainWithStack(DMACh *dma, int id) {
case 7: // End - Transfer QWC following the tag case 7: // End - Transfer QWC following the tag
dma->madr = dma->tadr + 16; //Set MADR to data following the tag dma->madr = dma->tadr + 16; //Set MADR to data following the tag
//comment out tadr fixes lemans //Dont Increment tadr, breaks Soul Calibur II and III
//dma->tadr = dma->madr + (dma->qwc << 4); //Dont Increment tag, breaks Soul Calibur II and III
return 1; //End Transfer return 1; //End Transfer
} }
@ -229,7 +225,6 @@ int hwDmacSrcChain(DMACh *dma, int id) {
switch (id) { switch (id) {
case 0: // Refe - Transfer Packet According to ADDR field case 0: // Refe - Transfer Packet According to ADDR field
//dma->tadr += 16;
return 1; //End Transfer return 1; //End Transfer
case 1: // CNT - Transfer QWC following the tag. case 1: // CNT - Transfer QWC following the tag.
@ -250,7 +245,7 @@ int hwDmacSrcChain(DMACh *dma, int id) {
case 7: // End - Transfer QWC following the tag case 7: // End - Transfer QWC following the tag
dma->madr = dma->tadr + 16; //Set MADR to data following the tag dma->madr = dma->tadr + 16; //Set MADR to data following the tag
//dma->tadr = dma->madr + (dma->qwc << 4); //Dont Increment tag, breaks Soul Calibur II and III //Dont Increment tadr, breaks Soul Calibur II and III
return 1; //End Transfer return 1; //End Transfer
} }
@ -467,18 +462,30 @@ __forceinline void __fastcall hwWrite32(u32 mem, u32 value)
case GIF_CTRL: case GIF_CTRL:
//Console::WriteLn("GIF_CTRL write %x", params value); //Console::WriteLn("GIF_CTRL write %x", params value);
psHu32(mem) = value & 0x8; psHu32(mem) = value & 0x8;
if (value & 0x1) gsGIFReset();
else if( value & 8 ) psHu32(GIF_STAT) |= 8; if (value & 0x1)
else psHu32(GIF_STAT) &= ~8; gsGIFReset();
else if( value & 8 )
psHu32(GIF_STAT) |= 8;
else
psHu32(GIF_STAT) &= ~8;
return; return;
case GIF_MODE: case GIF_MODE:
// need to set GIF_MODE (hamster ball) // need to set GIF_MODE (hamster ball)
psHu32(GIF_MODE) = value; psHu32(GIF_MODE) = value;
if (value & 0x1) psHu32(GIF_STAT)|= 0x1;
else psHu32(GIF_STAT)&= ~0x1; if (value & 0x1)
if (value & 0x4) psHu32(GIF_STAT)|= 0x4; psHu32(GIF_STAT)|= 0x1;
else psHu32(GIF_STAT)&= ~0x4; else
psHu32(GIF_STAT)&= ~0x1;
if (value & 0x4)
psHu32(GIF_STAT)|= 0x4;
else
psHu32(GIF_STAT)&= ~0x4;
break; break;
case GIF_STAT: // stat is readonly case GIF_STAT: // stat is readonly
@ -489,153 +496,170 @@ __forceinline void __fastcall hwWrite32(u32 mem, u32 value)
DMA_LOG("VIF0dma %lx", value); DMA_LOG("VIF0dma %lx", value);
DmaExec(dmaVIF0, mem, value); DmaExec(dmaVIF0, mem, value);
break; break;
//------------------------------------------------------------------
case 0x10009000: // dma1 - vif1 - chcr case 0x10009000: // dma1 - vif1 - chcr
DMA_LOG("VIF1dma CHCR %lx", value); DMA_LOG("VIF1dma CHCR %lx", value);
DmaExec(dmaVIF1, mem, value); DmaExec(dmaVIF1, mem, value);
break; break;
#ifdef PCSX2_DEVBUILD #ifdef PCSX2_DEVBUILD
case 0x10009010: // dma1 - vif1 - madr case 0x10009010: // dma1 - vif1 - madr
HW_LOG("VIF1dma Madr %lx", value); HW_LOG("VIF1dma Madr %lx", value);
psHu32(mem) = value;//dma1 madr psHu32(mem) = value;//dma1 madr
break; break;
case 0x10009020: // dma1 - vif1 - qwc case 0x10009020: // dma1 - vif1 - qwc
HW_LOG("VIF1dma QWC %lx", value); HW_LOG("VIF1dma QWC %lx", value);
psHu32(mem) = value;//dma1 qwc psHu32(mem) = value;//dma1 qwc
break; break;
case 0x10009030: // dma1 - vif1 - tadr case 0x10009030: // dma1 - vif1 - tadr
HW_LOG("VIF1dma TADR %lx", value); HW_LOG("VIF1dma TADR %lx", value);
psHu32(mem) = value;//dma1 tadr psHu32(mem) = value;//dma1 tadr
break; break;
case 0x10009040: // dma1 - vif1 - asr0 case 0x10009040: // dma1 - vif1 - asr0
HW_LOG("VIF1dma ASR0 %lx", value); HW_LOG("VIF1dma ASR0 %lx", value);
psHu32(mem) = value;//dma1 asr0 psHu32(mem) = value;//dma1 asr0
break; break;
case 0x10009050: // dma1 - vif1 - asr1 case 0x10009050: // dma1 - vif1 - asr1
HW_LOG("VIF1dma ASR1 %lx", value); HW_LOG("VIF1dma ASR1 %lx", value);
psHu32(mem) = value;//dma1 asr1 psHu32(mem) = value;//dma1 asr1
break; break;
case 0x10009080: // dma1 - vif1 - sadr case 0x10009080: // dma1 - vif1 - sadr
HW_LOG("VIF1dma SADR %lx", value); HW_LOG("VIF1dma SADR %lx", value);
psHu32(mem) = value;//dma1 sadr psHu32(mem) = value;//dma1 sadr
break; break;
#endif #endif
//------------------------------------------------------------------
case 0x1000a000: // dma2 - gif case 0x1000a000: // dma2 - gif
DMA_LOG("0x%8.8x hwWrite32: GSdma %lx", cpuRegs.cycle, value); DMA_LOG("0x%8.8x hwWrite32: GSdma %lx", cpuRegs.cycle, value);
DmaExec(dmaGIF, mem, value); DmaExec(dmaGIF, mem, value);
break; break;
#ifdef PCSX2_DEVBUILD #ifdef PCSX2_DEVBUILD
case 0x1000a010: case 0x1000a010:
psHu32(mem) = value;//dma2 madr psHu32(mem) = value;//dma2 madr
HW_LOG("Hardware write DMA2_MADR 32bit at %x with value %x",mem,value); HW_LOG("Hardware write DMA2_MADR 32bit at %x with value %x",mem,value);
break; break;
case 0x1000a020:
psHu32(mem) = value;//dma2 qwc case 0x1000a020:
HW_LOG("Hardware write DMA2_QWC 32bit at %x with value %x",mem,value); psHu32(mem) = value;//dma2 qwc
break; HW_LOG("Hardware write DMA2_QWC 32bit at %x with value %x",mem,value);
case 0x1000a030: break;
psHu32(mem) = value;//dma2 taddr
HW_LOG("Hardware write DMA2_TADDR 32bit at %x with value %x",mem,value); case 0x1000a030:
break; psHu32(mem) = value;//dma2 taddr
case 0x1000a040: HW_LOG("Hardware write DMA2_TADDR 32bit at %x with value %x",mem,value);
psHu32(mem) = value;//dma2 asr0 break;
HW_LOG("Hardware write DMA2_ASR0 32bit at %x with value %x",mem,value);
break; case 0x1000a040:
case 0x1000a050: psHu32(mem) = value;//dma2 asr0
psHu32(mem) = value;//dma2 asr1 HW_LOG("Hardware write DMA2_ASR0 32bit at %x with value %x",mem,value);
HW_LOG("Hardware write DMA2_ASR1 32bit at %x with value %x",mem,value); break;
break;
case 0x1000a080: case 0x1000a050:
psHu32(mem) = value;//dma2 saddr psHu32(mem) = value;//dma2 asr1
HW_LOG("Hardware write DMA2_SADDR 32bit at %x with value %x",mem,value); HW_LOG("Hardware write DMA2_ASR1 32bit at %x with value %x",mem,value);
break; break;
case 0x1000a080:
psHu32(mem) = value;//dma2 saddr
HW_LOG("Hardware write DMA2_SADDR 32bit at %x with value %x",mem,value);
break;
#endif #endif
//------------------------------------------------------------------
case 0x1000b000: // dma3 - fromIPU case 0x1000b000: // dma3 - fromIPU
DMA_LOG("IPU0dma %lx", value); DMA_LOG("IPU0dma %lx", value);
DmaExec(dmaIPU0, mem, value); DmaExec(dmaIPU0, mem, value);
break; break;
//------------------------------------------------------------------
#ifdef PCSX2_DEVBUILD #ifdef PCSX2_DEVBUILD
case 0x1000b010: case 0x1000b010:
psHu32(mem) = value;//dma2 madr psHu32(mem) = value;//dma2 madr
HW_LOG("Hardware write IPU0DMA_MADR 32bit at %x with value %x",mem,value); HW_LOG("Hardware write IPU0DMA_MADR 32bit at %x with value %x",mem,value);
break; break;
case 0x1000b020: case 0x1000b020:
psHu32(mem) = value;//dma2 madr psHu32(mem) = value;//dma2 madr
HW_LOG("Hardware write IPU0DMA_QWC 32bit at %x with value %x",mem,value); HW_LOG("Hardware write IPU0DMA_QWC 32bit at %x with value %x",mem,value);
break; break;
case 0x1000b030: case 0x1000b030:
psHu32(mem) = value;//dma2 tadr psHu32(mem) = value;//dma2 tadr
HW_LOG("Hardware write IPU0DMA_TADR 32bit at %x with value %x",mem,value); HW_LOG("Hardware write IPU0DMA_TADR 32bit at %x with value %x",mem,value);
break; break;
case 0x1000b080: case 0x1000b080:
psHu32(mem) = value;//dma2 saddr psHu32(mem) = value;//dma2 saddr
HW_LOG("Hardware write IPU0DMA_SADDR 32bit at %x with value %x",mem,value); HW_LOG("Hardware write IPU0DMA_SADDR 32bit at %x with value %x",mem,value);
break; break;
#endif #endif
//------------------------------------------------------------------
case 0x1000b400: // dma4 - toIPU case 0x1000b400: // dma4 - toIPU
DMA_LOG("IPU1dma %lx", value); DMA_LOG("IPU1dma %lx", value);
DmaExec(dmaIPU1, mem, value); DmaExec(dmaIPU1, mem, value);
break; break;
//------------------------------------------------------------------
#ifdef PCSX2_DEVBUILD #ifdef PCSX2_DEVBUILD
case 0x1000b410: case 0x1000b410:
psHu32(mem) = value;//dma2 madr psHu32(mem) = value;//dma2 madr
HW_LOG("Hardware write IPU1DMA_MADR 32bit at %x with value %x",mem,value); HW_LOG("Hardware write IPU1DMA_MADR 32bit at %x with value %x",mem,value);
break; break;
case 0x1000b420: case 0x1000b420:
psHu32(mem) = value;//dma2 madr psHu32(mem) = value;//dma2 madr
HW_LOG("Hardware write IPU1DMA_QWC 32bit at %x with value %x",mem,value); HW_LOG("Hardware write IPU1DMA_QWC 32bit at %x with value %x",mem,value);
break; break;
case 0x1000b430: case 0x1000b430:
psHu32(mem) = value;//dma2 tadr psHu32(mem) = value;//dma2 tadr
HW_LOG("Hardware write IPU1DMA_TADR 32bit at %x with value %x",mem,value); HW_LOG("Hardware write IPU1DMA_TADR 32bit at %x with value %x",mem,value);
break; break;
case 0x1000b480: case 0x1000b480:
psHu32(mem) = value;//dma2 saddr psHu32(mem) = value;//dma2 saddr
HW_LOG("Hardware write IPU1DMA_SADDR 32bit at %x with value %x",mem,value); HW_LOG("Hardware write IPU1DMA_SADDR 32bit at %x with value %x",mem,value);
break; break;
#endif #endif
//------------------------------------------------------------------
case 0x1000c000: // dma5 - sif0 case 0x1000c000: // dma5 - sif0
DMA_LOG("SIF0dma %lx", value); DMA_LOG("SIF0dma %lx", value);
//if (value == 0) psxSu32(0x30) = 0x40000;
DmaExec(dmaSIF0, mem, value); DmaExec(dmaSIF0, mem, value);
break; break;
//------------------------------------------------------------------
case 0x1000c400: // dma6 - sif1 case 0x1000c400: // dma6 - sif1
DMA_LOG("SIF1dma %lx", value); DMA_LOG("SIF1dma %lx", value);
DmaExec(dmaSIF1, mem, value); DmaExec(dmaSIF1, mem, value);
break; break;
#ifdef PCSX2_DEVBUILD #ifdef PCSX2_DEVBUILD
case 0x1000c420: // dma6 - sif1 - qwc case 0x1000c420: // dma6 - sif1 - qwc
HW_LOG("SIF1dma QWC = %lx", value); HW_LOG("SIF1dma QWC = %lx", value);
psHu32(mem) = value; psHu32(mem) = value;
break; break;
case 0x1000c430: // dma6 - sif1 - tadr case 0x1000c430: // dma6 - sif1 - tadr
HW_LOG("SIF1dma TADR = %lx", value); HW_LOG("SIF1dma TADR = %lx", value);
psHu32(mem) = value; psHu32(mem) = value;
break; break;
#endif #endif
//------------------------------------------------------------------
case 0x1000c800: // dma7 - sif2 case 0x1000c800: // dma7 - sif2
DMA_LOG("SIF2dma %lx", value); DMA_LOG("SIF2dma %lx", value);
DmaExec(dmaSIF2, mem, value); DmaExec(dmaSIF2, mem, value);
break; break;
//------------------------------------------------------------------
case 0x1000d000: // dma8 - fromSPR case 0x1000d000: // dma8 - fromSPR
DMA_LOG("fromSPRdma %lx", value); DMA_LOG("fromSPRdma %lx", value);
DmaExec(dmaSPR0, mem, value); DmaExec(dmaSPR0, mem, value);
break; break;
//------------------------------------------------------------------
case 0x1000d400: // dma9 - toSPR case 0x1000d400: // dma9 - toSPR
DMA_LOG("toSPRdma %lx", value); DMA_LOG("toSPRdma %lx", value);
DmaExec(dmaSPR1, mem, value); DmaExec(dmaSPR1, mem, value);
break; break;
//------------------------------------------------------------------
case 0x1000e000: // DMAC_CTRL case 0x1000e000: // DMAC_CTRL
HW_LOG("DMAC_CTRL Write 32bit %x", value); HW_LOG("DMAC_CTRL Write 32bit %x", value);
psHu32(0xe000) = value; psHu32(0xe000) = value;
@ -648,11 +672,10 @@ __forceinline void __fastcall hwWrite32(u32 mem, u32 value)
cpuTestDMACInts(); cpuTestDMACInts();
break; break;
//------------------------------------------------------------------
case 0x1000f000: // INTC_STAT case 0x1000f000: // INTC_STAT
HW_LOG("INTC_STAT Write 32bit %x", value); HW_LOG("INTC_STAT Write 32bit %x", value);
psHu32(0xf000)&=~value; psHu32(0xf000)&=~value;
//cpuTestINTCInts();
break; break;
case 0x1000f010: // INTC_MASK case 0x1000f010: // INTC_MASK
@ -660,7 +683,7 @@ __forceinline void __fastcall hwWrite32(u32 mem, u32 value)
psHu32(0xf010) ^= (u16)value; psHu32(0xf010) ^= (u16)value;
cpuTestINTCInts(); cpuTestINTCInts();
break; break;
//------------------------------------------------------------------
case 0x1000f430://MCH_RICM: x:4|SA:12|x:5|SDEV:1|SOP:4|SBC:1|SDEV:5 case 0x1000f430://MCH_RICM: x:4|SA:12|x:5|SDEV:1|SOP:4|SBC:1|SDEV:5
if ((((value >> 16) & 0xFFF) == 0x21) && (((value >> 6) & 0xF) == 1) && (((psHu32(0xf440) >> 7) & 1) == 0))//INIT & SRP=0 if ((((value >> 16) & 0xFFF) == 0x21) && (((value >> 6) & 0xF) == 1) && (((psHu32(0xf440) >> 7) & 1) == 0))//INIT & SRP=0
rdram_sdevid = 0; // if SIO repeater is cleared, reset sdevid rdram_sdevid = 0; // if SIO repeater is cleared, reset sdevid
@ -670,37 +693,41 @@ __forceinline void __fastcall hwWrite32(u32 mem, u32 value)
case 0x1000f440://MCH_DRD: case 0x1000f440://MCH_DRD:
psHu32(mem) = value; psHu32(mem) = value;
break; break;
//------------------------------------------------------------------
case 0x1000f590: // DMAC_ENABLEW case 0x1000f590: // DMAC_ENABLEW
HW_LOG("DMAC_ENABLEW Write 32bit %lx", value); HW_LOG("DMAC_ENABLEW Write 32bit %lx", value);
psHu32(0xf590) = value; psHu32(0xf590) = value;
psHu32(0xf520) = value; psHu32(0xf520) = value;
return; return;
//------------------------------------------------------------------
case 0x1000f200: case 0x1000f200:
psHu32(mem) = value; psHu32(mem) = value;
break; break;
case 0x1000f220: case 0x1000f220:
psHu32(mem) |= value; psHu32(mem) |= value;
break; break;
case 0x1000f230: case 0x1000f230:
psHu32(mem) &= ~value; psHu32(mem) &= ~value;
break; break;
case 0x1000f240: case 0x1000f240:
if(!(value & 0x100)) if(!(value & 0x100))
psHu32(mem) &= ~0x100; psHu32(mem) &= ~0x100;
else else
psHu32(mem) |= 0x100; psHu32(mem) |= 0x100;
break; break;
case 0x1000f260: case 0x1000f260:
psHu32(mem) = 0; psHu32(mem) = 0;
break; break;
//------------------------------------------------------------------
case 0x1000f130: case 0x1000f130:
case 0x1000f410: case 0x1000f410:
HW_LOG("Unknown Hardware write 32 at %x with value %x (%x)", mem, value, cpuRegs.CP0.n.Status.val); HW_LOG("Unknown Hardware write 32 at %x with value %x (%x)", mem, value, cpuRegs.CP0.n.Status.val);
break; break;
//------------------------------------------------------------------
default: default:
psHu32(mem) = value; psHu32(mem) = value;
HW_LOG("Unknown Hardware write 32 at %x with value %x (%x)", mem, value, cpuRegs.CP0.n.Status.val); HW_LOG("Unknown Hardware write 32 at %x with value %x (%x)", mem, value, cpuRegs.CP0.n.Status.val);
@ -710,7 +737,7 @@ __forceinline void __fastcall hwWrite32(u32 mem, u32 value)
#endif #endif
#if 0 /*
__forceinline void hwWrite64(u32 mem, u64 value) __forceinline void hwWrite64(u32 mem, u64 value)
{ {
u32 val32; u32 val32;
@ -846,4 +873,4 @@ __forceinline void hwWrite128(u32 mem, const u64 *value)
break; break;
} }
} }
#endif */

2
pcsx2/Hw.h
View File

@ -328,7 +328,7 @@ static __forceinline u8* dmaGetAddr(u32 mem)
#ifdef _WIN32 #ifdef _WIN32
// do manual LUT since IPU/SPR seems to use addrs 0x3000xxxx quite often // do manual LUT since IPU/SPR seems to use addrs 0x3000xxxx quite often
// linux doesn't suffer from this because it has better vm support // linux doesn't suffer from this because it has better vm support
if( memLUT[ (p-PS2MEM_BASE)>>12 ].aPFNs == NULL ) { if( memLUT[ (p-PS2MEM_BASE)>>12 ].aPFNs == NULL ) {
Console::WriteLn("dmaGetAddr: memLUT PFN warning"); Console::WriteLn("dmaGetAddr: memLUT PFN warning");
return NULL;//p; return NULL;//p;

54
pcsx2/SPR.cpp
View File

@ -98,7 +98,7 @@ void _SPR0interleave()
int qwc = spr0->qwc; int qwc = spr0->qwc;
int sqwc = psHu32(DMAC_SQWC) & 0xff; int sqwc = psHu32(DMAC_SQWC) & 0xff;
int tqwc = (psHu32(DMAC_SQWC) >> 16) & 0xff; int tqwc = (psHu32(DMAC_SQWC) >> 16) & 0xff;
int cycles = 0; //int cycles = 0;
u32 *pMem; u32 *pMem;
if (tqwc == 0) tqwc = qwc; if (tqwc == 0) tqwc = qwc;
@ -111,8 +111,8 @@ void _SPR0interleave()
spr0->qwc = std::min(tqwc, qwc); spr0->qwc = std::min(tqwc, qwc);
qwc -= spr0->qwc; qwc -= spr0->qwc;
pMem = (u32*)dmaGetAddr(spr0->madr); pMem = (u32*)dmaGetAddr(spr0->madr);
if ((psHu32(DMAC_CTRL) & 0xC) == 0xC || // GIF MFIFO if ((((psHu32(DMAC_CTRL) & 0xC) == 0xC) || // GIF MFIFO
(psHu32(DMAC_CTRL) & 0xC) == 0x8) // VIF1 MFIFO (psHu32(DMAC_CTRL) & 0xC) == 0x8)) // VIF1 MFIFO
{ {
hwMFIFOWrite(spr0->madr, (u8*)&PS2MEM_SCRATCH[spr0->sadr & 0x3fff], spr0->qwc << 4); hwMFIFOWrite(spr0->madr, (u8*)&PS2MEM_SCRATCH[spr0->sadr & 0x3fff], spr0->qwc << 4);
mfifotransferred += spr0->qwc; mfifotransferred += spr0->qwc;
@ -123,7 +123,7 @@ void _SPR0interleave()
TestClearVUs(spr0->madr, spr0->qwc << 2); TestClearVUs(spr0->madr, spr0->qwc << 2);
memcpy_fast((u8*)pMem, &PS2MEM_SCRATCH[spr0->sadr & 0x3fff], spr0->qwc << 4); memcpy_fast((u8*)pMem, &PS2MEM_SCRATCH[spr0->sadr & 0x3fff], spr0->qwc << 4);
} }
cycles += tqwc * BIAS; //cycles += tqwc * BIAS;
spr0->sadr += spr0->qwc * 16; spr0->sadr += spr0->qwc * 16;
spr0->madr += (sqwc + spr0->qwc) * 16; //qwc-= sqwc; spr0->madr += (sqwc + spr0->qwc) * 16; //qwc-= sqwc;
} }
@ -153,7 +153,7 @@ static __forceinline void _dmaSPR0()
int cycles = 0; int cycles = 0;
u32 *ptag; u32 *ptag;
int id; int id;
int done = 0; bool done = FALSE;
if (spr0->qwc > 0) if (spr0->qwc > 0)
{ {
@ -169,7 +169,7 @@ static __forceinline void _dmaSPR0()
spr0->chcr = (spr0->chcr & 0xFFFF) | ((*ptag) & 0xFFFF0000); //Transfer upper part of tag to CHCR bits 31-15 spr0->chcr = (spr0->chcr & 0xFFFF) | ((*ptag) & 0xFFFF0000); //Transfer upper part of tag to CHCR bits 31-15
id = (ptag[0] >> 28) & 0x7; //ID for DmaChain copied from bit 28 of the tag id = (ptag[0] >> 28) & 0x7; //ID for DmaChain copied from bit 28 of the tag
spr0->qwc = (u16)ptag[0]; //QWC set to lower 16bits of the tag spr0->qwc = (u16)ptag[0]; //QWC set to lower 16bits of the tag
spr0->madr = ptag[1]; //MADR = ADDR field spr0->madr = ptag[1]; //MADR = ADDR field
@ -188,27 +188,28 @@ static __forceinline void _dmaSPR0()
break; break;
case 1: // CNT - Transfer QWC following the tag. case 1: // CNT - Transfer QWC following the tag.
done = 0; done = FALSE;
break; break;
case 7: // End - Transfer QWC following the tag case 7: // End - Transfer QWC following the tag
done = 1; //End Transfer done = TRUE;
break; break;
} }
SPR0chain(); SPR0chain();
if (spr0->chcr & 0x80 && ptag[0] >> 31) //Check TIE bit of CHCR and IRQ bit of tag if (spr0->chcr & 0x80 && ptag[0] >> 31) //Check TIE bit of CHCR and IRQ bit of tag
{ {
//Console::WriteLn("SPR0 TIE"); //Console::WriteLn("SPR0 TIE");
done = 1; done = TRUE;
spr0->qwc = 0; spr0->qwc = 0;
} }
spr0finished = (done) ? 1 : 0;
spr0finished = done; if (!done)
if (done == 0)
{ {
ptag = (u32*) & PS2MEM_SCRATCH[spr0->sadr & 0x3fff]; //Set memory pointer to SADR ptag = (u32*) & PS2MEM_SCRATCH[spr0->sadr & 0x3fff]; //Set memory pointer to SADR
spr0->qwc = (u16)ptag[0]; //QWC set to lower 16bits of the tag //spr0->qwc = (u16)ptag[0]; //QWC set to lower 16bits of the tag
CPU_INT(8, spr0->qwc / BIAS); CPU_INT(8, ((u16)ptag[0]) / BIAS); //spr0->qwc / BIAS);
spr0->qwc = 0; spr0->qwc = 0;
return; return;
} }
@ -219,9 +220,6 @@ static __forceinline void _dmaSPR0()
{ {
_SPR0interleave(); _SPR0interleave();
} }
} }
void SPRFROMinterrupt() void SPRFROMinterrupt()
@ -253,8 +251,6 @@ void SPRFROMinterrupt()
void dmaSPR0() // fromSPR void dmaSPR0() // fromSPR
{ {
SPR_LOG("dmaSPR0 chcr = %lx, madr = %lx, qwc = %lx, sadr = %lx", SPR_LOG("dmaSPR0 chcr = %lx, madr = %lx, qwc = %lx, sadr = %lx",
spr0->chcr, spr0->madr, spr0->qwc, spr0->sadr); spr0->chcr, spr0->madr, spr0->qwc, spr0->sadr);
@ -303,7 +299,7 @@ void _SPR1interleave()
int qwc = spr1->qwc; int qwc = spr1->qwc;
int sqwc = psHu32(DMAC_SQWC) & 0xff; int sqwc = psHu32(DMAC_SQWC) & 0xff;
int tqwc = (psHu32(DMAC_SQWC) >> 16) & 0xff; int tqwc = (psHu32(DMAC_SQWC) >> 16) & 0xff;
int cycles = 0; //int cycles = 0;
u32 *pMem; u32 *pMem;
if (tqwc == 0) tqwc = qwc; if (tqwc == 0) tqwc = qwc;
@ -317,7 +313,7 @@ void _SPR1interleave()
pMem = (u32*)dmaGetAddr(spr1->madr); pMem = (u32*)dmaGetAddr(spr1->madr);
memcpy_fast(&PS2MEM_SCRATCH[spr1->sadr & 0x3fff], (u8*)pMem, spr1->qwc << 4); memcpy_fast(&PS2MEM_SCRATCH[spr1->sadr & 0x3fff], (u8*)pMem, spr1->qwc << 4);
spr1->sadr += spr1->qwc * 16; spr1->sadr += spr1->qwc * 16;
cycles += spr1->qwc * BIAS; //cycles += spr1->qwc * BIAS;
spr1->madr += (sqwc + spr1->qwc) * 16; //qwc-= sqwc; spr1->madr += (sqwc + spr1->qwc) * 16; //qwc-= sqwc;
} }
@ -339,7 +335,8 @@ void _dmaSPR1() // toSPR work function
{ {
int cycles = 0; int cycles = 0;
u32 *ptag; u32 *ptag;
int id, done = 0; int id;
bool done = FALSE;
if (spr1->qwc > 0) if (spr1->qwc > 0)
{ {
@ -356,8 +353,8 @@ void _dmaSPR1() // toSPR work function
Console::WriteLn("SPR1 Tag BUSERR"); Console::WriteLn("SPR1 Tag BUSERR");
spr1->chcr = (spr1->chcr & 0xFFFF) | ((*ptag) & 0xFFFF0000); //Transfer upper part of tag to CHCR bits 31-15 spr1->chcr = (spr1->chcr & 0xFFFF) | ((*ptag) & 0xFFFF0000); //Transfer upper part of tag to CHCR bits 31-15
psHu32(DMAC_STAT) |= 1 << 15; //If yes, set BEIS (BUSERR) in DMAC_STAT register psHu32(DMAC_STAT) |= 1 << 15; //If yes, set BEIS (BUSERR) in DMAC_STAT register
done = 1; done = TRUE;
spr1finished = done; spr1finished = (done) ? 1: 0;
return; return;
} }
spr1->chcr = (spr1->chcr & 0xFFFF) | ((*ptag) & 0xFFFF0000); //Transfer upper part of tag to CHCR bits 31-15 spr1->chcr = (spr1->chcr & 0xFFFF) | ((*ptag) & 0xFFFF0000); //Transfer upper part of tag to CHCR bits 31-15
@ -376,7 +373,7 @@ void _dmaSPR1() // toSPR work function
SPR_LOG("spr1 dmaChain %8.8x_%8.8x size=%d, id=%d, addr=%lx", SPR_LOG("spr1 dmaChain %8.8x_%8.8x size=%d, id=%d, addr=%lx",
ptag[1], ptag[0], spr1->qwc, id, spr1->madr); ptag[1], ptag[0], spr1->qwc, id, spr1->madr);
done = hwDmacSrcChain(spr1, id); done = (hwDmacSrcChain(spr1, id) == 1);
SPR1chain(); //Transfers the data set by the switch SPR1chain(); //Transfers the data set by the switch
if (spr1->chcr & 0x80 && ptag[0] >> 31) //Check TIE bit of CHCR and IRQ bit of tag if (spr1->chcr & 0x80 && ptag[0] >> 31) //Check TIE bit of CHCR and IRQ bit of tag
@ -385,15 +382,15 @@ void _dmaSPR1() // toSPR work function
//Console::WriteLn("SPR1 TIE"); //Console::WriteLn("SPR1 TIE");
spr1->qwc = 0; spr1->qwc = 0;
done = 1; done = TRUE;
} }
spr1finished = done; spr1finished = done;
if (done == 0) if (!done)
{ {
ptag = (u32*)dmaGetAddr(spr1->tadr); //Set memory pointer to TADR ptag = (u32*)dmaGetAddr(spr1->tadr); //Set memory pointer to TADR
spr1->qwc = (u16)ptag[0]; //QWC set to lower 16bits of the tag //spr1->qwc = (u16)ptag[0]; //QWC set to lower 16bits of the tag
CPU_INT(9, spr1->qwc / BIAS); CPU_INT(9, (((u16)ptag[0]) / BIAS));// spr1->qwc / BIAS);
spr1->qwc = 0; spr1->qwc = 0;
} }
} }
@ -416,7 +413,6 @@ void dmaSPR1() // toSPR
u32 *ptag; u32 *ptag;
ptag = (u32*)dmaGetAddr(spr1->tadr); //Set memory pointer to TADR ptag = (u32*)dmaGetAddr(spr1->tadr); //Set memory pointer to TADR
CPU_INT(9, (ptag[0] & 0xffff) / BIAS); CPU_INT(9, (ptag[0] & 0xffff) / BIAS);
//spr1->qwc = 0;
return; return;
} }
// COMPLETE HACK!!! For now at least.. FFX Videos dont rely on interrupts or reading DMA values // COMPLETE HACK!!! For now at least.. FFX Videos dont rely on interrupts or reading DMA values

92
pcsx2/Sif.cpp
View File

@ -40,26 +40,26 @@ DMACh *sif2ch;
struct _sif0 struct _sif0
{ {
u32 fifoData[FIFO_SIF0_W]; u32 fifoData[FIFO_SIF0_W];
int fifoReadPos; s32 fifoReadPos;
int fifoWritePos; s32 fifoWritePos;
int fifoSize; s32 fifoSize;
int chain; s32 chain;
int end; s32 end;
int tagMode; s32 tagMode;
int counter; s32 counter;
struct sifData sifData; struct sifData sifData;
}; };
struct _sif1 struct _sif1
{ {
u32 fifoData[FIFO_SIF1_W]; u32 fifoData[FIFO_SIF1_W];
int fifoReadPos; s32 fifoReadPos;
int fifoWritePos; s32 fifoWritePos;
int fifoSize; s32 fifoSize;
int chain; s32 chain;
int end; s32 end;
int tagMode; s32 tagMode;
int counter; s32 counter;
}; };
static _sif0 sif0; static _sif0 sif0;
@ -85,7 +85,6 @@ static __forceinline void SIF0write(u32 *from, int words)
memcpy(&sif0.fifoData[0], &from[wP0], wP1 << 2); memcpy(&sif0.fifoData[0], &from[wP0], wP1 << 2);
sif0.fifoWritePos = (sif0.fifoWritePos + words) & (FIFO_SIF0_W - 1); sif0.fifoWritePos = (sif0.fifoWritePos + words) & (FIFO_SIF0_W - 1);
sif0.fifoSize += words; sif0.fifoSize += words;
SIF_LOG(" SIF0 + %d = %d (pos=%d)", words, sif0.fifoSize, sif0.fifoWritePos); SIF_LOG(" SIF0 + %d = %d (pos=%d)", words, sif0.fifoSize, sif0.fifoWritePos);
} }
@ -132,7 +131,7 @@ static __forceinline void SIF1read(u32 *to, int words)
__forceinline void SIF0Dma() __forceinline void SIF0Dma()
{ {
u32 *ptag; u32 *ptag;
int notDone = TRUE; bool done = FALSE;
int cycles = 0, psxCycles = 0; int cycles = 0, psxCycles = 0;
SIF_LOG("SIF0 DMA start..."); SIF_LOG("SIF0 DMA start...");
@ -157,7 +156,7 @@ __forceinline void SIF0Dma()
PSX_INT(IopEvt_SIF0, psxCycles); PSX_INT(IopEvt_SIF0, psxCycles);
sif0.sifData.data = 0; sif0.sifData.data = 0;
notDone = FALSE; done = TRUE;
} }
else // Chain mode else // Chain mode
{ {
@ -171,13 +170,13 @@ __forceinline void SIF0Dma()
HW_DMA9_MADR = sif0.sifData.data & 0xFFFFFF; HW_DMA9_MADR = sif0.sifData.data & 0xFFFFFF;
HW_DMA9_TADR += 16; ///HW_DMA9_MADR + 16 + sif0.sifData.words << 2; HW_DMA9_TADR += 16; ///HW_DMA9_MADR + 16 + sif0.sifData.words << 2;
sif0.counter = sif0.sifData.words & 0xFFFFFF; sif0.counter = sif0.sifData.words & 0xFFFFFF;
notDone = TRUE;
SIF_LOG(" SIF0 Tag: madr=%lx, tadr=%lx, counter=%lx (%08X_%08X)", HW_DMA9_MADR, HW_DMA9_TADR, sif0.counter, sif0.sifData.words, sif0.sifData.data); SIF_LOG(" SIF0 Tag: madr=%lx, tadr=%lx, counter=%lx (%08X_%08X)", HW_DMA9_MADR, HW_DMA9_TADR, sif0.counter, sif0.sifData.words, sif0.sifData.data);
if (sif0.sifData.data & 0x40000000) if (sif0.sifData.data & 0x40000000)
SIF_LOG(" END"); SIF_LOG(" END");
else else
SIF_LOG(" CNT %08X, %08X", sif0.sifData.data, sif0.sifData.words); SIF_LOG(" CNT %08X, %08X", sif0.sifData.data, sif0.sifData.words);
done = FALSE;
} }
} }
else // There's some data ready to transfer into the fifo.. else // There's some data ready to transfer into the fifo..
@ -220,23 +219,16 @@ __forceinline void SIF0Dma()
if (sif0dma->qwc == 0) if (sif0dma->qwc == 0)
{ {
if ((sif0dma->chcr & 0x80000080) == 0x80000080) // Stop on tag IRQ if (((sif0dma->chcr & 0x80000080) == 0x80000080) || (sif0.end)) // Stop on tag IRQ or END
{ {
// Tag interrupt if (sif0.end)
SIF_LOG(" EE SIF interrupt"); SIF_LOG(" EE SIF end");
else
SIF_LOG(" EE SIF interrupt");
eesifbusy[0] = 0; eesifbusy[0] = 0;
CPU_INT(5, cycles*BIAS); CPU_INT(5, cycles*BIAS);
notDone = FALSE; done = TRUE;
}
else if (sif0.end) // Stop on tag END
{
// End tag.
SIF_LOG(" EE SIF end");
eesifbusy[0] = 0;
CPU_INT(5, cycles*BIAS);
notDone = FALSE;
} }
else if (sif0.fifoSize >= 4) // Read a tag else if (sif0.fifoSize >= 4) // Read a tag
{ {
@ -252,22 +244,22 @@ __forceinline void SIF0Dma()
if ((psHu32(DMAC_CTRL) & 0x30) != 0 && ((tag[0] >> 28)&3) == 0) if ((psHu32(DMAC_CTRL) & 0x30) != 0 && ((tag[0] >> 28)&3) == 0)
psHu32(DMAC_STADR) = sif0dma->madr + (sif0dma->qwc * 16); psHu32(DMAC_STADR) = sif0dma->madr + (sif0dma->qwc * 16);
notDone = TRUE;
sif0.chain = 1; sif0.chain = 1;
if (tag[0] & 0x40000000) sif0.end = 1; if (tag[0] & 0x40000000) sif0.end = 1;
done = FALSE;
} }
} }
} }
} }
while (notDone); while (!done);
} }
__forceinline void SIF1Dma() __forceinline void SIF1Dma()
{ {
int id; int id;
u32 *ptag; u32 *ptag;
bool notDone = true; bool done = FALSE;
int cycles = 0, psxCycles = 0; int cycles = 0, psxCycles = 0;
do do
{ {
@ -284,7 +276,7 @@ __forceinline void SIF1Dma()
// Stop & signal interrupts on EE // Stop & signal interrupts on EE
SIF_LOG("EE SIF1 End %x", sif1.end); SIF_LOG("EE SIF1 End %x", sif1.end);
eesifbusy[1] = 0; eesifbusy[1] = 0;
notDone = FALSE; done = TRUE;
CPU_INT(6, cycles*BIAS); CPU_INT(6, cycles*BIAS);
sif1.chain = 0; sif1.chain = 0;
sif1.end = 0; sif1.end = 0;
@ -292,7 +284,7 @@ __forceinline void SIF1Dma()
else // Chain mode else // Chain mode
{ {
// Process DMA tag at sif1dma->tadr // Process DMA tag at sif1dma->tadr
notDone = TRUE; done = FALSE;
_dmaGetAddr(sif1dma, ptag, sif1dma->tadr, 6); _dmaGetAddr(sif1dma, ptag, sif1dma->tadr, 6);
sif1dma->chcr = (sif1dma->chcr & 0xFFFF) | ((*ptag) & 0xFFFF0000); // Copy the tag sif1dma->chcr = (sif1dma->chcr & 0xFFFF) | ((*ptag) & 0xFFFF0000); // Copy the tag
sif1dma->qwc = (u16)ptag[0]; sif1dma->qwc = (u16)ptag[0];
@ -390,23 +382,17 @@ __forceinline void SIF1Dma()
if (sif1.counter <= 0) if (sif1.counter <= 0)
{ {
if (sif1.tagMode & 0x80) // Stop on tag IRQ if ((sif1.tagMode & 0x80) || (sif1.tagMode & 0x40)) // Stop on tag IRQ or END
{ {
// Tag interrupt if (sif1.tagMode & 0x40)
SIF_LOG(" IOP SIF interrupt"); SIF_LOG(" IOP SIF end");
else
SIF_LOG(" IOP SIF interrupt");
iopsifbusy[1] = 0; iopsifbusy[1] = 0;
PSX_INT(IopEvt_SIF1, psxCycles); PSX_INT(IopEvt_SIF1, psxCycles);
sif1.tagMode = 0; sif1.tagMode = 0;
notDone = FALSE; done = TRUE;
}
else if (sif1.tagMode & 0x40) // Stop on tag END
{
// End tag.
SIF_LOG(" IOP SIF end");
iopsifbusy[1] = 0;
PSX_INT(IopEvt_SIF1, psxCycles);
sif1.tagMode = 0;
notDone = FALSE;
} }
else if (sif1.fifoSize >= 4) // Read a tag else if (sif1.fifoSize >= 4) // Read a tag
{ {
@ -416,12 +402,12 @@ __forceinline void SIF1Dma()
HW_DMA10_MADR = d.data & 0xffffff; HW_DMA10_MADR = d.data & 0xffffff;
sif1.counter = d.words; sif1.counter = d.words;
sif1.tagMode = (d.data >> 24) & 0xFF; sif1.tagMode = (d.data >> 24) & 0xFF;
notDone = TRUE; done = FALSE;
} }
} }
} }
} }
while (notDone); while (!done);
} }
__forceinline void sif0Interrupt() __forceinline void sif0Interrupt()
@ -460,7 +446,7 @@ __forceinline void dmaSIF0()
psHu32(0x1000F240) |= 0x2000; psHu32(0x1000F240) |= 0x2000;
eesifbusy[0] = 1; eesifbusy[0] = 1;
if (eesifbusy[0] == 1 && iopsifbusy[0] == 1) if (iopsifbusy[0] == 1)
{ {
FreezeXMMRegs(1); FreezeXMMRegs(1);
hwIntcIrq(INTC_SBUS); hwIntcIrq(INTC_SBUS);
@ -483,7 +469,7 @@ __forceinline void dmaSIF1()
psHu32(0x1000F240) |= 0x4000; psHu32(0x1000F240) |= 0x4000;
eesifbusy[1] = 1; eesifbusy[1] = 1;
if (eesifbusy[1] == 1 && iopsifbusy[1] == 1) if (iopsifbusy[1] == 1)
{ {
FreezeXMMRegs(1); FreezeXMMRegs(1);
SIF1Dma(); SIF1Dma();

11
pcsx2/Sif.h
View File

@ -19,11 +19,12 @@
#ifndef __SIF_H__ #ifndef __SIF_H__
#define __SIF_H__ #define __SIF_H__
struct sifData{ struct sifData
int data, {
words, s32 data;
count, s32 words;
addr; s32 count;
s32 addr;
}; };
extern DMACh *sif0ch; extern DMACh *sif0ch;

189
pcsx2/Sifcmd.h
View File

@ -25,46 +25,49 @@
struct t_sif_cmd_header struct t_sif_cmd_header
{ {
u32 size; u32 size;
void *dest; void *dest;
int command; s32 command;
u32 unknown; u32 unknown;
}; };
struct t_sif_dma_transfer struct t_sif_dma_transfer
{ {
void *src, void *src;
*dest; void *dest;
int size; s32 size;
int attr; s32 attr;
}; };
struct t_sif_handler struct t_sif_handler
{ {
void (*handler) ( void *a, void *b); void (*handler)(void *a, void *b);
void *buff; void *buff;
}; };
#define SYSTEM_CMD_CHANGE_SADDR 0x80000000 #define SYSTEM_CMD_CHANGE_SADDR 0x80000000
#define SYSTEM_CMD_INIT_CMD 0x80000002 #define SYSTEM_CMD_INIT_CMD 0x80000002
struct t_sif_saddr{ struct t_sif_saddr
{
struct t_sif_cmd_header hdr; //+00 struct t_sif_cmd_header hdr; //+00
void *newaddr; //+10 void *newaddr; //+10
}; //=14 }; //=14
#define SYSTEM_CMD_SET_SREG 0x80000001 #define SYSTEM_CMD_SET_SREG 0x80000001
struct t_sif_sreg{ struct t_sif_sreg
{
struct t_sif_cmd_header hdr; //+00 struct t_sif_cmd_header hdr; //+00
int index; //+10 s32 index; //+10
unsigned int value; //+14 u32value; //+14
}; //=18 }; //=18
#define SYSTEM_CMD_RESET 0x80000003 #define SYSTEM_CMD_RESET 0x80000003
struct t_sif_reset{ struct t_sif_reset
{
struct t_sif_cmd_header hdr; //+00 struct t_sif_cmd_header hdr; //+00
int size, //+10 s32 size; //+10
flag; //+14 s32 flag; //+14
char data[80]; //+18 char data[80]; //+18
}; //=68 }; //=68
/* end of sifcmd.h */ /* end of sifcmd.h */
@ -73,119 +76,119 @@ struct t_sif_reset{
struct t_sif_rpc_rend struct t_sif_rpc_rend
{ {
struct t_sif_cmd_header sifcmd; struct t_sif_cmd_header sifcmd;
int rec_id; /* 04 */ s32 rec_id; /* 04 */
void *pkt_addr; /* 05 */ void *pkt_addr; /* 05 */
int rpc_id; /* 06 */ s32 rpc_id; /* 06 */
struct t_rpc_client_data *client; /* 7 */ struct t_rpc_client_data *client; /* 7 */
u32 command; /* 8 */ u32 command; /* 8 */
struct t_rpc_server_data *server; /* 9 */ struct t_rpc_server_data *server; /* 9 */
void *buff, /* 10 */ void *buff; /* 10 */
*buff2; /* 11 */ void *buff2; /* 11 */
}; };
struct t_sif_rpc_other_data struct t_sif_rpc_other_data
{ {
struct t_sif_cmd_header sifcmd; struct t_sif_cmd_header sifcmd;
int rec_id; /* 04 */ s32 rec_id; /* 04 */
void *pkt_addr; /* 05 */ void *pkt_addr; /* 05 */
int rpc_id; /* 06 */ s32 rpc_id; /* 06 */
struct t_rpc_receive_data *receive; /* 07 */ struct t_rpc_receive_data *receive; /* 07 */
void *src; /* 08 */ void *src; /* 08 */
void *dest; /* 09 */ void *dest; /* 09 */
int size; /* 10 */ s32 size; /* 10 */
}; };
struct t_sif_rpc_bind struct t_sif_rpc_bind
{ {
struct t_sif_cmd_header sifcmd; struct t_sif_cmd_header sifcmd;
int rec_id; /* 04 */ s32 rec_id; /* 04 */
void *pkt_addr; /* 05 */ void *pkt_addr; /* 05 */
int rpc_id; /* 06 */ s32 rpc_id; /* 06 */
struct t_rpc_client_data *client; /* 07 */ struct t_rpc_client_data *client; /* 07 */
int rpc_number; /* 08 */ s32 rpc_number; /* 08 */
}; };
struct t_sif_rpc_call struct t_sif_rpc_call
{ {
struct t_sif_cmd_header sifcmd; struct t_sif_cmd_header sifcmd;
int rec_id; /* 04 */ s32 rec_id; /* 04 */
void *pkt_addr; /* 05 */ void *pkt_addr; /* 05 */
int rpc_id; /* 06 */ s32 rpc_id; /* 06 */
struct t_rpc_client_data *client; /* 07 */ struct t_rpc_client_data *client; /* 07 */
int rpc_number; /* 08 */ s32 rpc_number; /* 08 */
int send_size; /* 09 */ s32 send_size; /* 09 */
void *receive; /* 10 */ void *receive; /* 10 */
int rec_size; /* 11 */ s32 rec_size; /* 11 */
int has_async_ef; /* 12 */ s32 has_async_ef; /* 12 */
struct t_rpc_server_data *server; /* 13 */ struct t_rpc_server_data *server; /* 13 */
}; };
struct t_rpc_server_data struct t_rpc_server_data
{ {
int command; /* 04 00 */ s32 command; /* 04 00 */
void * (*func)(u32, void *, int); /* 05 01 */ void *(*func)(u32, void *, int); /* 05 01 */
void *buff; /* 06 02 */ void *buff; /* 06 02 */
int size; /* 07 03 */ s32 size; /* 07 03 */
void * (*func2)(u32, void *, int); /* 08 04 */ void *(*func2)(u32, void *, int); /* 08 04 */
void *buff2; /* 09 05 */ void *buff2; /* 09 05 */
int size2; /* 10 06 */ s32 size2; /* 10 06 */
struct t_rpc_client_data *client; /* 11 07 */ struct t_rpc_client_data *client; /* 11 07 */
void *pkt_addr; /* 12 08 */ void *pkt_addr; /* 12 08 */
int rpc_number; /* 13 09 */ s32 rpc_number; /* 13 09 */
void *receive; /* 14 10 */ void *receive; /* 14 10 */
int rec_size; /* 15 11 */ s32 rec_size; /* 15 11 */
int has_async_ef; /* 16 12 */ s32 has_async_ef; /* 16 12 */
int rec_id; /* 17 13 */ s32 rec_id; /* 17 13 */
struct t_rpc_server_data *link; /* 18 14 */ struct t_rpc_server_data *link; /* 18 14 */
struct r_rpc_server_data *next; /* 19 15 */ struct r_rpc_server_data *next; /* 19 15 */
struct t_rpc_data_queue *queued_object; /* 20 16 */ struct t_rpc_data_queue *queued_object; /* 20 16 */
}; };
struct t_rpc_header struct t_rpc_header
{ {
void *pkt_addr; /* 04 00 */ void *pkt_addr; /* 04 00 */
u32 rpc_id; /* 05 01 */ u32 rpc_id; /* 05 01 */
int sema_id; /* 06 02 */ s32 sema_id; /* 06 02 */
u32 mode; /* 07 03 */ u32 mode; /* 07 03 */
}; };
struct t_rpc_client_data struct t_rpc_client_data
{ {
struct t_rpc_header hdr; struct t_rpc_header hdr;
u32 command; /* 04 08 */ u32 command; /* 04 08 */
void *buff, /* 05 09 */ void *buff; /* 05 09 */
*buff2; /* 06 10 */ void *buff2; /* 06 10 */
void (*end_function) ( void *); /* 07 11 */ void (*end_function)(void *); /* 07 11 */
void *end_param; /* 08 12*/ void *end_param; /* 08 12*/
struct t_rpc_server_data *server; /* 09 13 */ struct t_rpc_server_data *server; /* 09 13 */
}; };
struct t_rpc_receive_data struct t_rpc_receive_data
{ {
struct t_rpc_header hdr; struct t_rpc_header hdr;
void *src, /* 04 */ void *src; /* 04 */
*dest; /* 05 */ void *dest; /* 05 */
int size; /* 06 */ s32 size; /* 06 */
}; };
struct t_rpc_data_queue struct t_rpc_data_queue
{ {
int thread_id, /* 00 */ s32 thread_id; /* 00 */
active; /* 01 */ s32 active; /* 01 */
struct t_rpc_server_data *svdata_ref, /* 02 */ struct t_rpc_server_data *svdata_ref; /* 02 */
*start, /* 03 */ struct t_rpc_server_data *start; /* 03 */
*end; /* 04 */ struct t_rpc_server_data *end; /* 04 */
struct t_rpc_data_queue *next; /* 05 */ struct t_rpc_data_queue *next; /* 05 */
}; };
/* end of sifrpc.h */ /* end of sifrpc.h */

6
pcsx2/VifDma.cpp
View File

@ -446,13 +446,9 @@ static void VIFunpack(u32 *data, vifCode *v, int size, const unsigned int VIFdma
if (vif->cl == vifRegs->cycle.wl) if (vif->cl == vifRegs->cycle.wl)
{ {
if (vifRegs->cycle.cl != vifRegs->cycle.wl) if (vifRegs->cycle.cl != vifRegs->cycle.wl)
{
dest += ((vifRegs->cycle.cl - vifRegs->cycle.wl) << 2) + destinc; dest += ((vifRegs->cycle.cl - vifRegs->cycle.wl) << 2) + destinc;
}
else else
{
dest += destinc; dest += destinc;
}
vif->cl = 0; vif->cl = 0;
} }
else else
@ -539,7 +535,7 @@ static void VIFunpack(u32 *data, vifCode *v, int size, const unsigned int VIFdma
} }
#endif #endif
if (vifRegs->cycle.cl == 0 || vifRegs->cycle.wl == 0 || (vifRegs->cycle.cl == vifRegs->cycle.wl && !(vifRegs->code&0x10000000))) if ((vifRegs->cycle.cl == 0) || (vifRegs->cycle.wl == 0) || ((vifRegs->cycle.cl == vifRegs->cycle.wl) && !(vifRegs->code & 0x10000000)))
{ {
oldcycle = *(u32*) & vifRegs->cycle; oldcycle = *(u32*) & vifRegs->cycle;
vifRegs->cycle.cl = vifRegs->cycle.wl = 1; vifRegs->cycle.cl = vifRegs->cycle.wl = 1;