mirror of https://github.com/PCSX2/pcsx2.git
Made some minor tweaks to SIF to test some theories and fix some broken-looking code -- please report any regressions. Also commented some of SIF and IPU stuff. :)
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@3812 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
Jake.Stine
parent
d06838c4a5
commit
5fd2cf97d3
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@ -161,7 +161,7 @@ union u128
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bool operator!=( const u128& right ) const
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{
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return (lo != right.lo) && (hi != right.hi);
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return (lo != right.lo) || (hi != right.hi);
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}
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// In order for the following ToString() and WriteTo methods to be available, you must
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@ -206,7 +206,7 @@ struct s128
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bool operator!=( const s128& right ) const
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{
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return (lo != right.lo) && (hi != right.hi);
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return (lo != right.lo) || (hi != right.hi);
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}
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};
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@ -92,6 +92,8 @@ union tDMA_TAG {
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};
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u32 _u32;
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tDMA_TAG() {}
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tDMA_TAG(u32 val) { _u32 = val; }
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u16 upper() const { return (_u32 >> 16); }
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u16 lower() const { return (u16)_u32; }
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@ -206,7 +206,7 @@ __fi u32 ipuRead32(u32 mem)
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if (!ipuRegs.ctrl.BUSY)
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IPU_LOG("read32: IPU_CTRL=0x%08X", ipuRegs.ctrl._u32);
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return ipuRegs.ctrl._u32;
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return ipuRegs.ctrl._u32;
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}
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ipucase(IPU_BP): // IPU_BP
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@ -218,7 +218,7 @@ __fi u32 ipuRead32(u32 mem)
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ipuRegs.ipubp |= g_BP.FP << 16;
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IPU_LOG("read32: IPU_BP=0x%08X", ipuRegs.ipubp);
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return ipuRegs.ipubp;
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return ipuRegs.ipubp;
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}
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default:
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@ -448,6 +448,14 @@ static bool __fastcall ipuVDEC(u32 val)
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jNO_DEFAULT
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}
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// HACK ATTACK! This code OR's the MPEG decoder's bitstream position into the upper
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// 16 bits of DATA; which really doesn't make sense since (a) we already rewound the bits
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// back into the IPU internal buffer above, and (b) the IPU doesn't have an MPEG internal
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// 32-bit decoder buffer of its own anyway. Furthermore, setting the upper 16 bits to
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// any value other than zero appears to work fine. When set to zero, however, FMVs run
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// very choppy (basically only decoding/updating every 30th frame or so). So yeah,
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// someone with knowledge on the subject please feel free to explain this one. :) --air
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ipuRegs.cmd.DATA &= 0xFFFF;
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ipuRegs.cmd.DATA |= 0x10000;
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@ -466,6 +474,7 @@ static bool __fastcall ipuVDEC(u32 val)
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IPU_LOG("VDEC command data 0x%x(0x%x). Skip 0x%X bits/Table=%d (%s), pct %d",
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ipuRegs.cmd.DATA, ipuRegs.cmd.DATA >> 16, val & 0x3f, (val >> 26) & 3, (val >> 26) & 1 ?
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((val >> 26) & 2 ? "DMV" : "MBT") : (((val >> 26) & 2 ? "MC" : "MBAI")), ipuRegs.ctrl.PCT);
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return true;
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jNO_DEFAULT
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@ -488,8 +497,6 @@ static __fi bool ipuFDEC(u32 val)
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static bool ipuSETIQ(u32 val)
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{
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int i;
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if ((val >> 27) & 1)
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{
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u8 (&niq)[64] = decoder.niq;
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@ -500,7 +507,7 @@ static bool ipuSETIQ(u32 val)
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}
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IPU_LOG("Read non-intra quantization matrix from FIFO.");
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for (i = 0; i < 8; i++)
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for (uint i = 0; i < 8; i++)
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{
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IPU_LOG("%02X %02X %02X %02X %02X %02X %02X %02X",
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niq[i * 8 + 0], niq[i * 8 + 1], niq[i * 8 + 2], niq[i * 8 + 3],
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@ -517,7 +524,7 @@ static bool ipuSETIQ(u32 val)
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}
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IPU_LOG("Read intra quantization matrix from FIFO.");
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for (i = 0; i < 8; i++)
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for (uint i = 0; i < 8; i++)
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{
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IPU_LOG("%02X %02X %02X %02X %02X %02X %02X %02X",
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iq[i * 8 + 0], iq[i * 8 + 1], iq[i * 8 + 2], iq[i *8 + 3],
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@ -539,7 +546,7 @@ static bool ipuSETVQ(u32 val)
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"%02d:%02d:%02d %02d:%02d:%02d %02d:%02d:%02d %02d:%02d:%02d\n"
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"%02d:%02d:%02d %02d:%02d:%02d %02d:%02d:%02d %02d:%02d:%02d\n"
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"%02d:%02d:%02d %02d:%02d:%02d %02d:%02d:%02d %02d:%02d:%02d\n"
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"%02d:%02d:%02d %02d:%02d:%02d %02d:%02d:%02d %02d:%02d:%02d",
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"%02d:%02d:%02d %02d:%02d:%02d %02d:%02d:%02d %02d:%02d:%02d",
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vqclut[0] >> 10, (vqclut[0] >> 5) & 0x1F, vqclut[0] & 0x1F,
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vqclut[1] >> 10, (vqclut[1] >> 5) & 0x1F, vqclut[1] & 0x1F,
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vqclut[2] >> 10, (vqclut[2] >> 5) & 0x1F, vqclut[2] & 0x1F,
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@ -195,14 +195,8 @@ void psxDma9(u32 madr, u32 bcr, u32 chcr)
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SIF_LOG("IOP: dmaSIF0 chcr = %lx, madr = %lx, bcr = %lx, tadr = %lx", chcr, madr, bcr, HW_DMA9_TADR);
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sif0.iop.busy = true;
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psHu32(SBUS_F240) |= 0x2000;
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/*if (sif0.ee.busy)
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{*/
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SIF0Dma();
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psHu32(SBUS_F240) &= ~0x20;
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psHu32(SBUS_F240) &= ~0x2000;
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//}
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SIF0Dma();
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}
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void psxDma10(u32 madr, u32 bcr, u32 chcr)
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@ -210,15 +204,8 @@ void psxDma10(u32 madr, u32 bcr, u32 chcr)
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SIF_LOG("IOP: dmaSIF1 chcr = %lx, madr = %lx, bcr = %lx", chcr, madr, bcr);
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sif1.iop.busy = true;
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psHu32(SBUS_F240) |= 0x4000;
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/*if (sif1.ee.busy)
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{*/
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SIF1Dma();
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psHu32(SBUS_F240) &= ~0x40;
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psHu32(SBUS_F240) &= ~0x100;
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psHu32(SBUS_F240) &= ~0x4000;
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//}
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SIF1Dma();
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}
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/* psxDma11 & psxDma 12 are in IopSio2.cpp, along with the appropriate interrupt functions. */
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12
pcsx2/Sif.h
12
pcsx2/Sif.h
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@ -22,13 +22,17 @@ static DMACh& sif0dma = (DMACh&)eeHw[0xc000];
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static DMACh& sif1dma = (DMACh&)eeHw[0xc400];
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static DMACh& sif2dma = (DMACh&)eeHw[0xc800];
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// Despite its name, this is actually the IOP's DMAtag, which itself also contains
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// the EE's DMAtag in its upper 64 bits. Note that only the lower 24 bits of 'data' is
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// the IOP's chain transfer address (loaded into MADR). Bits 30 and 31 are transfer stop
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// bits of some sort.
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struct sifData
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{
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s32 data;
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s32 words;
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s32 count; // I think this is unused.
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s32 addr; // This too.
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tDMA_TAG tag_lo; // EE DMA tag
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tDMA_TAG tag_hi; // EE DMA tag
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};
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struct sifFifo
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@ -100,6 +104,7 @@ struct sif_ee
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s32 cycles;
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};
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struct sif_iop
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{
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bool end;
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@ -110,6 +115,7 @@ struct sif_iop
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s32 counter; // Used to keep track of how much is left in IOP.
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struct sifData data; // Only used in IOP.
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};
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struct _sif
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{
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sifFifo fifo; // Used in both.
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@ -69,8 +69,8 @@ static __fi bool WriteIOPtoFifo()
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SIF_LOG("Write IOP to Fifo: +++++++++++ %lX of %lX", writeSize, sif0.iop.counter);
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sif0.fifo.write((u32*)iopPhysMem(hw_dma(9).madr), writeSize);
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hw_dma(9).madr += writeSize << 2;
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sif0.fifo.write((u32*)iopPhysMem(hw_dma9.madr), writeSize);
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hw_dma9.madr += writeSize << 2;
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// iop is 1/8th the clock rate of the EE and psxcycles is in words (not quadwords).
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sif0.iop.cycles += (writeSize >> 2)/* * BIAS*/; // fixme : should be >> 4
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@ -83,13 +83,13 @@ static __fi bool WriteIOPtoFifo()
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static __fi bool ProcessEETag()
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{
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static __aligned16 u32 tag[4];
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tDMA_TAG& ptag(*(tDMA_TAG*)tag);
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sif0.fifo.read((u32*)&tag[0], 4); // Tag
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SIF_LOG("SIF0 EE read tag: %x %x %x %x", tag[0], tag[1], tag[2], tag[3]);
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sif0dma.unsafeTransfer(((tDMA_TAG*)(tag)));
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sif0dma.unsafeTransfer(&ptag);
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sif0dma.madr = tag[1];
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tDMA_TAG ptag(tag[0]);
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SIF_LOG("SIF0 EE dest chain tag madr:%08X qwc:%04X id:%X irq:%d(%08X_%08X)",
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sif0dma.madr, sif0dma.qwc, ptag.ID, ptag.IRQ, tag[1], tag[0]);
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@ -102,16 +102,12 @@ static __fi bool ProcessEETag()
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switch (ptag.ID)
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{
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case TAG_REFE:
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sif0.ee.end = true;
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if (dmacRegs.ctrl.STS != NO_STS)
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dmacRegs.stadr.ADDR = sif0dma.madr + (sif0dma.qwc * 16);
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break;
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case TAG_CNT: break;
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case TAG_REFS:
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case TAG_CNTS:
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if (dmacRegs.ctrl.STS != NO_STS)
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dmacRegs.stadr.ADDR = sif0dma.madr + (sif0dma.qwc * 16);
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break;
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break;
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case TAG_END:
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sif0.ee.end = true;
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@ -120,22 +116,29 @@ static __fi bool ProcessEETag()
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return true;
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}
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// Read Fifo into an iop tag, and transfer it to hw_dma(9). And presumably process it.
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// Read Fifo into an iop tag, and transfer it to hw_dma9. And presumably process it.
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static __fi bool ProcessIOPTag()
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{
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// Process DMA tag at hw_dma(9).tadr
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sif0.iop.data = *(sifData *)iopPhysMem(hw_dma(9).tadr);
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// Process DMA tag at hw_dma9.tadr
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sif0.iop.data = *(sifData *)iopPhysMem(hw_dma9.tadr);
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sif0.iop.data.words = (sif0.iop.data.words + 3) & 0xfffffffc; // Round up to nearest 4.
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sif0.fifo.write((u32*)iopPhysMem(hw_dma(9).tadr + 8), 4);
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hw_dma(9).tadr += 16; ///hw_dma(9).madr + 16 + sif0.sifData.words << 2;
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// send the EE's side of the DMAtag. The tag is only 64 bits, with the upper 64 bits
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// ignored by the EE.
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// We're only copying the first 24 bits.
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hw_dma(9).madr = sif0data & 0xFFFFFF;
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sif0.fifo.write((u32*)iopPhysMem(hw_dma9.tadr + 8), 2);
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sif0.fifo.writePos = (sif0.fifo.writePos + 2) & (FIFO_SIF_W - 1); // iggy on the upper 64.
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sif0.fifo.size += 2;
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hw_dma9.tadr += 16; ///hw_dma9.madr + 16 + sif0.sifData.words << 2;
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// We're only copying the first 24 bits. Bits 30 and 31 (checked below) are Stop/IRQ bits.
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hw_dma9.madr = sif0data & 0xFFFFFF;
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sif0.iop.counter = sif0words;
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// IOP tags have an IRQ bit and an End of Transfer bit:
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if (sif0tag.IRQ || (sif0tag.ID & 4)) sif0.iop.end = true;
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SIF_LOG("SIF0 IOP Tag: madr=%lx, tadr=%lx, counter=%lx (%08X_%08X)", hw_dma(9).madr, hw_dma(9).tadr, sif0.iop.counter, sif0words, sif0data);
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SIF_LOG("SIF0 IOP Tag: madr=%lx, tadr=%lx, counter=%lx (%08X_%08X)", hw_dma9.madr, hw_dma9.tadr, sif0.iop.counter, sif0words, sif0data);
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return true;
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}
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@ -265,7 +268,7 @@ static __fi void HandleIOPTransfer()
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}
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else
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{
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// Read Fifo into an iop tag, and transfer it to hw_dma(9).
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// Read Fifo into an iop tag, and transfer it to hw_dma9.
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// And presumably process it.
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ProcessIOPTag();
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}
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@ -282,6 +285,9 @@ static __fi void HandleIOPTransfer()
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static __fi void Sif0End()
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{
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psHu32(SBUS_F240) &= ~0x20;
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psHu32(SBUS_F240) &= ~0x2000;
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SIF_LOG("SIF0 DMA end...");
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}
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@ -351,8 +357,5 @@ __fi void dmaSIF0()
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{
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//hwIntcIrq(INTC_SBUS); // not sure, so let's not
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SIF0Dma();
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// Do we really want to mess with the SIF flags like that? Nah.
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//psHu32(SBUS_F240) &= ~0x20;
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//psHu32(SBUS_F240) &= ~0x2000;
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}
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}
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@ -68,9 +68,9 @@ static __fi bool WriteFifoToIOP()
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SIF_LOG("Sif 1 IOP doing transfer %04X to %08X", readSize, HW_DMA10_MADR);
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sif1.fifo.read((u32*)iopPhysMem(hw_dma(10).madr), readSize);
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psxCpu->Clear(hw_dma(10).madr, readSize);
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hw_dma(10).madr += readSize << 2;
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sif1.fifo.read((u32*)iopPhysMem(hw_dma10.madr), readSize);
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psxCpu->Clear(hw_dma10.madr, readSize);
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hw_dma10.madr += readSize << 2;
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sif1.iop.cycles += readSize >> 2; // fixme: should be >> 4
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sif1.iop.counter -= readSize;
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@ -151,7 +151,7 @@ static __fi bool SIFIOPReadTag()
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sif1data & 0xffffff, sif1words, sif1tag.ID, sif1tag.IRQ);
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// Only use the first 24 bits.
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hw_dma(10).madr = sif1data & 0xffffff;
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hw_dma10.madr = sif1data & 0xffffff;
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sif1.iop.counter = sif1words;
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if (sif1tag.IRQ || (sif1tag.ID & 4)) sif1.iop.end = true;
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@ -276,6 +276,9 @@ static __fi void HandleIOPTransfer()
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static __fi void Sif1End()
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{
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psHu32(SBUS_F240) &= ~0x40;
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psHu32(SBUS_F240) &= ~0x4000;
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SIF_LOG("SIF1 DMA end...");
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}
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@ -349,9 +352,5 @@ __fi void dmaSIF1()
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if (sif1.iop.busy)
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{
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SIF1Dma();
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// Do we really want to mess with the SIF flags like that? Nah.
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//psHu32(SBUS_F240) &= ~0x40;
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//psHu32(SBUS_F240) &= ~0x100;
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//psHu32(SBUS_F240) &= ~0x4000;
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}
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}
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@ -17,20 +17,20 @@ s32 PrepareEERead()
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{
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static __aligned16 u32 tag[4];
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// Process DMA tag at hw_dma(9).tadr
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sif0.iop.data = *(sifData *)iopPhysMem(hw_dma(9).tadr);
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// Process DMA tag at hw_dma9.tadr
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sif0.iop.data = *(sifData *)iopPhysMem(hw_dma9.tadr);
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sif0.iop.data.words = (sif0.iop.data.words + 3) & 0xfffffffc; // Round up to nearest 4.
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memcpy(tag, (u32*)iopPhysMem(hw_dma(9).tadr + 8), 16);
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memcpy(tag, (u32*)iopPhysMem(hw_dma9.tadr + 8), 16);
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hw_dma(9).tadr += 16; ///hw_dma(9).madr + 16 + sif0.sifData.words << 2;
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hw_dma9.tadr += 16; ///hw_dma9.madr + 16 + sif0.sifData.words << 2;
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// We're only copying the first 24 bits.
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hw_dma(9).madr = sif0data & 0xFFFFFF;
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hw_dma9.madr = sif0data & 0xFFFFFF;
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sif0.iop.counter = sif0words;
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if (sif0tag.IRQ || (sif0tag.ID & 4)) sif0.iop.end = true;
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SIF_LOG("SIF0 IOP to EE Tag: madr=%lx, tadr=%lx, counter=%lx (%08X_%08X)"
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"\n\tread tag: %x %x %x %x", hw_dma(9).madr, hw_dma(9).tadr, sif0.iop.counter, sif0words, sif0data,
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"\n\tread tag: %x %x %x %x", hw_dma9.madr, hw_dma9.tadr, sif0.iop.counter, sif0words, sif0data,
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tag[0], tag[1], tag[2], tag[3]);
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sif0dma.unsafeTransfer(((tDMA_TAG*)(tag)));
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@ -98,7 +98,7 @@ s32 DoSifRead(u32 iopAvailable)
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return false;
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}
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||||
memcpy((u32*)ptag, (u32*)iopPhysMem(hw_dma(9).madr), transferSizeBytes);
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memcpy((u32*)ptag, (u32*)iopPhysMem(hw_dma9.madr), transferSizeBytes);
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// Clearing handled by vtlb memory protection and manual blocks.
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//Cpu->Clear(sif0dma.madr, readSize*4);
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||||
|
|
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Loading…
Reference in New Issue