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Minor PERF fixups -- moved the diagnostic msg to a less spamming-like area (on PCCR assignment, rather than on PCR update). 

git-svn-id: http://pcsx2.googlecode.com/svn/trunk@748 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
Jake.Stine 2009-03-11 19:08:08 +00:00
parent 004d559678
commit 5d93b6bbe9
4 changed files with 29 additions and 37 deletions
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28
pcsx2/COP0.cpp
View File

@ -164,7 +164,7 @@ void WriteTLB(int i)
// count. But only mode 1 (instruction counter) has been found to be used by games thus far.
//
__forceinline bool PERF_ShouldCountEvent( uint evt )
static __forceinline bool PERF_ShouldCountEvent( uint evt )
{
switch( evt )
{
@ -188,7 +188,6 @@ __forceinline bool PERF_ShouldCountEvent( uint evt )
case 8: // Non-blocking load / WBB burst request fail
case 9:
case 10:
Console::Notice( "COP0 - PCR0 Unsupported Update Event Mode = 0x%x\n\t(Nneeve says this should probably never happen!)", params cpuRegs.PERF.n.pccr.b.Event0 );
return false;
case 11: // CPU address bus busy / CPU data bus busy
@ -204,7 +203,19 @@ __forceinline bool PERF_ShouldCountEvent( uint evt )
return false;
}
__forceinline void COP0_UpdatePCR()
// Diagnostics for event modes that we just ignore for now. Using these perf units could
// cause compat issues in some very odd/rare games, so if this msg comes up who knows,
// might save some debugging effort. :)
void COP0_DiagnosticPCCR()
{
if( cpuRegs.PERF.n.pccr.b.Event0 >= 7 && cpuRegs.PERF.n.pccr.b.Event0 <= 10 )
Console::Notice( "PERF/PCR0 Unsupported Update Event Mode = 0x%x", params cpuRegs.PERF.n.pccr.b.Event0 );
if( cpuRegs.PERF.n.pccr.b.Event1 >= 7 && cpuRegs.PERF.n.pccr.b.Event1 <= 10 )
Console::Notice( "PERF/PCR1 Unsupported Update Event Mode = 0x%x", params cpuRegs.PERF.n.pccr.b.Event1 );
}
__forceinline void COP0_UpdatePCCR()
{
if( cpuRegs.CP0.n.Status.b.ERL || !cpuRegs.PERF.n.pccr.b.CTE ) return;
@ -283,6 +294,9 @@ __forceinline void COP0_UpdatePCR()
}
}
//////////////////////////////////////////////////////////////////////////////////////////
//
namespace R5900 {
namespace Interpreter {
namespace OpcodeImpl {
@ -297,7 +311,6 @@ void MFC0()
//if(bExecBIOS == FALSE && _Rd_ == 25) SysPrintf("MFC0 _Rd_ %x = %x\n", _Rd_, cpuRegs.CP0.r[_Rd_]);
switch (_Rd_)
{
case 12:
cpuRegs.GPR.r[_Rt_].SD[0] = (s32)(cpuRegs.CP0.r[_Rd_] & 0xf0c79c1f);
break;
@ -310,12 +323,12 @@ void MFC0()
break;
case 1: // MFPC [LSB is set] - read PCR0
COP0_UpdatePCR();
COP0_UpdatePCCR();
cpuRegs.GPR.r[_Rt_].SD[0] = (s32)cpuRegs.PERF.n.pcr0;
break;
case 3: // MFPC [LSB is set] - read PCR1
COP0_UpdatePCR();
COP0_UpdatePCCR();
cpuRegs.GPR.r[_Rt_].SD[0] = (s32)cpuRegs.PERF.n.pcr1;
break;
}
@ -354,8 +367,9 @@ void MTC0()
{
case 0: // MTPS [LSB is clear]
// Updates PCRs and sets the PCCR.
COP0_UpdatePCR();
COP0_UpdatePCCR();
cpuRegs.PERF.n.pccr.val = cpuRegs.GPR.r[_Rt_].UL[0];
COP0_DiagnosticPCCR();
break;
case 1: // MTPC [LSB is set] - set PCR0

3
pcsx2/COP0.h
View File

@ -25,7 +25,8 @@ extern void WriteTLB(int i);
extern void UnmapTLB(int i);
extern void MapTLB(int i);
extern void COP0_UpdatePCR();
extern void COP0_UpdatePCCR();
extern void COP0_DiagnosticPCCR();
#endif /* __COP0_H__ */

2
pcsx2/R5900.cpp
View File

@ -392,7 +392,7 @@ static __forceinline void _cpuTestPERF()
// around twice on us btween updates. Hence this function is called from the cpu's
// Counters update.
COP0_UpdatePCR();
COP0_UpdatePCCR();
}
// Checks the COP0.Status for exception enablings.

33
pcsx2/x86/iCOP0.cpp
View File

@ -166,8 +166,7 @@ void recMFC0( void )
case 1:
case 3:
CALLFunc( (uptr)COP0_UpdatePCR );
CALLFunc( (uptr)COP0_UpdatePCR );
CALLFunc( (uptr)COP0_UpdatePCCR );
break;
}
_deleteEEreg(_Rt_, 0);
@ -231,30 +230,6 @@ void recMFC0( void )
}
}
void updatePCCR()
{
// read the old pccr and update pcr0/1
MOV32MtoR(EAX, (uptr)&cpuRegs.PERF.n.pccr);
MOV32RtoR(EDX, EAX);
MOV32MtoR(ECX, (uptr)&cpuRegs.cycle);
AND32ItoR(EAX, 0x800003E0);
CMP32ItoR(EAX, 0x80000020);
j8Ptr[0] = JNE8(0);
MOV32MtoR(EAX, (uptr)&s_iLastPERFCycle[0]);
ADD32RtoM((uptr)&cpuRegs.PERF.n.pcr0, ECX);
SUB32RtoM((uptr)&cpuRegs.PERF.n.pcr0, EAX);
x86SetJ8(j8Ptr[0]);
AND32ItoR(EDX, 0x800F8000);
CMP32ItoR(EDX, 0x80008000);
j8Ptr[0] = JNE8(0);
MOV32MtoR(EAX, (uptr)&s_iLastPERFCycle[1]);
ADD32RtoM((uptr)&cpuRegs.PERF.n.pcr1, ECX);
SUB32RtoM((uptr)&cpuRegs.PERF.n.pcr1, EAX);
x86SetJ8(j8Ptr[0]);
}
void recMTC0()
{
if( GPR_IS_CONST1(_Rt_) )
@ -277,8 +252,9 @@ void recMTC0()
switch(_Imm_ & 0x3F)
{
case 0:
CALLFunc( (uptr)COP0_UpdatePCR );
CALLFunc( (uptr)COP0_UpdatePCCR );
MOV32ItoM((uptr)&cpuRegs.PERF.n.pccr, g_cpuConstRegs[_Rt_].UL[0]);
CALLFunc( (uptr)COP0_DiagnosticPCCR );
break;
case 1:
@ -324,8 +300,9 @@ void recMTC0()
switch(_Imm_ & 0x3F)
{
case 0:
CALLFunc( (uptr)COP0_UpdatePCR );
CALLFunc( (uptr)COP0_UpdatePCCR );
_eeMoveGPRtoM((uptr)&cpuRegs.PERF.n.pccr, _Rt_);
CALLFunc( (uptr)COP0_DiagnosticPCCR );
break;
case 1: