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Few more SSE checks removed. 

git-svn-id: http://pcsx2-playground.googlecode.com/svn/trunk@283 a6443dda-0b58-4228-96e9-037be469359c
This commit is contained in:
ramapcsx2 2008-11-03 16:20:40 +00:00 committed by Gregory Hainaut
parent 8dc5441547
commit 5d6c89f1e2
2 changed files with 131 additions and 168 deletions
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12
pcsx2/windows/CpuDlg.c
View File

@ -86,18 +86,6 @@ BOOL CALLBACK CpuDlgProc(HWND hW, UINT uMsg, WPARAM wParam, LPARAM lParam)
// if(cpucaps.has3DNOWInstructionExtensions) strcat(features,",3DNOW");
// if(cpucaps.has3DNOWInstructionExtensionsExt)strcat(features,",3DNOW+");
if(cpucaps.hasAMD64BitArchitecture) strcat(features,",x86-64");
SetDlgItemText(hW, IDC_FEATURESINPUT, features);
if(!cpucaps.hasStreamingSIMDExtensions)
{
EnableWindow(GetDlgItem(hW,IDC_RADIORECOMPILERVU),FALSE);//disable checkbox if no SSE2 found
Config.Options &= (PCSX2_VU0REC|PCSX2_VU1REC);//disable the config just in case
}
if(!cpucaps.hasMultimediaExtensions)
{
EnableWindow(GetDlgItem(hW,IDC_RADIORECOMPILER),FALSE);
Config.Options &= ~(PCSX2_EEREC|PCSX2_VU0REC|PCSX2_VU1REC|PCSX2_COP2REC);//return to interpreter mode
}
SetDlgItemText(hW, IDC_FEATURESINPUT, features);
CheckDlgButton(hW, IDC_CPU_EEREC, !!CHECK_EEREC);

27
pcsx2/x86/ix86-64/iR5900-64.c
View File

@ -285,7 +285,7 @@ u8 _eeIsLoadStoreCoIssue(u32 firstcode, u32 secondcode)
case 57: // swc1
case 54: // lqc2
case 62: // sqc2
return (secondcode>>26)==(firstcode>>26)&&cpucaps.hasStreamingSIMDExtensions;
return (secondcode>>26)==(firstcode>>26);
}
return 0;
}
@ -1078,7 +1078,6 @@ void eeFPURecompileCode(R5900FNPTR_INFO xmmcode, R5900FNPTR fpucode, int xmminfo
{
int mmregs=-1, mmregt=-1, mmregd=-1, mmregacc=-1;
if( cpucaps.hasStreamingSIMDExtensions ) {
int info = PROCESS_EE_XMM;
if( xmminfo & XMMINFO_READS ) _addNeededFPtoXMMreg(_Fs_);
@ -1212,13 +1211,6 @@ void eeFPURecompileCode(R5900FNPTR_INFO xmmcode, R5900FNPTR fpucode, int xmminfo
xmmcode(info);
_clearNeededXMMregs();
return;
}
MOV32ItoM((uptr)&cpuRegs.code, cpuRegs.code);
MOV32ItoM((uptr)&cpuRegs.pc, pc);
iFlushCall(FLUSH_EVERYTHING);
CALLFunc((uptr)fpucode);
}
#undef _Ft_
@ -1818,25 +1810,8 @@ void recCOP2( void )
#ifdef CPU_LOG
CPU_LOG( "Recompiling COP2:%s\n", disR5900Fasm( cpuRegs.code, cpuRegs.pc ) );
#endif
if ( !cpucaps.hasStreamingSIMDExtensions ) {
MOV32ItoM( (uptr)&cpuRegs.code, cpuRegs.code );
MOV32ItoM( (uptr)&cpuRegs.pc, pc );
iFlushCall(FLUSH_EVERYTHING);
g_cpuHasConstReg = 1; // reset all since COP2 can change regs
CALLFunc( (uptr)COP2 );
CMP32ItoM((uptr)&cpuRegs.pc, pc);
j8Ptr[0] = JE8(0);
ADD32ItoM((uptr)&cpuRegs.cycle, s_nBlockCycles);
JMP32((uptr)DispatcherReg - ( (uptr)x86Ptr + 5 ));
x86SetJ8(j8Ptr[0]);
}
else
{
recCOP22( );
}
}
#endif