mirror of https://github.com/PCSX2/pcsx2.git
Rule Of Rose now works with the FPU recs :D
git-svn-id: http://pcsx2-playground.googlecode.com/svn/trunk@131 a6443dda-0b58-4228-96e9-037be469359c
This commit is contained in:
cottonvibes
Gregory Hainaut
parent
0bab1b1e8c
commit
5c2c09caf0
292
pcsx2/x86/iFPU.c
292
pcsx2/x86/iFPU.c
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@ -302,8 +302,8 @@ void recCOP1_BC1()
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recCP1BC1[_Rt_]();
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}
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static u32 _mxcsr = 0x7F80;
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static u32 _mxcsrs;
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//static u32 _mxcsr = 0x7F80;
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//static u32 _mxcsrs;
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static u32 fpucw = 0x007f;
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static u32 fpucws = 0;
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@ -360,7 +360,6 @@ void recCOP1_W( void )
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#ifndef FPU_RECOMPILE
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REC_FPUFUNC(ADD_S);
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REC_FPUFUNC(SUB_S);
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REC_FPUFUNC(MUL_S);
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@ -385,10 +384,10 @@ REC_FPUBRANCH(BC1F);
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REC_FPUBRANCH(BC1T);
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REC_FPUBRANCH(BC1FL);
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REC_FPUBRANCH(BC1TL);
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REC_FPUFUNC(C_F);
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REC_FPUFUNC(C_EQ);
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REC_FPUFUNC(C_LE);
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REC_FPUFUNC(C_F);
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REC_FPUFUNC(C_LT);
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REC_FPUFUNC(C_LE);
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#else
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@ -676,97 +675,7 @@ void recMIN_S_(int info) {
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#endif
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////////////////////////////////////////////////////
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void recC_EQ_xmm(int info)
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{
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// assumes that inputs are valid
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switch(info & (PROCESS_EE_S|PROCESS_EE_T) ) {
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case PROCESS_EE_S: SSE_UCOMISS_M32_to_XMM(EEREC_S, (uptr)&fpuRegs.fpr[_Ft_]); break;
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case PROCESS_EE_T: SSE_UCOMISS_M32_to_XMM(EEREC_T, (uptr)&fpuRegs.fpr[_Fs_]); break;
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default: SSE_UCOMISS_XMM_to_XMM(EEREC_S, EEREC_T); break;
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}
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//write8(0x9f); // lahf
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//TEST16ItoR(EAX, 0x4400);
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j8Ptr[0] = JZ8(0);
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AND32ItoM( (uptr)&fpuRegs.fprc[31], ~0x00800000 );
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j8Ptr[1] = JMP8(0);
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x86SetJ8(j8Ptr[0]);
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OR32ItoM((uptr)&fpuRegs.fprc[31], 0x00800000);
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x86SetJ8(j8Ptr[1]);
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}
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FPURECOMPILE_CONSTCODE(C_EQ, XMMINFO_READS|XMMINFO_READT);
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////////////////////////////////////////////////////
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void recC_F()
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{
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AND32ItoM( (uptr)&fpuRegs.fprc[31], ~0x00800000 );
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}
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////////////////////////////////////////////////////
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void recC_LT_xmm(int info)
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{
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// assumes that inputs are valid
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switch(info & (PROCESS_EE_S|PROCESS_EE_T) ) {
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case PROCESS_EE_S: SSE_UCOMISS_M32_to_XMM(EEREC_S, (uptr)&fpuRegs.fpr[_Ft_]); break;
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case PROCESS_EE_T: SSE_UCOMISS_M32_to_XMM(EEREC_T, (uptr)&fpuRegs.fpr[_Fs_]); break;
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default: SSE_UCOMISS_XMM_to_XMM(EEREC_S, EEREC_T); break;
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}
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//write8(0x9f); // lahf
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//TEST16ItoR(EAX, 0x4400);
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if( info & PROCESS_EE_S ) {
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j8Ptr[0] = JB8(0);
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AND32ItoM( (uptr)&fpuRegs.fprc[31], ~0x00800000 );
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j8Ptr[1] = JMP8(0);
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x86SetJ8(j8Ptr[0]);
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OR32ItoM((uptr)&fpuRegs.fprc[31], 0x00800000);
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x86SetJ8(j8Ptr[1]);
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}
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else {
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j8Ptr[0] = JBE8(0);
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OR32ItoM((uptr)&fpuRegs.fprc[31], 0x00800000);
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j8Ptr[1] = JMP8(0);
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x86SetJ8(j8Ptr[0]);
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AND32ItoM( (uptr)&fpuRegs.fprc[31], ~0x00800000 );
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x86SetJ8(j8Ptr[1]);
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}
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}
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FPURECOMPILE_CONSTCODE(C_LT, XMMINFO_READS|XMMINFO_READT);
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////////////////////////////////////////////////////
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void recC_LE_xmm(int info )
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{
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switch(info & (PROCESS_EE_S|PROCESS_EE_T) ) {
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case PROCESS_EE_S: SSE_UCOMISS_M32_to_XMM(EEREC_S, (uptr)&fpuRegs.fpr[_Ft_]); break;
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case PROCESS_EE_T: SSE_UCOMISS_M32_to_XMM(EEREC_T, (uptr)&fpuRegs.fpr[_Fs_]); break;
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default: SSE_UCOMISS_XMM_to_XMM(EEREC_S, EEREC_T); break;
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}
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//write8(0x9f); // lahf
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//TEST16ItoR(EAX, 0x4400);
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if( info & PROCESS_EE_S ) {
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j8Ptr[0] = JBE8(0);
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AND32ItoM( (uptr)&fpuRegs.fprc[31], ~0x00800000 );
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j8Ptr[1] = JMP8(0);
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x86SetJ8(j8Ptr[0]);
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OR32ItoM((uptr)&fpuRegs.fprc[31], 0x00800000);
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x86SetJ8(j8Ptr[1]);
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}
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else {
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j8Ptr[0] = JB8(0);
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OR32ItoM((uptr)&fpuRegs.fprc[31], 0x00800000);
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j8Ptr[1] = JMP8(0);
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x86SetJ8(j8Ptr[0]);
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AND32ItoM( (uptr)&fpuRegs.fprc[31], ~0x00800000 );
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x86SetJ8(j8Ptr[1]);
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}
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}
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FPURECOMPILE_CONSTCODE(C_LE, XMMINFO_READS|XMMINFO_READT);
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////////////////////////////////////////////////////
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static u32 s_signbit = 0x80000000;
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extern int g_VuNanHandling;
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@ -802,6 +711,199 @@ void ClampValues2(regd) {
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}
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////////////////////////////////////////////////////
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void recC_EQ_xmm(int info)
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{
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int tempReg;
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switch(info & (PROCESS_EE_S|PROCESS_EE_T) ) {
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case PROCESS_EE_S: SSE_UCOMISS_M32_to_XMM(EEREC_S, (uptr)&fpuRegs.fpr[_Ft_]); break;
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case PROCESS_EE_T: SSE_UCOMISS_M32_to_XMM(EEREC_T, (uptr)&fpuRegs.fpr[_Fs_]); break;
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case (PROCESS_EE_S|PROCESS_EE_T):
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fpuFloat(EEREC_S);
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fpuFloat(EEREC_T);
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SSE_UCOMISS_XMM_to_XMM(EEREC_S, EEREC_T);
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break;
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default:
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tempReg = _allocX86reg(-1, X86TYPE_TEMP, 0, 0);
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if (tempReg == -1) {SysPrintf("FPU: DIV Allocation Error!\n"); tempReg = EAX;}
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MOV32MtoR(tempReg, (uptr)&fpuRegs.fpr[_Fs_]);
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CMP32MtoR(tempReg, (uptr)&fpuRegs.fpr[_Ft_]);
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j8Ptr[0] = JZ8(0);
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AND32ItoM( (uptr)&fpuRegs.fprc[31], ~FPUflagC );
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j8Ptr[1] = JMP8(0);
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x86SetJ8(j8Ptr[0]);
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OR32ItoM((uptr)&fpuRegs.fprc[31], FPUflagC);
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x86SetJ8(j8Ptr[1]);
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_freeX86reg(tempReg);
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return;
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}
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j8Ptr[0] = JZ8(0);
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AND32ItoM( (uptr)&fpuRegs.fprc[31], ~FPUflagC );
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j8Ptr[1] = JMP8(0);
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x86SetJ8(j8Ptr[0]);
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OR32ItoM((uptr)&fpuRegs.fprc[31], FPUflagC);
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x86SetJ8(j8Ptr[1]);
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}
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FPURECOMPILE_CONSTCODE(C_EQ, XMMINFO_READS|XMMINFO_READT);
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//REC_FPUFUNC(C_EQ);
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////////////////////////////////////////////////////
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void recC_F()
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{
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AND32ItoM( (uptr)&fpuRegs.fprc[31], ~FPUflagC );
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}
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//REC_FPUFUNC(C_F);
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////////////////////////////////////////////////////
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void recC_LT_xmm(int info)
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{
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int tempReg;
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switch(info & (PROCESS_EE_S|PROCESS_EE_T) ) {
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case PROCESS_EE_S:
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//SysPrintf("PROCESS_EE_S\n");
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SSE_UCOMISS_M32_to_XMM(EEREC_S, (uptr)&fpuRegs.fpr[_Ft_]);
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break;
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case PROCESS_EE_T:
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//SysPrintf("PROCESS_EE_T\n");
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SSE_UCOMISS_M32_to_XMM(EEREC_T, (uptr)&fpuRegs.fpr[_Fs_]);
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j8Ptr[0] = JA8(0);
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AND32ItoM( (uptr)&fpuRegs.fprc[31], ~FPUflagC );
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j8Ptr[1] = JMP8(0);
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x86SetJ8(j8Ptr[0]);
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OR32ItoM((uptr)&fpuRegs.fprc[31], FPUflagC);
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x86SetJ8(j8Ptr[1]);
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return;
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case (PROCESS_EE_S|PROCESS_EE_T):
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//SysPrintf("PROCESS_EE_S|PROCESS_EE_T\n");
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fpuFloat(EEREC_S);
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fpuFloat(EEREC_T);
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SSE_UCOMISS_XMM_to_XMM(EEREC_S, EEREC_T);
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break;
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default:
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//SysPrintf("Default\n");
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tempReg = _allocX86reg(-1, X86TYPE_TEMP, 0, 0);
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if (tempReg == -1) {SysPrintf("FPU: DIV Allocation Error!\n"); tempReg = EAX;}
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MOV32MtoR(tempReg, (uptr)&fpuRegs.fpr[_Fs_]);
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CMP32MtoR(tempReg, (uptr)&fpuRegs.fpr[_Ft_]);
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j8Ptr[0] = JL8(0);
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AND32ItoM( (uptr)&fpuRegs.fprc[31], ~FPUflagC );
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j8Ptr[1] = JMP8(0);
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x86SetJ8(j8Ptr[0]);
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OR32ItoM((uptr)&fpuRegs.fprc[31], FPUflagC);
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x86SetJ8(j8Ptr[1]);
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_freeX86reg(tempReg);
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return;
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}
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j8Ptr[0] = JB8(0);
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AND32ItoM( (uptr)&fpuRegs.fprc[31], ~FPUflagC );
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j8Ptr[1] = JMP8(0);
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x86SetJ8(j8Ptr[0]);
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OR32ItoM((uptr)&fpuRegs.fprc[31], FPUflagC);
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x86SetJ8(j8Ptr[1]);
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}
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FPURECOMPILE_CONSTCODE(C_LT, XMMINFO_READS|XMMINFO_READT);
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//REC_FPUFUNC(C_LT);
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/*
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void recC_LT()
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{
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int tempS, tempT, tempReg;
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iFlushCall(FLUSH_EVERYTHING);
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tempS = _allocTempXMMreg(XMMT_FPS, -1);
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tempT = _allocTempXMMreg(XMMT_FPS, -1);
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tempReg = _allocX86reg(-1, X86TYPE_TEMP, 0, 0);
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if (tempReg == -1) {SysPrintf("FPU: DIV Allocation Error!\n"); tempReg = EAX;}
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SysPrintf("Default\n");
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SSE_MOVSS_M32_to_XMM(tempS, (uptr)&fpuRegs.fpr[_Fs_]);
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SSE_MINSS_M32_to_XMM(tempS, (uptr)&g_maxvals[0]);
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SSE_MAXSS_M32_to_XMM(tempS, (uptr)&g_minvals[0]);
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SSE_MOVSS_M32_to_XMM(tempT, (uptr)&fpuRegs.fpr[_Ft_]);
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SSE_MINSS_M32_to_XMM(tempT, (uptr)&g_maxvals[0]);
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SSE_MAXSS_M32_to_XMM(tempT, (uptr)&g_minvals[0]);
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SSE_UCOMISS_XMM_to_XMM(tempS, tempT);
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//MOV32MtoR(tempReg, (uptr)&fpuRegs.fpr[_Fs_]);
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//CMP32MtoR(tempReg, (uptr)&fpuRegs.fpr[_Ft_]);
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//j8Ptr[0] = JL8(0);
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j8Ptr[0] = JB8(0);
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AND32ItoM( (uptr)&fpuRegs.fprc[31], ~FPUflagC );
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j8Ptr[1] = JMP8(0);
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x86SetJ8(j8Ptr[0]);
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OR32ItoM((uptr)&fpuRegs.fprc[31], FPUflagC);
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x86SetJ8(j8Ptr[1]);
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_freeXMMreg(tempS);
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_freeXMMreg(tempT);
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_freeX86reg(tempReg);
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}*/
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////////////////////////////////////////////////////
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void recC_LE_xmm(int info )
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{
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int tempReg;
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switch(info & (PROCESS_EE_S|PROCESS_EE_T) ) {
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case PROCESS_EE_S:
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//SysPrintf("PROCESS_EE_S\n");
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SSE_UCOMISS_M32_to_XMM(EEREC_S, (uptr)&fpuRegs.fpr[_Ft_]);
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break;
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case PROCESS_EE_T:
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//SysPrintf("PROCESS_EE_T\n");
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SSE_UCOMISS_M32_to_XMM(EEREC_T, (uptr)&fpuRegs.fpr[_Fs_]);
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j8Ptr[0] = JAE8(0);
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AND32ItoM( (uptr)&fpuRegs.fprc[31], ~FPUflagC );
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j8Ptr[1] = JMP8(0);
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x86SetJ8(j8Ptr[0]);
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OR32ItoM((uptr)&fpuRegs.fprc[31], FPUflagC);
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x86SetJ8(j8Ptr[1]);
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return;
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case (PROCESS_EE_S|PROCESS_EE_T):
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//SysPrintf("PROCESS_EE_S|PROCESS_EE_T\n");
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fpuFloat(EEREC_S);
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fpuFloat(EEREC_T);
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SSE_UCOMISS_XMM_to_XMM(EEREC_S, EEREC_T);
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break;
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default:
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//SysPrintf("Default\n");
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tempReg = _allocX86reg(-1, X86TYPE_TEMP, 0, 0);
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if (tempReg == -1) {SysPrintf("FPU: DIV Allocation Error!\n"); tempReg = EAX;}
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MOV32MtoR(tempReg, (uptr)&fpuRegs.fpr[_Fs_]);
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CMP32MtoR(tempReg, (uptr)&fpuRegs.fpr[_Ft_]);
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j8Ptr[0] = JLE8(0);
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AND32ItoM( (uptr)&fpuRegs.fprc[31], ~FPUflagC );
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j8Ptr[1] = JMP8(0);
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x86SetJ8(j8Ptr[0]);
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OR32ItoM((uptr)&fpuRegs.fprc[31], FPUflagC);
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x86SetJ8(j8Ptr[1]);
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_freeX86reg(tempReg);
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return;
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}
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j8Ptr[0] = JBE8(0);
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AND32ItoM( (uptr)&fpuRegs.fprc[31], ~FPUflagC );
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j8Ptr[1] = JMP8(0);
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x86SetJ8(j8Ptr[0]);
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OR32ItoM((uptr)&fpuRegs.fprc[31], FPUflagC);
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x86SetJ8(j8Ptr[1]);
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}
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FPURECOMPILE_CONSTCODE(C_LE, XMMINFO_READS|XMMINFO_READT);
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//REC_FPUFUNC(C_LE);
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////////////////////////////////////////////////////
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static void (*recComOpXMM_to_XMM[] )(x86SSERegType, x86SSERegType) = {
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SSE_ADDSS_XMM_to_XMM, SSE_MULSS_XMM_to_XMM, SSE_MAXSS_XMM_to_XMM, SSE_MINSS_XMM_to_XMM };
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