mirror of https://github.com/PCSX2/pcsx2.git
IPU: Reorder DMA timing for IPU_TO and IPU_FROM
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6e1f76185e
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@ -91,6 +91,8 @@ struct alignas(16) tIPU_BP {
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__fi void Advance(uint bits)
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__fi void Advance(uint bits)
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{
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{
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FillBuffer(bits);
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BP += bits;
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BP += bits;
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pxAssume( BP <= 256 );
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pxAssume( BP <= 256 );
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@ -112,10 +114,10 @@ struct alignas(16) tIPU_BP {
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// if FP == 0 then an already-drained buffer is being advanced, and we need to drop a
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// if FP == 0 then an already-drained buffer is being advanced, and we need to drop a
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// quadword from the IPU FIFO.
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// quadword from the IPU FIFO.
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if (!FP)
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if (ipu_fifo.in.read(&internal_qwc[0]))
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ipu_fifo.in.read(&internal_qwc[0]);
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FP = 1;
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else
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FP = 0;
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FP = 0;
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}
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}
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}
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}
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}
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}
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@ -86,6 +86,9 @@ int IPU_Fifo_Input::write(u32* pMem, int size)
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pMem += 4;
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pMem += 4;
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}
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}
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if (g_BP.IFC == 8)
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IPU1Status.DataRequested = false;
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return firsttrans;
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return firsttrans;
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}
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}
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@ -99,7 +102,7 @@ int IPU_Fifo_Input::read(void *value)
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if(ipu1ch.chcr.STR && cpuRegs.eCycle[4] == 0x9999)
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if(ipu1ch.chcr.STR && cpuRegs.eCycle[4] == 0x9999)
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{
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{
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CPU_INT( DMAC_TO_IPU, 32 );
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CPU_INT( DMAC_TO_IPU, 4);
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}
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}
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if (g_BP.IFC == 0) return 0;
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if (g_BP.IFC == 0) return 0;
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@ -135,7 +138,7 @@ int IPU_Fifo_Output::write(const u32 *value, uint size)
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}
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}
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/*} while(true);*/
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/*} while(true);*/
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if(ipu0ch.chcr.STR)
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if(ipu0ch.chcr.STR)
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IPU_INT_FROM(64);
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IPU_INT_FROM(ipuRegs.ctrl.OFC * BIAS);
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return origsize - size;
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return origsize - size;
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}
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}
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@ -121,7 +121,7 @@ void IPU1dma()
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if(totalqwc == 0 || (IPU1Status.DMAFinished && !IPU1Status.InProgress))
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if(totalqwc == 0 || (IPU1Status.DMAFinished && !IPU1Status.InProgress))
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{
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{
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totalqwc = std::max(4, totalqwc);
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totalqwc = std::max(4, totalqwc);
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IPU_INT_TO(totalqwc);
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IPU_INT_TO(totalqwc * BIAS);
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}
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}
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else
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else
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{
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{
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@ -133,18 +133,18 @@ void IPU1dma()
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}
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}
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else
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else
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{
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{
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IPU_INT_TO(totalqwc*BIAS);
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IPU_INT_TO(totalqwc * BIAS);
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}
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}
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}
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}
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IPUProcessInterrupt();
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CPU_INT(IPU_PROCESS, totalqwc * BIAS);
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IPU_LOG("Completed Call IPU1 DMA QWC Remaining %x Finished %d In Progress %d tadr %x", ipu1ch.qwc, IPU1Status.DMAFinished, IPU1Status.InProgress, ipu1ch.tadr);
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IPU_LOG("Completed Call IPU1 DMA QWC Remaining %x Finished %d In Progress %d tadr %x", ipu1ch.qwc, IPU1Status.DMAFinished, IPU1Status.InProgress, ipu1ch.tadr);
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}
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}
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void IPU0dma()
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void IPU0dma()
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{
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{
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if(!ipuRegs.ctrl.OFC)
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if(!ipuRegs.ctrl.OFC)
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{
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{
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IPUProcessInterrupt();
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IPUProcessInterrupt();
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return;
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return;
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@ -181,6 +181,9 @@ void IPU0dma()
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}
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}
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IPU_INT_FROM( readsize * BIAS );
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IPU_INT_FROM( readsize * BIAS );
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if (ipu0ch.qwc > 0)
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CPU_INT(IPU_PROCESS, 4);
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}
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}
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__fi void dmaIPU0() // fromIPU
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__fi void dmaIPU0() // fromIPU
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@ -256,6 +259,11 @@ __fi void dmaIPU1() // toIPU
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}
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}
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}
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}
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void ipuCMDProcess()
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{
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IPUProcessInterrupt();
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}
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void ipu0Interrupt()
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void ipu0Interrupt()
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{
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{
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IPU_LOG("ipu0Interrupt: %x", cpuRegs.cycle);
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IPU_LOG("ipu0Interrupt: %x", cpuRegs.cycle);
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@ -23,6 +23,7 @@ struct IPUStatus {
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bool DataRequested;
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bool DataRequested;
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};
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};
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extern void ipuCMDProcess();
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extern void ipu0Interrupt();
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extern void ipu0Interrupt();
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extern void ipu1Interrupt();
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extern void ipu1Interrupt();
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@ -297,7 +297,7 @@ static __fi void _cpuTestInterrupts()
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TESTINT(DMAC_GIF, gifInterrupt);
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TESTINT(DMAC_GIF, gifInterrupt);
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TESTINT(DMAC_SIF0, EEsif0Interrupt);
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TESTINT(DMAC_SIF0, EEsif0Interrupt);
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TESTINT(DMAC_SIF1, EEsif1Interrupt);
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TESTINT(DMAC_SIF1, EEsif1Interrupt);
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TESTINT(IPU_PROCESS, ipuCMDProcess);
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// Profile-guided Optimization (sorta)
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// Profile-guided Optimization (sorta)
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// The following ints are rarely called. Encasing them in a conditional
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// The following ints are rarely called. Encasing them in a conditional
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// as follows helps speed up most games.
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// as follows helps speed up most games.
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@ -413,7 +413,8 @@ enum EE_EventType
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DMAC_GIF_UNIT,
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DMAC_GIF_UNIT,
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VIF_VU0_FINISH,
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VIF_VU0_FINISH,
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VIF_VU1_FINISH
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VIF_VU1_FINISH,
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IPU_PROCESS
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};
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};
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extern void CPU_INT( EE_EventType n, s32 ecycle );
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extern void CPU_INT( EE_EventType n, s32 ecycle );
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