mirror of https://github.com/PCSX2/pcsx2.git
microVU: fried my brain with some very-complex VU flag-handling logic/algorithms (hopefully they work as expected)
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@959 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
cottonvibes
parent
97fac9e635
commit
5b0d9b6723
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@ -359,7 +359,7 @@ emitterT void MOV32RtoRm( x86IntRegType to, x86IntRegType from, int offset)
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}
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/* mov r32 to r32 */
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/* mov r16 to r16 */
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emitterT void MOV16RtoR( x86IntRegType to, x86IntRegType from )
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{
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if( to == from ) return;
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@ -53,10 +53,11 @@ struct microAllocInfo {
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microRegInfo regs; // Pipeline info
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microTempRegInfo regsTemp; // Temp Pipeline info (used so that new pipeline info isn't conflicting between upper and lower instructions in the same cycle)
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u8 branch; // 0 = No Branch, 1 = B. 2 = BAL, 3~8 = Conditional Branches, 9 = JALR, 10 = JR
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u8 maxStall; // Helps in computing stalls (stores the max amount of cycles to stall for the current opcodes)
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//u8 maxStall; // Helps in computing stalls (stores the max amount of cycles to stall for the current opcodes)
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u32 cycles; // Cycles for current block
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u32 count; // Number of VU 64bit instructions ran (starts at 0 for each block)
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u32 curPC; // Current PC
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u32 startPC; // Start PC for Cur Block
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u32 info[pSize/8]; // Info for Instructions in current block
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u8 stall[pSize/8]; // Info on how much each instruction stalled
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};
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@ -682,8 +682,7 @@ microVUt(void) mVUallocSFLAGa(int reg, int fInstance) {
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microVUt(void) mVUallocSFLAGb(int reg, int fInstance) {
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getFlagReg(fInstance, fInstance);
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AND32ItoR(fInstance, 0xffff0000);
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OR16RtoR(fInstance, reg);
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MOV16RtoR(fInstance, reg);
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}
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microVUt(void) mVUallocMFLAGa(int reg, int fInstance) {
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@ -245,19 +245,42 @@ microVUt(void) mVUanalyzeR2(int Ft, bool canBeNOP) {
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microVUt(void) mVUanalyzeSflag(int It) {
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microVU* mVU = mVUx;
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if (!It) { mVUinfo |= _isNOP; }
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else { mVUinfo |= _isSflag | _swapOps; } // ToDo: set s flag at right time
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else { // Sets _isSflag at instruction that FSxxx opcode reads it's status flag from
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mVUinfo |= _swapOps;
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if (mVUcount >= 4) { incPC2(-8); mVUinfo |= _isSflag; incPC2(8); }
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//else { incPC2((mVUcount*-2)); mVUinfo |= _isSflag; incPC2(mVUcount*-2); }
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}
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analyzeVIreg2(It, 1);
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}
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microVUt(void) mVUanalyzeFSSET() {
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microVU* mVU = mVUx;
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int i, curPC = iPC;
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for (i = mVUcount; i > 0; i--) {
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incPC2(-2);
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if (isSflag) break;
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mVUinfo &= ~_doStatus;
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mVUinfo |= _isFSSSET;
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}
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//------------------------------------------------------------------
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// Mflag - Mac Flag Opcodes
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//------------------------------------------------------------------
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microVUt(void) mVUanalyzeMflag(int Is, int It) {
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microVU* mVU = mVUx;
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if (!It) { mVUinfo |= _isNOP; }
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else if (mVUcount >= 4) {
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incPC2(-8);
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if (doStatus) { mVUinfo |= _doMac; }
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else {
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int curPC = iPC;
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int i = mVUcount;
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for (; i > 0; i--) {
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incPC2(-2);
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if (doStatus) { mVUinfo |= _doMac; break; }
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}
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iPC = curPC;
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}
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incPC2(8);
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}
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iPC = curPC;
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analyzeVIreg1(Is);
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analyzeVIreg2(It, 1);
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}
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//------------------------------------------------------------------
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@ -19,6 +19,10 @@
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#pragma once
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#ifdef PCSX2_MICROVU
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//------------------------------------------------------------------
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// Helper Macros
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//------------------------------------------------------------------
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#define createBlock(blockEndPtr) { \
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block.pipelineState = pipelineState; \
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block.x86ptrStart = x86ptrStart; \
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@ -46,6 +50,115 @@
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#define incP() { mVU->p = (mVU->p+1) & 1; }
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#define incQ() { mVU->q = (mVU->q+1) & 1; }
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//------------------------------------------------------------------
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// Helper Functions
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//------------------------------------------------------------------
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// Optimizes out unneeded status flag updates
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microVUt(void) mVUstatusFlagOp() {
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microVU* mVU = mVUx;
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int curPC = iPC;
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int i = mVUcount;
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if (doStatus) { mVUinfo |= _isSflag; }
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else {
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for (; i > 0; i--) {
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incPC2(-2);
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if (doStatus) { mVUinfo |= _isSflag; break; }
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}
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}
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for (; i > 0; i--) {
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incPC2(-2);
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if (isSflag) break;
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mVUinfo &= ~_doStatus;
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}
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iPC = curPC;
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}
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// Note: Flag handling is 'very' complex, it requires full knowledge of how microVU recs work, so don't touch!
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microVUt(void) mVUsetFlags(int* bStatus, int* bMac) {
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microVU* mVU = mVUx;
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// Ensure last ~4+ instructions update mac flags
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int endPC = iPC;
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int aCount = 1; // Amount of instructions needed to get 4 valid status/mac flag instances
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for (int i = mVUcount; i > 0; i++, aCount++;) {
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if (doStatus) { mVUinfo |= _doMac; if (i >= 4) { break; } }
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incPC2(-2);
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}
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// Status/Mac Flags Setup Code
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int xStatus = 0; // Status Instance starts at #0 on every block
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int xMac = 0; // Mac Instance starts at #0 on every block
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int pStatus = 0;
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int pMac = 0;
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int xCount = mVUcount; // Backup count
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mVUcount = 0;
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iPC = mVUstartPC;
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for (int i = 0; i < xCount; i++) {
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if ((xCount - i) > aCount) mVUstatusFlagOp<vuIndex>(); // Don't Optimize out on the last ~4+ instructions
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if (doStatus||isFSSET) { mVUinfo |= xStatus << 12; } // _fsInstance
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if (doMac) { mVUinfo |= xMac << 10; } // _fmInstance
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pStatus = (xStatus + ((mVUstall > 3) ? 3 : mVUstall)) & 3;
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pMac = (xMac + ((mVUstall > 3) ? 3 : mVUstall)) & 3;
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mVUinfo |= pStatus << 18; // _fvsInstance
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mVUinfo |= pMac << 16; // _fvmInstance
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if (doStatus||isFSSET) { xStatus = (xStatus+1) & 3; }
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if (doMac) { xMac = (xMac+1) & 3; }
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incPC2(2);
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}
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mVUcount = xCount; // Restore count
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// Setup Last 4 instances of Status/Mac flags (needed for accurate block linking)
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iPC = endPC;
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for (int i = 3, int j = 3, int ii = 1, int jj = 3; aCount > 0; ii++, aCount--) {
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if (doStatus && (i >= 0)) {
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for (; (ii > 0 && i >= 0); ii--) { xStatus = (xStatus-1) & 3; bStatus[i] = xStatus; i--; }
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}
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if (doMac && (j >= 0)) {
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for (; (jj > 0 && j >= 0); jj--) { xMac = (xMac-1) & 3; bMac[i] = xMac; j--; }
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}
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incPC2(-2);
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}
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}
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#define getFlagReg1(x) ((x == 3) ? gprF3 : ((x == 2) ? gprF2 : ((x == 1) ? gprF1 : gprF0)))
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#define getFlagReg2(x) ((x == bStatus[3]) ? gprESP : ((x == bStatus[2]) ? gprR : ((x == bStatus[1]) ? gprT2 : gprT1)))
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// Recompiles Code for Proper Flags on Block Linkings
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microVUt(void) mVUsetFlagsRec(int* bStatus, int* bMac) {
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PUSHR(gprR); // Backup gprR
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PUSHR(gprESP); // Backup gprESP
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MOV32RtoR(gprT1, getFlagReg1(bStatus[0]));
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MOV32RtoR(gprT2, getFlagReg1(bStatus[1]));
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MOV32RtoR(gprR, getFlagReg1(bStatus[2]));
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MOV32RtoR(gprESP, getFlagReg1(bStatus[3]));
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MOV32RtoR(gprF0, gprT1);
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MOV32RtoR(gprF1, gprT2);
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MOV32RtoR(gprF2, gprR);
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MOV32RtoR(gprF3, gprESP);
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AND32ItoR(gprT1, 0xffff0000);
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AND32ItoR(gprT2, 0xffff0000);
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AND32ItoR(gprR, 0xffff0000);
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AND32ItoR(gprESP, 0xffff0000);
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AND32ItoR(gprF0, 0x0000ffff);
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AND32ItoR(gprF1, 0x0000ffff);
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AND32ItoR(gprF2, 0x0000ffff);
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AND32ItoR(gprF3, 0x0000ffff);
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OR32RtoR(gprF0, getFlagReg2(bMac[0]));
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OR32RtoR(gprF1, getFlagReg2(bMac[1]));
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OR32RtoR(gprF2, getFlagReg2(bMac[2]));
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OR32RtoR(gprF3, getFlagReg2(bMac[3]));
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POPR(gprESP); // Restore gprESP
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POPR(gprR); // Restore gprR
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}
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microVUt(void) mVUincCycles(int x) {
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microVU* mVU = mVUx;
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mVUcycles += x;
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@ -130,13 +243,14 @@ microVUx(void*) mVUcompile(u32 startPC, u32 pipelineState, microRegInfo* pState,
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mVUcount++;
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}
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// Sets Up Flag instances
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int bStatus[4]; int bMac[4];
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mVUsetFlags<vuIndex>(bStatus, bMac);
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// Second Pass
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iPC = mVUstartPC;
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setCode();
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for (bool x = 1; x; ) {
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//
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// ToDo: status/mac flag stuff?
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//
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if (isEOB) { x = 0; }
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//if (isBranch2) { mVUopU<vuIndex, 1>(); incPC(2); }
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@ -156,9 +270,10 @@ microVUx(void*) mVUcompile(u32 startPC, u32 pipelineState, microRegInfo* pState,
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case 8: branchCase(JNZ32); // IBNEQ
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case 2: branchCase2(); // BAL
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case 1:
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// search for block
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// ToDo: search for block
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// (remember about global variables and recursion!)
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mVUsetFlagsRec<vuIndex>(bStatus, bMac);
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ajmp = JMP32((uptr)0);
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break; // B/BAL
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case 9: branchCase2(); // JALR
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case 10: break; // JR/JALR
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@ -167,8 +282,8 @@ microVUx(void*) mVUcompile(u32 startPC, u32 pipelineState, microRegInfo* pState,
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return thisPtr;
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}
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}
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// Do E-bit end stuff here
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// Do E-bit end stuff here
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incCycles(55); // Ensures Valid P/Q instances
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mVUcycles -= 55;
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if (mVU->q) { SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, 0xe5); }
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@ -176,10 +291,11 @@ microVUx(void*) mVUcompile(u32 startPC, u32 pipelineState, microRegInfo* pState,
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SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, mVU->p ? 3 : 2);
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SSE_MOVSS_XMM_to_M32((uptr)&mVU->regs->VI[REG_P], xmmPQ);
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MOV32ItoM((uptr)&mVU->p, mVU->p);
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MOV32ItoM((uptr)&mVU->q, mVU->q);
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//MOV32ItoM((uptr)&mVU->p, mVU->p);
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//MOV32ItoM((uptr)&mVU->q, mVU->q);
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AND32ItoM((uptr)µVU0.regs.VI[REG_VPU_STAT].UL, (vuIndex ? ~0x100 : ~0x001)); // VBS0/VBS1 flag
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AND32ItoM((uptr)&mVU->regs->vifRegs->stat, ~0x4); // Not sure what this does but zerorecs do it...
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AND32ItoM((uptr)&mVU->regs->vifRegs->stat, ~0x4); // Clear VU 'is busy' signal for vif
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MOV32ItoM((uptr)&mVU->regs->VI[REG_TPC], xPC);
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JMP32((uptr)mVU->exitFunct - ((uptr)x86Ptr + 5));
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return thisPtr;
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@ -547,10 +547,12 @@ microVUf(void) mVU_FSSET() {
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microVU* mVU = mVUx;
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if (!recPass) { mVUanalyzeFSSET<vuIndex>(); }
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else {
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int flagReg;
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getFlagReg(flagReg, fsInstance);
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AND32ItoR(flagReg, 0x03f);
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OR32ItoR(flagReg, (_Imm12_ & 0xfc0));
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int flagReg = gprT1;
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if (doStatus) { getFlagReg(flagReg, fsInstance); } // Get status result from upper instruction
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else { mVUallocSFLAGa<vuIndex>(flagReg, fpsInstance); } // Get status result from last status setting instruction
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AND16ItoR(flagReg, 0x03f); // Remember not to modify upper 16 bits because of mac flag
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OR16ItoR(flagReg, (_Imm12_ & 0xfc0));
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if (!doStatus) { mVUallocSFLAGb<vuIndex>(flagReg, fsInstance); }
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}
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}
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@ -144,12 +144,13 @@ declareAllVariables
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#define mVUbranch mVUallocInfo.branch
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#define mVUcycles mVUallocInfo.cycles
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#define mVUcount mVUallocInfo.count
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#define mVUstall mVUallocInfo.maxStall
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//#define mVUstall mVUallocInfo.maxStall
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#define mVUregs mVUallocInfo.regs
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#define mVUregsTemp mVUallocInfo.regsTemp
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#define mVUinfo mVUallocInfo.info[mVUallocInfo.curPC / 2]
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#define mVUstartPC mVUallocInfo.startPC
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#define iPC mVUallocInfo.curPC
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#define mVUinfo mVUallocInfo.info[iPC / 2]
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#define mVUstall mVUallocInfo.stall[iPC / 2]
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#define mVUstartPC mVUallocInfo.startPC
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#define xPC ((iPC / 2) * 8)
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#define curI mVUcurProg.data[iPC]
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#define setCode() { mVU->code = curI; }
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@ -183,7 +184,8 @@ declareAllVariables
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#define _memReadIt (1<<24) // Read If (VI reg) from memory (used by branches)
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#define _writesVI (1<<25) // Current Instruction writes to VI
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#define _swapOps (1<<26) // Runs Lower Instruction Before Upper Instruction
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//#define _isBranch2 (1<<27) // Cur Instruction is a Branch that writes VI regs (BAL/JALR)
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#define _isFSSSET (1<<27) // Cur Instruction is FSSET
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//#define _isBranch2 (1<<28) // Cur Instruction is a Branch that writes VI regs (BAL/JALR)
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#define isNOP (mVUinfo & (1<<0))
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#define isBranch (mVUinfo & (1<<1))
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@ -211,7 +213,8 @@ declareAllVariables
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#define memReadIt (mVUinfo & (1<<24))
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#define writesVI (mVUinfo & (1<<25))
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#define swapOps (mVUinfo & (1<<26))
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//#define isBranch2 (mVUinfo & (1<<27))
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#define isFSSET (mVUinfo & (1<<27))
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//#define isBranch2 (mVUinfo & (1<<28))
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#define isMMX(_VIreg_) (_VIreg_ >= 1 && _VIreg_ <=9)
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#define mmVI(_VIreg_) (_VIreg_ - 1)
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