mirror of https://github.com/PCSX2/pcsx2.git
Mostly added comments to some code. Also added a "safety" set of FreezeXMMRegs calls to gs.cpp, in a spot of code that should always be called from a frozen register state anyway (but better to be safe).
git-svn-id: http://pcsx2-playground.googlecode.com/svn/trunk@425 a6443dda-0b58-4228-96e9-037be469359c
This commit is contained in:
Jake.Stine
Gregory Hainaut
parent
be9d0ea954
commit
5a317846a5
19
pcsx2/CDVD.c
19
pcsx2/CDVD.c
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@ -672,11 +672,26 @@ void cdvdReset()
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}
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// CDVD Timing Notes...
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// As of recent IOP sync fixes, CDVD timings seem to be fairly unimportant
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// to compatibility now. Tests have shown that setting CDVD read speeds to
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// insanely low values (equating to unrealistically fast DVDdrive speeds)
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// don't break any games, nor do higher/lower speeds cause/fix IPU sync
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// problems anymore either. Games do tend to issue a lot of CDVD BREAKs
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// when the CDVD latency is very low, which are something the emulator can
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// safely ignore anyway.
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// Notable Exception : DigitalDevilSaga PAL, in which certain movies do not
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// play unless the CDVD read speed is *insanely* high (several thousand
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// cycles per block). This probably has nothing to do with the CDVD though,
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// and is likely caused by some other emulation problem that just happens
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// to be "masked over" by slowing down the CDVD.
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#define PSX_CD_READSPEED (PSXCLK / 153600) // 1 Byte Time @ x1 (150KB = cd x 1)
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#define PSX_DVD_READSPEED (PSXCLK /1382400) // normal is 1 Byte Time @ x1 (1350KB = dvd x 1)
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#define PSX_DVD_READSPEED (PSXCLK / 1382400) // normal is 1 Byte Time @ x1 (1350KB = dvd x 1)
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void cdvdReadTimeRcnt(int mode) // Mode 0 is DVD, Mode 1 is CD
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{
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{
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if (cdvd.Sector == 16) //DVD TOC
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cdvdReadTime = 30000; //simulates spin-up time, fixes hdloader
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else
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16
pcsx2/GS.cpp
16
pcsx2/GS.cpp
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@ -432,16 +432,20 @@ s32 gsOpen()
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void GS_SETEVENT()
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{
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// Win32 Kernel calls can corrupt the XMM/MMX registers.
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// Callers should always make sure those registers are frozen:
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assert( !g_EEFreezeRegs || (g_globalXMMSaved > 0) );
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event_set(g_hGsEvent);
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m_mtgsCopyCommandTally = 0;
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}
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__forceinline void gsWaitGS()
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void gsWaitGS()
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{
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if( !CHECK_MULTIGS ) return;
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// Freeze registers because some kernel code likes to destroy them
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FreezeXMMRegs(1);
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FreezeXMMRegs(1);
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FreezeMMXRegs(1);
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GS_SETEVENT();
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while( *(volatile PU8*)&g_pGSRingPos != *(volatile PU8*)&g_pGSWritePos )
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@ -511,8 +515,13 @@ void GSRINGBUF_DONECOPY(const u8* mem, u32 size)
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// 24 - very slow on HT machines (+5% drop in fps)
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// 8 - roughly 2% slower on HT machines.
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FreezeXMMRegs(1);
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FreezeMMXRegs(1);
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if( ++m_mtgsCopyCommandTally > 16 )
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GS_SETEVENT();
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FreezeXMMRegs(0);
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FreezeMMXRegs(0);
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}
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void gsShutdown()
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@ -1830,6 +1839,9 @@ extern "C" void gsPostVsyncEnd()
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//SysPrintf( " Sending VSync : %d \n", g_pGSvSyncCount );
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#endif
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GSRingBufSimplePacket(GS_RINGTYPE_VSYNC, (*(u32*)(PS2MEM_GS+0x1000)&0x2000), 0, 0);
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// No need to freeze MMX/XMM registers here since this
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// code is always called from the context of a BranchTest.
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GS_SETEVENT();
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}
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else
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@ -27,15 +27,22 @@
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#include "iR5900.h"
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#include "coroutine.h"
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// IPU Speedhack : Calls the IPU interrupt handlers directly instead of feeding
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// them through the EE's branch test. Not tested extensively yet.
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#ifdef USE_IPU_SPEEDHACK
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# define IPU_TO_INT( val ) ipu1Interrupt()
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# define IPU_FROM_INT( val ) ipu0Interrupt()
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// Zero cycle IRQ schedules aren't really good, but the IPU uses them.
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// Better to throw the IRQ inline:
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#define IPU_INT0_FROM() ipu0Interrupt()
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//#define IPU_INT0_FROM() CPU_INT( DMAC_FROM_IPU, 0 )
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// IPU Inline'd IRQs : Calls the IPU interrupt handlers directly instead of
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// feeding them through the EE's branch test. (see IPU.H for details)
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#ifdef IPU_INLINE_IRQS
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# define IPU_INT_TO( cycles ) ipu1Interrupt()
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# define IPU_INT_FROM( cycles ) ipu0Interrupt()
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# define IPU_FORCEINLINE
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#else
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# define IPU_TO_INT( val ) CPU_INT( DMAC_TO_IPU, val )
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# define IPU_FROM_INT( val ) CPU_INT( DMAC_FROM_IPU, val )
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# define IPU_INT_TO( cycles ) CPU_INT( DMAC_TO_IPU, cycles )
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# define IPU_INT_FROM( cycles ) CPU_INT( DMAC_FROM_IPU, cycles )
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# define IPU_FORCEINLINE __forceinline
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#endif
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@ -1028,7 +1035,7 @@ void IPUCMD_WRITE(u32 val) {
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if( ipuCSC(ipuRegs->cmd.DATA) ) {
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if(ipu0dma->qwc > 0 && (ipu0dma->chcr & 0x100))
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IPU_FROM_INT(0);
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IPU_INT0_FROM();
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return;
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}
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@ -1048,7 +1055,7 @@ void IPUCMD_WRITE(u32 val) {
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if( ipuIDEC(val) ) {
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// idec done, ipu0 done too
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if(ipu0dma->qwc > 0 && (ipu0dma->chcr & 0x100))
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IPU_FROM_INT(0);
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IPU_INT0_FROM();
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return;
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}
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@ -1062,7 +1069,7 @@ void IPUCMD_WRITE(u32 val) {
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case SCE_IPU_BDEC:
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if( ipuBDEC(val)) {
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if(ipu0dma->qwc > 0 && (ipu0dma->chcr & 0x100))
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IPU_FROM_INT(0);
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IPU_INT0_FROM();
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if (ipuRegs->ctrl.SCD || ipuRegs->ctrl.ECD)
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hwIntcIrq(INTC_IPU);
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@ -1135,7 +1142,7 @@ void IPUWorker()
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}
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if(ipu0dma->qwc > 0 && (ipu0dma->chcr & 0x100))
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IPU_FROM_INT(0);
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IPU_INT0_FROM();
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break;
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case SCE_IPU_PACK:
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if( !ipuPACK(ipuRegs->cmd.DATA) )
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@ -1160,7 +1167,7 @@ void IPUWorker()
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ipuCurCmd = 0xffffffff;
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// CHECK!: IPU0dma remains when IDEC is done, so we need to clear it
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if(ipu0dma->qwc > 0 && (ipu0dma->chcr & 0x100))
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IPU_FROM_INT(0);
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IPU_INT0_FROM();
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s_routine = NULL;
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break;
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@ -1177,7 +1184,7 @@ void IPUWorker()
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ipuRegs->cmd.BUSY = 0;
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ipuCurCmd = 0xffffffff;
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if(ipu0dma->qwc > 0 && (ipu0dma->chcr & 0x100))
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IPU_FROM_INT(0);
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IPU_INT0_FROM();
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s_routine = NULL;
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if (ipuRegs->ctrl.SCD || ipuRegs->ctrl.ECD)
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hwIntcIrq(INTC_IPU);
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@ -1642,7 +1649,7 @@ int IPU1dma()
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if ((ipu1dma->chcr & 0x80) && (g_nDMATransfer&IPU_DMA_DOTIE1)) { //Check TIE bit of CHCR and IRQ bit of tag
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SysPrintf("IPU1 TIE\n");
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IPU_TO_INT(totalqwc*BIAS);
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IPU_INT_TO(totalqwc*BIAS);
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g_nDMATransfer &= ~(IPU_DMA_ACTV1|IPU_DMA_DOTIE1);
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g_nDMATransfer |= IPU_DMA_TIE1;
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return totalqwc;
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@ -1651,7 +1658,7 @@ int IPU1dma()
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g_nDMATransfer &= ~(IPU_DMA_ACTV1|IPU_DMA_DOTIE1);
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if( (ipu1dma->chcr&0xc) == 0 ) {
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IPU_TO_INT(totalqwc*BIAS);
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IPU_INT_TO(totalqwc*BIAS);
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return totalqwc;
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}
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else {
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@ -1667,7 +1674,7 @@ int IPU1dma()
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ipu1dma->chcr = (ipu1dma->chcr & 0xFFFF) | ( (*ptag) & 0xFFFF0000 );
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IPU_LOG("IPU dmaIrq Set\n");
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IPU_TO_INT(totalqwc*BIAS);
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IPU_INT_TO(totalqwc*BIAS);
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g_nDMATransfer |= IPU_DMA_TIE1;
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return totalqwc;
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}
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@ -1676,12 +1683,12 @@ int IPU1dma()
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{
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case 0x00000000:
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ipu1dma->tadr += 16;
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IPU_TO_INT((1+totalqwc)*BIAS);
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IPU_INT_TO((1+totalqwc)*BIAS);
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return totalqwc;
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case 0x70000000:
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ipu1dma->tadr = ipu1dma->madr;
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IPU_TO_INT((1+totalqwc)*BIAS);
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IPU_INT_TO((1+totalqwc)*BIAS);
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return totalqwc;
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}
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}
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@ -1698,7 +1705,7 @@ int IPU1dma()
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IPU_LOG("dmaIPU1 Normal size=%d, addr=%lx, fifosize=%x\n",
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ipu1dma->qwc, ipu1dma->madr, 8 - g_BP.IFC);
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IPU1chain();
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IPU_TO_INT((ipu1cycles+totalqwc)*BIAS);
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IPU_INT_TO((ipu1cycles+totalqwc)*BIAS);
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return totalqwc;
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}
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else
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@ -1780,35 +1787,31 @@ int IPU1dma()
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ipu1dma->chcr = (ipu1dma->chcr & 0xFFFF) | ( (*ptag) & 0xFFFF0000 );
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}
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IPU_TO_INT(ipu1cycles+totalqwc*BIAS);
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IPU_INT_TO(ipu1cycles+totalqwc*BIAS);
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g_nDMATransfer |= IPU_DMA_TIE1;
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return totalqwc;
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}
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//}
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if(ipu1dma->qwc == 0){
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switch( ptag[0]&0x70000000 )
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if(ipu1dma->qwc == 0)
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{
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case 0x00000000:
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ipu1dma->tadr += 16;
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IPU_TO_INT((ipu1cycles+totalqwc)*BIAS);
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return totalqwc;
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case 0x70000000:
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ipu1dma->tadr = ipu1dma->madr;
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IPU_TO_INT((ipu1cycles+totalqwc)*BIAS);
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return totalqwc;
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}
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switch( ptag[0]&0x70000000 )
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{
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case 0x00000000:
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ipu1dma->tadr += 16;
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break;
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case 0x70000000:
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ipu1dma->tadr = ipu1dma->madr;
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break;
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}
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}
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}
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IPU_TO_INT((ipu1cycles+totalqwc)*BIAS);
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IPU_INT_TO((ipu1cycles+totalqwc)*BIAS);
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return totalqwc;
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}
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int FIFOfrom_write(u32 *value,int size)
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{
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int transsize;
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@ -1910,7 +1913,7 @@ int IPU0dma()
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break;
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}
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}
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IPU_FROM_INT(readsize*BIAS);
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IPU_INT_FROM( readsize*BIAS );
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}
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return readsize;
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@ -1932,7 +1935,7 @@ void dmaIPU1() // toIPU
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extern void GIFdma();
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IPU_FORCEINLINE void ipu0Interrupt() {
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void ipu0Interrupt() {
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IPU_LOG("ipu0Interrupt: %x\n", cpuRegs.cycle);
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if( g_nDMATransfer & IPU_DMA_FIREINT0 ) {
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@ -21,12 +21,20 @@
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#include "Common.h"
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// IPU Speed Hack!
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// By uncommenting the define below, the IPU can get a pretty nice speed boost,
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// of about 10%. Additionally, the ipuInterrupt handlers in the cpuBranchTest
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// are also be removed, which helps reduce branch test overhead in *all* games.
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// IPU_INLINE_IRQS
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// Scheduling ints into the future is a purist approach to emulation, and
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// is mostly cosmetic since the emulator itself performs all actions instantly
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// (as far as the emulated CPU is concerned). In some cases this can actually
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// cause more sync problems than it supposedly solves, due to accumulated
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// delays incurred by the recompiler's low cycle update rate and also Pcsx2
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// failing to properly handle pre-emptive DMA/IRQs or cpu exceptions.
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//#define USE_IPU_SPEEDHACK
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// Uncomment the following line to enable inline IRQs for the IPU. Tests show
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// that it doesn't have any effect on compatibility or audio/video sync, and it
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// speeds up movie playback by some 6-8%. But it lacks the purist touch, so it's
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// not enabled by default.
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//#define IPU_INLINE_IRQS
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#ifdef _MSC_VER
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@ -32,7 +32,7 @@ u32 g_psxHasConstReg, g_psxFlushedConstReg;
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// Controls when branch tests are performed.
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u32 g_psxNextBranchCycle = 0;
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// This value is used when the IOP execution is broken to return contorl to the EE.
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// This value is used when the IOP execution is broken to return control to the EE.
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// (which happens when the IOP throws EE-bound interrupts). It holds the value of
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// psxCycleEE (which is set to zero to facilitate the code break), so that the unrun
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// cycles can be accounted for later.
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@ -42,6 +42,9 @@ s32 psxBreak = 0;
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// control is returned to the EE.
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s32 psxCycleEE = -1;
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// Used to signal to the EE when important actions that need IOP-attention have
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// happened (hsyncs, vsyncs, IOP exceptions, etc). IOP runs code whenever this
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// is true, even if it's already running ahead a bit.
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int iopBranchAction = 0;
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16
pcsx2/Sio.c
16
pcsx2/Sio.c
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@ -34,7 +34,17 @@ FILE * MemoryCard1, * MemoryCard2;
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const unsigned char cardh[4] = { 0xFF, 0xFF, 0x5a, 0x5d };
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// Memory Card Specs : Sector size etc.
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struct mc_command_0x26_tag mc_command_0x26= {'+', 512, 16, 0x4000, 0x52, 0x5A};
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#define SIO_INT() PSX_INT(16, PSXCLK/250000); /*270;*/
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// SIO Inline'd IRQs : Calls the SIO interrupt handlers directly instead of
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// feeding them through the IOP's branch test. (see SIO.H for details)
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#ifdef SIO_INLINE_IRQS
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#define SIO_INT() sioInterrupt()
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#define SIO_FORCEINLINE
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#else
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#define SIO_INT() PSX_INT(16, PSXCLK/250000);
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#define SIO_FORCEINLINE __forceinline
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#endif
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void _ReadMcd(char *data, u32 adr, int size) {
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ReadMcd(sio.CtrlReg&0x2000?2:1, data, adr, size);
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@ -348,7 +358,7 @@ void SIO_CommandWrite(u8 value,int way) {
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_SaveMcd(sio.buf, (512+16)*sio.sector+256, 256);
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_SaveMcd(sio.buf, (512+16)*sio.sector+512, 16);
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sio.buf[2]='+';
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*/ sio.buf[3]=sio.terminator;
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sio.buf[3]=sio.terminator;*/
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//sio.buf[sio.bufcount] = sio.terminator;
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MEMCARDS_LOG("MC(%d) INTERNAL ERASE command 0x%02X\n", ((sio.CtrlReg&0x2000)>>13)+1, value);
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}
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@ -497,7 +507,7 @@ void sioWriteCtrl16(unsigned short value) {
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}
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}
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__forceinline void sioInterrupt() {
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void sioInterrupt() {
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PAD_LOG("Sio Interrupt\n");
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sio.StatReg|= IRQ;
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psxHu32(0x1070)|=0x80;
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18
pcsx2/Sio.h
18
pcsx2/Sio.h
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@ -20,6 +20,24 @@
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#ifndef _SIO_H_
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#define _SIO_H_
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// SIO IRQ Timings...
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// Scheduling ints into the future is a purist approach to emulation, and
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// is mostly cosmetic since the emulator itself performs all actions instantly
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// (as far as the emulated CPU is concerned). In some cases this can actually
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// cause more sync problems than it supposedly solves, due to accumulated
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// delays incurred by the recompiler's low cycle update rate and also Pcsx2
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// failing to properly handle pre-emptive DMA/IRQs or cpu exceptions.
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// The SIO is one of these cases, where-by many games seem to be a lot happier
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// if the SIO handles its IRQs instantly instead of scheduling them.
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// Uncomment the line below for SIO instant-IRQ mode. It improves responsiveness
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// considerably, fixes PAD latency problems in some games, and may even reduce the
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// chance of saves getting corrupted (untested). But it lacks the purist touch,
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// so it's not enabled by default.
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//#define SIO_INLINE_IRQS
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typedef struct {
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u16 StatReg;
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u16 ModeReg;
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Loading…
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