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pcsx2
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I give up on the dmac branch. It will be easier to just do this in trunk, since it can be easily turned off. 

I made it so each part can be enabled separately, but atm they are missing some code so nothing will work if enabled.
Commit is mostly for backup/history purposes.

git-svn-id: http://pcsx2.googlecode.com/svn/trunk@2486 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
gigaherz 2010-01-23 03:28:32 +00:00
parent 84bc805761
commit 5715c181dc
9 changed files with 312 additions and 167 deletions
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51
common/include/PS2Edefs.h
View File

@ -16,6 +16,15 @@
#ifndef __PS2EDEFS_H__ #ifndef __PS2EDEFS_H__
#define __PS2EDEFS_H__ #define __PS2EDEFS_H__
//#define ENABLE_NEW_IOPDMA
#ifdef ENABLE_NEW_IOPDMA
//#define ENABLE_NEW_IOPDMA_SPU2
//#define ENABLE_NEW_IOPDMA_SIO
//#define ENABLE_NEW_IOPDMA_CDVD
#endif
/* /*
* PS2E Definitions v0.6.2 (beta) * PS2E Definitions v0.6.2 (beta)
* *
@ -90,7 +99,11 @@ typedef struct _keyEvent {
// PS2EgetLibVersion2 (high 16 bits) // PS2EgetLibVersion2 (high 16 bits)
#define PS2E_GS_VERSION 0x0006 #define PS2E_GS_VERSION 0x0006
#define PS2E_PAD_VERSION 0x0002 // -=[ OBSOLETE ]=- #define PS2E_PAD_VERSION 0x0002 // -=[ OBSOLETE ]=-
#ifdef ENABLE_NEW_IOPDMA_SPU2
#define PS2E_SPU2_VERSION 0x0006
#else
#define PS2E_SPU2_VERSION 0x0005 #define PS2E_SPU2_VERSION 0x0005
#endif
#define PS2E_CDVD_VERSION 0x0005 #define PS2E_CDVD_VERSION 0x0005
#define PS2E_DEV9_VERSION 0x0003 #define PS2E_DEV9_VERSION 0x0003
#define PS2E_USB_VERSION 0x0003 #define PS2E_USB_VERSION 0x0003
@ -322,6 +335,15 @@ void CALLBACK SPU2setSettingsDir( const char* dir );
void CALLBACK SPU2write(u32 mem, u16 value); void CALLBACK SPU2write(u32 mem, u16 value);
u16 CALLBACK SPU2read(u32 mem); u16 CALLBACK SPU2read(u32 mem);
#ifdef ENABLE_NEW_IOPDMA_SPU2
s32 CALLBACK SPU2dmaRead(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed);
s32 CALLBACK SPU2dmaWrite(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed);
void CALLBACK SPU2dmaInterrupt(s32 channel);
// dma irq callbacks not needed anymore, they are handled by the dmac
void CALLBACK SPU2irqCallback(void (*SPU2callback)());
#else
void CALLBACK SPU2readDMA4Mem(u16 *pMem, int size); void CALLBACK SPU2readDMA4Mem(u16 *pMem, int size);
void CALLBACK SPU2writeDMA4Mem(u16 *pMem, int size); void CALLBACK SPU2writeDMA4Mem(u16 *pMem, int size);
void CALLBACK SPU2interruptDMA4(); void CALLBACK SPU2interruptDMA4();
@ -333,9 +355,12 @@ void CALLBACK SPU2writeDMA7Mem(u16 *pMem, int size);
void CALLBACK SPU2setDMABaseAddr(uptr baseaddr); void CALLBACK SPU2setDMABaseAddr(uptr baseaddr);
void CALLBACK SPU2interruptDMA7(); void CALLBACK SPU2interruptDMA7();
u32 CALLBACK SPU2ReadMemAddr(int core); u32 CALLBACK SPU2ReadMemAddr(int core);
void CALLBACK SPU2WriteMemAddr(int core,u32 value); void CALLBACK SPU2WriteMemAddr(int core,u32 value);
void CALLBACK SPU2irqCallback(void (*SPU2callback)(),void (*DMA4callback)(),void (*DMA7callback)()); void CALLBACK SPU2irqCallback(void (*SPU2callback)(),void (*DMA4callback)(),void (*DMA7callback)());
#endif
// extended funcs // extended funcs
// if start is 1, starts recording spu2 data, else stops // if start is 1, starts recording spu2 data, else stops
@ -563,6 +588,15 @@ typedef s32 (CALLBACK* _PADqueryMtap)(u8 port);
typedef s32 (CALLBACK* _SPU2open)(void *pDsp); typedef s32 (CALLBACK* _SPU2open)(void *pDsp);
typedef void (CALLBACK* _SPU2write)(u32 mem, u16 value); typedef void (CALLBACK* _SPU2write)(u32 mem, u16 value);
typedef u16 (CALLBACK* _SPU2read)(u32 mem); typedef u16 (CALLBACK* _SPU2read)(u32 mem);
#ifdef ENABLE_NEW_IOPDMA_SPU2
typedef s32 (CALLBACK* _SPU2dmaRead)(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed);
typedef s32 (CALLBACK* _SPU2dmaWrite)(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed);
typedef void (CALLBACK* _SPU2dmaInterrupt)(s32 channel);
// dma irq callbacks not needed anymore, they are handled by the dmac
typedef void (CALLBACK* _SPU2irqCallback)(void (*SPU2callback)());
#else
typedef void (CALLBACK* _SPU2readDMA4Mem)(u16 *pMem, int size); typedef void (CALLBACK* _SPU2readDMA4Mem)(u16 *pMem, int size);
typedef void (CALLBACK* _SPU2writeDMA4Mem)(u16 *pMem, int size); typedef void (CALLBACK* _SPU2writeDMA4Mem)(u16 *pMem, int size);
typedef void (CALLBACK* _SPU2interruptDMA4)(); typedef void (CALLBACK* _SPU2interruptDMA4)();
@ -571,13 +605,15 @@ typedef void (CALLBACK* _SPU2writeDMA7Mem)(u16 *pMem, int size);
typedef void (CALLBACK* _SPU2setDMABaseAddr)(uptr baseaddr); typedef void (CALLBACK* _SPU2setDMABaseAddr)(uptr baseaddr);
typedef void (CALLBACK* _SPU2interruptDMA7)(); typedef void (CALLBACK* _SPU2interruptDMA7)();
typedef void (CALLBACK* _SPU2irqCallback)(void (*SPU2callback)(),void (*DMA4callback)(),void (*DMA7callback)()); typedef void (CALLBACK* _SPU2irqCallback)(void (*SPU2callback)(),void (*DMA4callback)(),void (*DMA7callback)());
typedef u32 (CALLBACK* _SPU2ReadMemAddr)(int core);
typedef void (CALLBACK* _SPU2WriteMemAddr)(int core,u32 value);
#endif
typedef int (CALLBACK* _SPU2setupRecording)(int, void*); typedef int (CALLBACK* _SPU2setupRecording)(int, void*);
typedef void (CALLBACK* _SPU2setClockPtr)(u32*ptr); typedef void (CALLBACK* _SPU2setClockPtr)(u32*ptr);
typedef void (CALLBACK* _SPU2setTimeStretcher)(short int enable); typedef void (CALLBACK* _SPU2setTimeStretcher)(short int enable);
typedef u32 (CALLBACK* _SPU2ReadMemAddr)(int core);
typedef void (CALLBACK* _SPU2WriteMemAddr)(int core,u32 value);
typedef void (CALLBACK* _SPU2async)(u32 cycles); typedef void (CALLBACK* _SPU2async)(u32 cycles);
@ -696,6 +732,12 @@ extern _PADqueryMtap PADqueryMtap;
extern _SPU2open SPU2open; extern _SPU2open SPU2open;
extern _SPU2write SPU2write; extern _SPU2write SPU2write;
extern _SPU2read SPU2read; extern _SPU2read SPU2read;
#ifdef ENABLE_NEW_IOPDMA_SPU2
extern _SPU2dmaRead SPU2dmaRead;
extern _SPU2dmaWrite SPU2dmaWrite;
extern _SPU2dmaInterrupt SPU2dmaInterrupt;
#else
extern _SPU2readDMA4Mem SPU2readDMA4Mem; extern _SPU2readDMA4Mem SPU2readDMA4Mem;
extern _SPU2writeDMA4Mem SPU2writeDMA4Mem; extern _SPU2writeDMA4Mem SPU2writeDMA4Mem;
extern _SPU2interruptDMA4 SPU2interruptDMA4; extern _SPU2interruptDMA4 SPU2interruptDMA4;
@ -707,6 +749,11 @@ extern _SPU2ReadMemAddr SPU2ReadMemAddr;
extern _SPU2setupRecording SPU2setupRecording; extern _SPU2setupRecording SPU2setupRecording;
extern _SPU2WriteMemAddr SPU2WriteMemAddr; extern _SPU2WriteMemAddr SPU2WriteMemAddr;
extern _SPU2irqCallback SPU2irqCallback; extern _SPU2irqCallback SPU2irqCallback;
#endif
extern _SPU2irqCallback SPU2irqCallback;
extern _SPU2setupRecording SPU2setupRecording;
extern _SPU2setClockPtr SPU2setClockPtr; extern _SPU2setClockPtr SPU2setClockPtr;
extern _SPU2setTimeStretcher SPU2setTimeStretcher; extern _SPU2setTimeStretcher SPU2setTimeStretcher;

6
pcsx2/CDVD/CdRom.cpp
View File

@ -937,6 +937,7 @@ void psxDma3(u32 madr, u32 bcr, u32 chcr) {
#ifdef ENABLE_NEW_IOPDMA #ifdef ENABLE_NEW_IOPDMA
s32 cdvdDmaRead(s32 channel, u32* data, u32 wordsLeft, u32* wordsProcessed) s32 cdvdDmaRead(s32 channel, u32* data, u32 wordsLeft, u32* wordsProcessed)
{ {
#ifdef ENABLE_NEW_IOPDMA_CDVD
// hacked up from the code above // hacked up from the code above
if (cdr.Readed == 0) if (cdr.Readed == 0)
@ -951,13 +952,16 @@ s32 cdvdDmaRead(s32 channel, u32* data, u32 wordsLeft, u32* wordsProcessed)
cdr.pTransfer+=wordsLeft; cdr.pTransfer+=wordsLeft;
*wordsProcessed = wordsLeft; *wordsProcessed = wordsLeft;
Console.Status("New IOP DMA handled CDVD DMA: channel %d, data %p, remaining %08x, processed %08x.", channel,data,wordsLeft, *wordsProcessed); Console.WriteLn(Color_Black,"New IOP DMA handled CDVD DMA: channel %d, data %p, remaining %08x, processed %08x.", channel,data,wordsLeft, *wordsProcessed);
#endif
return 0; return 0;
} }
void cdvdDmaInterrupt(s32 channel) void cdvdDmaInterrupt(s32 channel)
{ {
#ifdef ENABLE_NEW_IOPDMA_CDVD
cdrInterrupt(); cdrInterrupt();
#endif
} }
#endif #endif

261
pcsx2/IopDma.cpp
View File

@ -28,6 +28,7 @@ using namespace R3000A;
bool iopsifbusy[2] = { false, false }; bool iopsifbusy[2] = { false, false };
extern bool eesifbusy[2]; extern bool eesifbusy[2];
#ifndef ENABLE_NEW_IOPDMA_SPU2
static void __fastcall psxDmaGeneric(u32 madr, u32 bcr, u32 chcr, u32 spuCore, _SPU2writeDMA4Mem spu2WriteFunc, _SPU2readDMA4Mem spu2ReadFunc) static void __fastcall psxDmaGeneric(u32 madr, u32 bcr, u32 chcr, u32 spuCore, _SPU2writeDMA4Mem spu2WriteFunc, _SPU2readDMA4Mem spu2ReadFunc)
{ {
const char dmaNum = spuCore ? '7' : '4'; const char dmaNum = spuCore ? '7' : '4';
@ -78,6 +79,7 @@ static void __fastcall psxDmaGeneric(u32 madr, u32 bcr, u32 chcr, u32 spuCore, _
break; break;
} }
} }
#endif
void psxDma2(u32 madr, u32 bcr, u32 chcr) // GPU void psxDma2(u32 madr, u32 bcr, u32 chcr) // GPU
{ {
@ -87,6 +89,7 @@ void psxDma2(u32 madr, u32 bcr, u32 chcr) // GPU
/* psxDma3 is in CdRom.cpp */ /* psxDma3 is in CdRom.cpp */
#ifndef ENABLE_NEW_IOPDMA_SPU2
void psxDma4(u32 madr, u32 bcr, u32 chcr) // SPU2's Core 0 void psxDma4(u32 madr, u32 bcr, u32 chcr) // SPU2's Core 0
{ {
psxDmaGeneric(madr, bcr, chcr, 0, SPU2writeDMA4Mem, SPU2readDMA4Mem); psxDmaGeneric(madr, bcr, chcr, 0, SPU2writeDMA4Mem, SPU2readDMA4Mem);
@ -99,6 +102,7 @@ int psxDma4Interrupt()
iopIntcIrq(9); iopIntcIrq(9);
return 1; return 1;
} }
#endif
void psxDma6(u32 madr, u32 bcr, u32 chcr) void psxDma6(u32 madr, u32 bcr, u32 chcr)
{ {
@ -125,6 +129,7 @@ void psxDma6(u32 madr, u32 bcr, u32 chcr)
psxDmaInterrupt(6); psxDmaInterrupt(6);
} }
#ifndef ENABLE_NEW_IOPDMA_SPU2
void psxDma7(u32 madr, u32 bcr, u32 chcr) // SPU2's Core 1 void psxDma7(u32 madr, u32 bcr, u32 chcr) // SPU2's Core 1
{ {
psxDmaGeneric(madr, bcr, chcr, 1, SPU2writeDMA7Mem, SPU2readDMA7Mem); psxDmaGeneric(madr, bcr, chcr, 1, SPU2writeDMA7Mem, SPU2readDMA7Mem);
@ -137,6 +142,7 @@ int psxDma7Interrupt()
return 1; return 1;
} }
#endif
void psxDma8(u32 madr, u32 bcr, u32 chcr) void psxDma8(u32 madr, u32 bcr, u32 chcr)
{ {
@ -229,6 +235,7 @@ void fwIrq()
hwIntcIrq(INTC_SBUS); hwIntcIrq(INTC_SBUS);
} }
#ifndef ENABLE_NEW_IOPDMA_SPU2
void spu2DMA4Irq() void spu2DMA4Irq()
{ {
SPU2interruptDMA4(); SPU2interruptDMA4();
@ -242,6 +249,7 @@ void spu2DMA7Irq()
HW_DMA7_CHCR &= ~0x01000000; HW_DMA7_CHCR &= ~0x01000000;
psxDmaInterrupt2(0); psxDmaInterrupt2(0);
} }
#endif
void spu2Irq() void spu2Irq()
{ {
@ -264,90 +272,36 @@ void iopIntcIrq(uint irqType)
s32 spu2DmaRead(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed) s32 spu2DmaRead(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed)
{ {
// FIXME: change the plugin interfaces so that they are aware of this new dma handler #ifdef ENABLE_NEW_IOPDMA_SPU2
return SPU2dmaRead(channel,data,bytesLeft,bytesProcessed);
/* #else
u32 bytes = 1024;
if(bytesLeft<1024)
bytes=bytesLeft;
*/
u32 bytes=bytesLeft;
// Update the spu2 to the current cycle before initiating the DMA
if (SPU2async)
{
SPU2async(psxRegs.cycle - psxCounters[6].sCycleT);
//Console.Status("cycles sent to SPU2 %x\n", psxRegs.cycle - psxCounters[6].sCycleT);
psxCounters[6].sCycleT = psxRegs.cycle;
psxCounters[6].CycleT = bytes * 3;
psxNextCounter -= (psxRegs.cycle - psxNextsCounter);
psxNextsCounter = psxRegs.cycle;
if (psxCounters[6].CycleT < psxNextCounter)
psxNextCounter = psxCounters[6].CycleT;
}
if(channel==7)
SPU2readDMA7Mem((u16 *)data, bytes/2);
else
SPU2readDMA4Mem((u16 *)data, bytes/2);
*bytesProcessed = bytes;
return 0; return 0;
#endif
} }
s32 spu2DmaWrite(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed) s32 spu2DmaWrite(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed)
{ {
// FIXME: change the plugin interfaces so that they are aware of this new dma handler #ifdef ENABLE_NEW_IOPDMA_SPU2
return SPU2dmaWrite(channel,data,bytesLeft,bytesProcessed);
#else
/*
u32 bytes = 1024;
if(bytesLeft<1024)
bytes=bytesLeft;
*/
u32 bytes=bytesLeft;
// Update the spu2 to the current cycle before initiating the DMA
if (SPU2async)
{
SPU2async(psxRegs.cycle - psxCounters[6].sCycleT);
//Console.Status("cycles sent to SPU2 %x\n", psxRegs.cycle - psxCounters[6].sCycleT);
psxCounters[6].sCycleT = psxRegs.cycle;
psxCounters[6].CycleT = bytes * 3;
psxNextCounter -= (psxRegs.cycle - psxNextsCounter);
psxNextsCounter = psxRegs.cycle;
if (psxCounters[6].CycleT < psxNextCounter)
psxNextCounter = psxCounters[6].CycleT;
}
if(channel==7)
SPU2writeDMA7Mem((u16 *)data, bytes/2);
else
SPU2writeDMA4Mem((u16 *)data, bytes/2);
*bytesProcessed = bytes;
return 0; return 0;
#endif
} }
void spu2DmaInterrupt(s32 channel) void spu2DmaInterrupt(s32 channel)
{ {
if(channel==7) #ifdef ENABLE_NEW_IOPDMA_SPU2
SPU2interruptDMA7(); SPU2dmaInterrupt(channel);
else #endif
SPU2interruptDMA4();
} }
//typedef s32(* DmaHandler)(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed); //typedef s32(* DmaHandler)(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed);
//typedef void (* DmaIHandler)(s32 channel); //typedef void (* DmaIHandler)(s32 channel);
extern s32 sio2DmaRead(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed);
extern s32 sio2DmaWrite(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed);
extern void sio2DmaInterrupt(s32 channel);
s32 errDmaWrite(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed); s32 errDmaWrite(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed);
s32 errDmaRead(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed); s32 errDmaRead(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed);
@ -355,43 +309,34 @@ DmaStatusInfo IopChannels[DMA_CHANNEL_MAX]; // I dont' knwo how many there are,
DmaHandlerInfo IopDmaHandlers[DMA_CHANNEL_MAX] = DmaHandlerInfo IopDmaHandlers[DMA_CHANNEL_MAX] =
{ {
{0}, //0 // First DMAC, same as PS1
{0}, //1 {"Ps1 Mdec", 0}, //0
{0}, //2 {"Ps1 Mdec", 0}, //1
{cdvdDmaRead, errDmaWrite, cdvdDmaInterrupt}, //3: CDVD {"Ps1 Gpu", 0}, //2
{spu2DmaRead, spu2DmaWrite, spu2DmaInterrupt}, //4: Spu Core0 {"CDVD", cdvdDmaRead, errDmaWrite, cdvdDmaInterrupt}, //3: CDVD
{0}, //5 {"SPU2 Core0", spu2DmaRead, spu2DmaWrite, spu2DmaInterrupt}, //4: Spu Core0
{0}, //6: OT? {"?", 0}, //5
{spu2DmaRead, spu2DmaWrite, spu2DmaInterrupt}, //7: Spu Core1 {"OT", 0}, //6: OT?
{0},//{dev9DmaRead, dev9DmaWrite, dev9DmaInterrupt}, //8: Dev9
{0},//{sif0DmaRead, sif0DmaWrite, sif0DmaInterrupt}, //9: SIF0
{0},//{sif1DmaRead, sif1DmaWrite, sif1DmaInterrupt}, //10: SIF1
{0}, // Sio2
{0}, // Sio2
};
const char* IopDmaNames[DMA_CHANNEL_MAX] = // Second DMAC, new in PS2 IOP
{ {"SPU2 Core1", spu2DmaRead, spu2DmaWrite, spu2DmaInterrupt}, //7: Spu Core1
"Ps1 Mdec", {"Dev9", 0},//dev9DmaRead, dev9DmaWrite, dev9DmaInterrupt}, //8: Dev9
"Ps1 Mdec", {"Sif0", 0},//sif0DmaRead, sif0DmaWrite, sif0DmaInterrupt}, //9: SIF0
"Ps1 Gpu", {"Sif1", 0},//sif1DmaRead, sif1DmaWrite, sif1DmaInterrupt}, //10: SIF1
"CDVD", {"Sio2 (writes)", errDmaRead, sio2DmaWrite, sio2DmaInterrupt}, //11: Sio2
"SPU/SPU2 Core0", {"Sio2 (reads)", sio2DmaRead, errDmaWrite, sio2DmaInterrupt}, //12: Sio2
"?", {"?", 0}, //13
"OT", // if each dmac has 7 channels, the list would end here, but i made it 16 cos I'm not sure :p
"SPU2 Core1", //7: Spu Core1 {"?", 0}, //14
"Dev9", //8: Dev9 {"?", 0}, //15
"Sif0", //9: SIF0
"Sif1", //10: SIF1
"Sio2",//...
"Sio2",
"?", "?", "?"
}; };
// Prototypes. To be implemented later (or in other parts of the emulator) // Prototypes. To be implemented later (or in other parts of the emulator)
void SetDmaUpdateTarget(u32 delay) void SetDmaUpdateTarget(u32 delay)
{ {
psxCounters[8].CycleT = delay; psxCounters[8].CycleT = delay;
if (delay < psxNextCounter)
psxNextCounter = delay;
} }
void RaiseDmaIrq(u32 channel) void RaiseDmaIrq(u32 channel)
@ -402,7 +347,6 @@ void RaiseDmaIrq(u32 channel)
psxDmaInterrupt2(channel-7); psxDmaInterrupt2(channel-7);
} }
// WARNING: CALLER ****[MUST]**** CALL IopDmaUpdate RIGHT AFTER THIS!
void IopDmaStart(int channel, u32 chcr, u32 madr, u32 bcr) void IopDmaStart(int channel, u32 chcr, u32 madr, u32 bcr)
{ {
// I dont' really understand this, but it's used above. Is this BYTES OR WHAT? // I dont' really understand this, but it's used above. Is this BYTES OR WHAT?
@ -411,64 +355,93 @@ void IopDmaStart(int channel, u32 chcr, u32 madr, u32 bcr)
IopChannels[channel].Control = chcr | DMA_CTRL_ACTIVE; IopChannels[channel].Control = chcr | DMA_CTRL_ACTIVE;
IopChannels[channel].MemAddr = madr; IopChannels[channel].MemAddr = madr;
IopChannels[channel].ByteCount = size; IopChannels[channel].ByteCount = size;
IopChannels[channel].Target=0;
SetDmaUpdateTarget(0); //SetDmaUpdateTarget(1);
{
const s32 difference = psxRegs.cycle - psxCounters[8].sCycleT;
psxCounters[8].sCycleT = psxRegs.cycle;
psxCounters[8].CycleT = psxCounters[8].rate;
IopDmaUpdate(difference);
s32 c = psxCounters[8].CycleT;
if (c < psxNextCounter) psxNextCounter = c;
}
} }
void IopDmaUpdate(u32 elapsed) void IopDmaUpdate(u32 elapsed)
{ {
s32 MinDelay = 0x7FFFFFFF; s32 MinDelay=0;
do {
MinDelay = 0x7FFFFFFF;
for (int i = 0;i < DMA_CHANNEL_MAX;i++) for (int i = 0;i < DMA_CHANNEL_MAX;i++)
{
DmaStatusInfo *ch = IopChannels + i;
if (ch->Control&DMA_CTRL_ACTIVE)
{ {
ch->Target -= elapsed; DmaStatusInfo *ch = IopChannels + i;
if (ch->Target <= 0)
if (ch->Control&DMA_CTRL_ACTIVE)
{ {
if (ch->ByteCount <= 0) ch->Target -= elapsed;
if (ch->Target <= 0)
{ {
ch->Control &= ~DMA_CTRL_ACTIVE; if (ch->ByteCount <= 0)
RaiseDmaIrq(i); {
IopDmaHandlers[i].Interrupt(i); ch->Target = 0x7fffffff;
ch->Control &= ~DMA_CTRL_ACTIVE;
RaiseDmaIrq(i);
IopDmaHandlers[i].Interrupt(i);
}
else
{
DmaHandler handler = (ch->Control & DMA_CTRL_DIRECTION) ? IopDmaHandlers[i].Write : IopDmaHandlers[i].Read;
u32 BCount = 0;
s32 Target = (handler) ? handler(i, (u32*)iopPhysMem(ch->MemAddr), ch->ByteCount, &BCount) : 0;
if(BCount>0)
{
psxCpu->Clear(ch->MemAddr, BCount/4);
}
int TTarget = 100;
if (Target < 0)
{
// TODO: ... What to do if the handler gives an error code? :P
}
else if (BCount > 0)
{
ch->MemAddr += BCount;
ch->ByteCount -= BCount;
TTarget = BCount/4; // / ch->Width;
}
if (Target != 0) TTarget = Target;
ch->Target += TTarget;
TTarget = ch->Target;
if(TTarget < 0)
TTarget = 0;
if (TTarget<MinDelay)
MinDelay = TTarget;
}
} }
else else
{ {
// TODO: Make sure it's the right order int TTarget = ch->Target;
DmaHandler handler = (ch->Control & DMA_CTRL_DIRECTION) ? IopDmaHandlers[i].Write : IopDmaHandlers[i].Read; if (TTarget<MinDelay)
MinDelay = TTarget;
u32 BCount = 0;
s32 Target = (handler) ? handler(i, (u32*)iopPhysMem(ch->MemAddr), ch->ByteCount, &BCount) : 0;
if(BCount>0)
{
psxCpu->Clear(ch->MemAddr, BCount/4);
}
int TTarget = 100;
if (Target < 0)
{
// TODO: ... What to do if the plugin errors? :P
}
else if (BCount != 0)
{
ch->MemAddr += BCount;
ch->ByteCount -= BCount;
TTarget = BCount; // / ch->Width;
}
if (Target != 0) TTarget = Target;
if (ch->Target<MinDelay) MinDelay = TTarget;
ch->Target += TTarget;
} }
} }
} }
elapsed=0;
} }
while(MinDelay <= 0);
if(MinDelay<0x7FFFFFFF) if(MinDelay<0x7FFFFFFF)
SetDmaUpdateTarget(MinDelay); SetDmaUpdateTarget(MinDelay);
@ -478,7 +451,7 @@ void IopDmaUpdate(u32 elapsed)
s32 errDmaRead(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed) s32 errDmaRead(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed)
{ {
Console.Error("ERROR: Tried to read using DMA %d (%s). Ignoring.", 0, channel, IopDmaNames[channel]); Console.Error("ERROR: Tried to read using DMA %d (%s). Ignoring.", 0, channel, IopDmaHandlers[channel]);
*bytesProcessed = bytesLeft; *bytesProcessed = bytesLeft;
return 0; return 0;
@ -486,7 +459,7 @@ s32 errDmaRead(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed)
s32 errDmaWrite(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed) s32 errDmaWrite(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed)
{ {
Console.Error("ERROR: Tried to write using DMA %d (%s). Ignoring.", 0, channel, IopDmaNames[channel]); Console.Error("ERROR: Tried to write using DMA %d (%s). Ignoring.", 0, channel, IopDmaHandlers[channel]);
*bytesProcessed = bytesLeft; *bytesProcessed = bytesLeft;
return 0; return 0;

8
pcsx2/IopDma.h
View File

@ -18,7 +18,7 @@
#include "PS2Edefs.h" #include "PS2Edefs.h"
//#define ENABLE_NEW_IOPDMA // defined in PS2Edefs.h
#ifdef ENABLE_NEW_IOPDMA #ifdef ENABLE_NEW_IOPDMA
@ -27,6 +27,7 @@ typedef void (* DmaIHandler)(s32 channel);
struct DmaHandlerInfo struct DmaHandlerInfo
{ {
const char* Name;
DmaHandler Read; DmaHandler Read;
DmaHandler Write; DmaHandler Write;
DmaIHandler Interrupt; DmaIHandler Interrupt;
@ -37,7 +38,7 @@ struct DmaStatusInfo
u32 Control; u32 Control;
u32 Width; // bytes/word, for timing purposes u32 Width; // bytes/word, for timing purposes
u32 MemAddr; u32 MemAddr;
u32 ByteCount; s32 ByteCount;
s32 Target; s32 Target;
}; };
@ -47,7 +48,8 @@ struct DmaStatusInfo
#define DMA_CHANNEL_MAX 16 /* ? */ #define DMA_CHANNEL_MAX 16 /* ? */
// WARNING: CALLER ****[MUST]**** CALL IopDmaUpdate RIGHT AFTER THIS! extern DmaStatusInfo IopChannels[DMA_CHANNEL_MAX];
extern void IopDmaStart(int channel, u32 chcr, u32 madr, u32 bcr); extern void IopDmaStart(int channel, u32 chcr, u32 madr, u32 bcr);
extern void IopDmaUpdate(u32 elapsed); extern void IopDmaUpdate(u32 elapsed);

69
pcsx2/IopSio2.cpp
View File

@ -210,6 +210,74 @@ void SaveStateBase::sio2Freeze()
///////////////////////////////////////////////// /////////////////////////////////////////////////
//////////////////////////////////////////// DMA //////////////////////////////////////////// DMA
///////////////////////////////////////////////// /////////////////////////////////////////////////
#ifdef ENABLE_NEW_IOPDMA
s32 sio2DmaRead(s32 channel, u32* tdata, u32 bytesLeft, u32* bytesProcessed)
{
#ifdef ENABLE_NEW_IOPDMA_SIO
u8* data = (u8*)tdata;
if(channel!=12)
return -1;
sio2.recvIndex = 0; // Set To start; saqib
int read = 0;
while (bytesLeft > 0)
{
(*(data++)) = sio2_fifoOut();
bytesLeft--;
read++;
if(sio2.recvIndex == sio2.packet.sendSize)
{
PSX_INT(IopEvt_Dma12,read/2); // Interrupts should always occur at the end
break;
}
}
*bytesProcessed = read;
#endif
return 0;
}
s32 sio2DmaWrite(s32 channel, u32* tdata, u32 bytesLeft, u32* bytesProcessed)
{
#ifdef ENABLE_NEW_IOPDMA_SIO
u8* data = (u8*)tdata;
if(channel!=11)
return -1;
//int available = sio2_getFifoInFree();
int written = 0;
for(int i = 0; i < bytesLeft; i++)
{
sio.count = 1;
sio2_fifoIn(*(data++));
written++;
if(sio2.packet.sendSize == BUFSIZE)
{
PSX_INT(IopEvt_Dma11,written/2); // Interrupts should always occur at the end
break;
}
}
*bytesProcessed = written;
#endif
return 0;
}
void sio2DmaInterrupt(s32 channel)
{
#ifdef ENABLE_NEW_IOPDMA_SIO
#endif
}
//#else
#endif
void psxDma11(u32 madr, u32 bcr, u32 chcr) { void psxDma11(u32 madr, u32 bcr, u32 chcr) {
unsigned int i, j; unsigned int i, j;
@ -265,3 +333,4 @@ void psxDMA12Interrupt()
psxDmaInterrupt2(5); psxDmaInterrupt2(5);
} }
//#endif

20
pcsx2/PluginManager.cpp
View File

@ -203,6 +203,11 @@ static void PAD_update( u32 padslot ) { }
_SPU2open SPU2open; _SPU2open SPU2open;
_SPU2write SPU2write; _SPU2write SPU2write;
_SPU2read SPU2read; _SPU2read SPU2read;
#ifdef ENABLE_NEW_IOPDMA_SPU2
_SPU2dmaRead SPU2dmaRead;
_SPU2dmaWrite SPU2dmaWrite;
_SPU2dmaInterrupt SPU2dmaInterrupt;
#else
_SPU2readDMA4Mem SPU2readDMA4Mem; _SPU2readDMA4Mem SPU2readDMA4Mem;
_SPU2writeDMA4Mem SPU2writeDMA4Mem; _SPU2writeDMA4Mem SPU2writeDMA4Mem;
_SPU2interruptDMA4 SPU2interruptDMA4; _SPU2interruptDMA4 SPU2interruptDMA4;
@ -211,8 +216,9 @@ _SPU2writeDMA7Mem SPU2writeDMA7Mem;
_SPU2setDMABaseAddr SPU2setDMABaseAddr; _SPU2setDMABaseAddr SPU2setDMABaseAddr;
_SPU2interruptDMA7 SPU2interruptDMA7; _SPU2interruptDMA7 SPU2interruptDMA7;
_SPU2ReadMemAddr SPU2ReadMemAddr; _SPU2ReadMemAddr SPU2ReadMemAddr;
_SPU2setupRecording SPU2setupRecording;
_SPU2WriteMemAddr SPU2WriteMemAddr; _SPU2WriteMemAddr SPU2WriteMemAddr;
#endif
_SPU2setupRecording SPU2setupRecording;
_SPU2irqCallback SPU2irqCallback; _SPU2irqCallback SPU2irqCallback;
_SPU2setClockPtr SPU2setClockPtr; _SPU2setClockPtr SPU2setClockPtr;
@ -468,6 +474,11 @@ static const LegacyApi_ReqMethod s_MethMessReq_SPU2[] =
{ "SPU2open", (vMeth**)&SPU2open, NULL }, { "SPU2open", (vMeth**)&SPU2open, NULL },
{ "SPU2write", (vMeth**)&SPU2write, NULL }, { "SPU2write", (vMeth**)&SPU2write, NULL },
{ "SPU2read", (vMeth**)&SPU2read, NULL }, { "SPU2read", (vMeth**)&SPU2read, NULL },
#ifdef ENABLE_NEW_IOPDMA_SPU2
{ "SPU2dmaRead", (vMeth**)&SPU2dmaRead, NULL },
{ "SPU2dmaWrite", (vMeth**)&SPU2dmaWrite, NULL },
{ "SPU2dmaInterrupt", (vMeth**)&SPU2dmaInterrupt, NULL },
#else
{ "SPU2readDMA4Mem", (vMeth**)&SPU2readDMA4Mem, NULL }, { "SPU2readDMA4Mem", (vMeth**)&SPU2readDMA4Mem, NULL },
{ "SPU2readDMA7Mem", (vMeth**)&SPU2readDMA7Mem, NULL }, { "SPU2readDMA7Mem", (vMeth**)&SPU2readDMA7Mem, NULL },
{ "SPU2writeDMA4Mem", (vMeth**)&SPU2writeDMA4Mem, NULL }, { "SPU2writeDMA4Mem", (vMeth**)&SPU2writeDMA4Mem, NULL },
@ -475,6 +486,7 @@ static const LegacyApi_ReqMethod s_MethMessReq_SPU2[] =
{ "SPU2interruptDMA4", (vMeth**)&SPU2interruptDMA4,NULL }, { "SPU2interruptDMA4", (vMeth**)&SPU2interruptDMA4,NULL },
{ "SPU2interruptDMA7", (vMeth**)&SPU2interruptDMA7,NULL }, { "SPU2interruptDMA7", (vMeth**)&SPU2interruptDMA7,NULL },
{ "SPU2ReadMemAddr", (vMeth**)&SPU2ReadMemAddr, NULL }, { "SPU2ReadMemAddr", (vMeth**)&SPU2ReadMemAddr, NULL },
#endif
{ "SPU2irqCallback", (vMeth**)&SPU2irqCallback, NULL }, { "SPU2irqCallback", (vMeth**)&SPU2irqCallback, NULL },
{ NULL } { NULL }
@ -484,8 +496,10 @@ static const LegacyApi_OptMethod s_MethMessOpt_SPU2[] =
{ {
{ "SPU2setClockPtr", (vMeth**)&SPU2setClockPtr }, { "SPU2setClockPtr", (vMeth**)&SPU2setClockPtr },
{ "SPU2async", (vMeth**)&SPU2async }, { "SPU2async", (vMeth**)&SPU2async },
#ifndef ENABLE_NEW_IOPDMA_SPU2
{ "SPU2WriteMemAddr", (vMeth**)&SPU2WriteMemAddr }, { "SPU2WriteMemAddr", (vMeth**)&SPU2WriteMemAddr },
{ "SPU2setDMABaseAddr", (vMeth**)&SPU2setDMABaseAddr}, { "SPU2setDMABaseAddr", (vMeth**)&SPU2setDMABaseAddr},
#endif
{ "SPU2setupRecording", (vMeth**)&SPU2setupRecording}, { "SPU2setupRecording", (vMeth**)&SPU2setupRecording},
{ NULL } { NULL }
@ -905,8 +919,12 @@ bool PluginManager::OpenPlugin_SPU2()
{ {
if( SPU2open((void*)&pDsp) ) return false; if( SPU2open((void*)&pDsp) ) return false;
#ifdef ENABLE_NEW_IOPDMA_SPU2
SPU2irqCallback( spu2Irq );
#else
SPU2irqCallback( spu2Irq, spu2DMA4Irq, spu2DMA7Irq ); SPU2irqCallback( spu2Irq, spu2DMA4Irq, spu2DMA7Irq );
if( SPU2setDMABaseAddr != NULL ) SPU2setDMABaseAddr((uptr)psxM); if( SPU2setDMABaseAddr != NULL ) SPU2setDMABaseAddr((uptr)psxM);
#endif
if( SPU2setClockPtr != NULL ) SPU2setClockPtr(&psxRegs.cycle); if( SPU2setClockPtr != NULL ) SPU2setClockPtr(&psxRegs.cycle);
return true; return true;
} }

32
pcsx2/pcsx2hostfs.cpp
View File

@ -16,10 +16,10 @@
#include "PrecompiledHeader.h" #include "PrecompiledHeader.h"
#include "IopCommon.h" #include "IopCommon.h"
#include "Utilities/Console.h" #include "Utilities/Console.h"
#ifndef __LINUX__ #ifndef __LINUX__
#include <io.h> #include <io.h>
#endif #endif
#pragma optimize("", off) #pragma optimize("", off)
@ -45,14 +45,14 @@ u32 paramsAddress;
u32 paramsLength; u32 paramsLength;
u32 returnValue; u32 returnValue;
#define IOP_RDONLY 0x0001 #define IOP_RDONLY 0x0001
#define IOP_WRONLY 0x0002 #define IOP_WRONLY 0x0002
#define IOP_RDWR 0x0003 #define IOP_RDWR 0x0003
#define IOP_NBLOCK 0x0010 #define IOP_NBLOCK 0x0010
#define IOP_APPEND 0x0100 #define IOP_APPEND 0x0100
#define IOP_CREAT 0x0200 #define IOP_CREAT 0x0200
#define IOP_TRUNC 0x0400 #define IOP_TRUNC 0x0400
#define IOP_NOWAIT 0x8000 #define IOP_NOWAIT 0x8000
int pcsx2fio_open_file(char *path, int flags) int pcsx2fio_open_file(char *path, int flags)
{ {
@ -107,11 +107,11 @@ int pcsx2fio_remove(char *name)
} }
int pcsx2fio_mkdir(char *name, int mode) int pcsx2fio_mkdir(char *name, int mode)
{ {
#ifdef __LINUX__ #ifdef __LINUX__
return mkdir(name,mode); return mkdir(name,mode);
#else #else
return mkdir(name); return mkdir(name);
#endif #endif
} }
@ -203,4 +203,4 @@ u32 Pcsx2HostFSread32(u32 addr)
break; break;
} }
return 0; return 0;
} }

8
pcsx2/ps2/Iop/IopHwRead.cpp
View File

@ -277,11 +277,19 @@ static __forceinline T _HwRead_16or32_Page1( u32 addr )
// Soon-to-be outdated SPU2 DMA hack (spu2 manages its own DMA MADR). // Soon-to-be outdated SPU2 DMA hack (spu2 manages its own DMA MADR).
// //
mcase(0x1f8010C0): mcase(0x1f8010C0):
#ifdef ENABLE_NEW_IOPDMA_SPU2
ret = IopChannels[4].MemAddr;
#else
ret = SPU2ReadMemAddr(0); ret = SPU2ReadMemAddr(0);
#endif
break; break;
mcase(0x1f801500): mcase(0x1f801500):
#ifdef ENABLE_NEW_IOPDMA_SPU2
ret = IopChannels[7].MemAddr;
#else
ret = SPU2ReadMemAddr(1); ret = SPU2ReadMemAddr(1);
#endif
break; break;
// ------------------------------------------------------------------------ // ------------------------------------------------------------------------

24
pcsx2/ps2/Iop/IopHwWrite.cpp
View File

@ -321,12 +321,20 @@ static __forceinline void _HwWrite_16or32_Page1( u32 addr, T val )
// as asinine as that may seem). // as asinine as that may seem).
// //
mcase(0x1f8010C0): mcase(0x1f8010C0):
#ifdef ENABLE_NEW_IOPDMA_SPU2
IopChannels[4].MemAddr = val;
#else
SPU2WriteMemAddr( 0, val ); SPU2WriteMemAddr( 0, val );
#endif
HW_DMA4_MADR = val; HW_DMA4_MADR = val;
break; break;
mcase(0x1f801500): mcase(0x1f801500):
#ifdef ENABLE_NEW_IOPDMA_SPU2
IopChannels[7].MemAddr = val;
#else
SPU2WriteMemAddr( 1, val ); SPU2WriteMemAddr( 1, val );
#endif
HW_DMA7_MADR = val; HW_DMA7_MADR = val;
break; break;
@ -352,7 +360,11 @@ static __forceinline void _HwWrite_16or32_Page1( u32 addr, T val )
mcase(0x1f8010c8): // DMA4 CHCR -- SPU2 Core 1 mcase(0x1f8010c8): // DMA4 CHCR -- SPU2 Core 1
psxHu(addr) = val; psxHu(addr) = val;
#ifdef ENABLE_NEW_IOPDMA_SPU2
DmaExecNew(4); DmaExecNew(4);
#else
DmaExec(4);
#endif
break; break;
mcase(0x1f8010e8): // DMA6 CHCR -- OT clear mcase(0x1f8010e8): // DMA6 CHCR -- OT clear
@ -362,7 +374,11 @@ static __forceinline void _HwWrite_16or32_Page1( u32 addr, T val )
mcase(0x1f801508): // DMA7 CHCR -- SPU2 core 2 mcase(0x1f801508): // DMA7 CHCR -- SPU2 core 2
psxHu(addr) = val; psxHu(addr) = val;
#ifdef ENABLE_NEW_IOPDMA_SPU2
DmaExecNew2(7); DmaExecNew2(7);
#else
DmaExec2(7);
#endif
break; break;
mcase(0x1f801518): // DMA8 CHCR -- DEV9 mcase(0x1f801518): // DMA8 CHCR -- DEV9
@ -382,12 +398,20 @@ static __forceinline void _HwWrite_16or32_Page1( u32 addr, T val )
mcase(0x1f801548): // DMA11 CHCR -- SIO2 IN mcase(0x1f801548): // DMA11 CHCR -- SIO2 IN
psxHu(addr) = val; psxHu(addr) = val;
#ifdef ENABLE_NEW_IOPDMA_SIO
DmaExecNew2(11);
#else
DmaExec2(11); DmaExec2(11);
#endif
break; break;
mcase(0x1f801558): // DMA12 CHCR -- SIO2 OUT mcase(0x1f801558): // DMA12 CHCR -- SIO2 OUT
psxHu(addr) = val; psxHu(addr) = val;
#ifdef ENABLE_NEW_IOPDMA_SIO
DmaExecNew2(12);
#else
DmaExec2(12); DmaExec2(12);
#endif
break; break;
// ------------------------------------------------------------------------ // ------------------------------------------------------------------------