mirror of https://github.com/PCSX2/pcsx2.git
major counters changes; i rewrote the vSync/vBlank/hBlank algorithms. they still need some more tweaks though; and i need to check if the other counters are doing their jobs correctly.
also fixed the counters bug introduced in r220. git-svn-id: http://pcsx2-playground.googlecode.com/svn/trunk@228 a6443dda-0b58-4228-96e9-037be469359c
This commit is contained in:
cottonvibes
Gregory Hainaut
parent
ee9dcd4130
commit
55ba76be5d
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@ -145,7 +145,7 @@ extern TESTRUNARGS g_TestRun;
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//#define PS2CLK 36864000 /* 294.912 mhz */
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//#define PSXCLK 9216000 /* 36.864 Mhz */
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//#define PSXCLK 186864000 /* 36.864 Mhz */
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#define PS2CLK 294912000 /* 294.912 mhz */
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#define PS2CLK 294912000 //hz /* 294.912 mhz */
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/* Config.PsxType == 1: PAL:
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185
pcsx2/Counters.c
185
pcsx2/Counters.c
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@ -67,13 +67,14 @@ void rcntSet() {
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}
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//Calculate HBlank
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c = counters[4].CycleT - (cpuRegs.cycle - counters[4].sCycleT);//HBLANKCNT(0.5);
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if (c < nextCounter) nextCounter = c;
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//if(nextCounter > 0x1000) SysPrintf("Nextcounter %x HBlank %x VBlank %x\n", nextCounter, c, counters[5].CycleT - (cpuRegs.cycle - counters[5].sCycleT));
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//Calculate VBlank
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c = counters[5].CycleT - (cpuRegs.cycle - counters[5].sCycleT);//(VBLANKCNT(1) / 2);
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if (c < nextCounter) nextCounter = c;
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if (counters[4].mode & MODE_HBLANK) { //hBlank
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if (Config.PsxType&1) { if (HBLANK_TIME_PAL < nextCounter) nextCounter = HBLANK_TIME_PAL; }
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else if (HBLANK_TIME_NTSC < nextCounter) nextCounter = HBLANK_TIME_NTSC;
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}
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else { //not hBlank (drawing part of the scanline)
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if (Config.PsxType&1) { if (HRENDER_TIME_PAL < nextCounter) nextCounter = HRENDER_TIME_PAL; }
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else if (HRENDER_TIME_NTSC < nextCounter) nextCounter = HRENDER_TIME_NTSC;
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}
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}
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void rcntInit() {
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@ -145,16 +146,16 @@ void UpdateVSyncRate() {
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//else counters[5].rate = (Config.PsxType & 1) ? PS2VBLANK_PAL : PS2VBLANK_NTSC;
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counters[4].mode &= ~0x10000;
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counters[5].mode &= ~0x10000;
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counters[5].mode &= ~0x30000;
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counters[4].count = 1;
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counters[5].count = 1;
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counters[4].Cycle = 227000;
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counters[5].Cycle = 720;
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counters[4].CycleT = HBLANKCNT(1);
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counters[5].CycleT = VBLANKCNT(1);
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//counters[4].count = 1;
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//counters[5].count = 1;
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//counters[4].Cycle = 227000;
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//counters[5].Cycle = 720;
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//counters[4].CycleT = HBLANKCNT(1);
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//counters[5].CycleT = VBLANKCNT(1);
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counters[4].sCycleT = cpuRegs.cycle;
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counters[5].sCycleT = cpuRegs.cycle;
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//counters[5].sCycleT = cpuRegs.cycle;
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if (Config.CustomFps > 0) {
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iTicks = GetTickFrequency() / Config.CustomFps;
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@ -349,22 +350,18 @@ __forceinline void frameLimit()
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}
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}
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void VSyncStart() // VSync Start (240 hsyncs)
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__forceinline void VSyncStart() // VSync Start (240 hsyncs)
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{
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vSyncDebugStuff(); // EE Profiling and Debug code
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if ((CSRw & 0x8)) GSCSRr|= 0x8;
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if (!(GSIMR&0x800)) gsIrq(); //GS Irq
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hwIntcIrq(2); // HW Irq
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psxVSyncStart(); // psxCounters vSync Start
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if (Config.Patch) applypatch(1); // Apply patches (ToDo: clean up patch code)
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if (gates) rcntStartGate(0x8); // Counters Start Gate code
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counters[5].mode ^= 0x10000; // Alternate vSync Start/End
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}
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void VSyncEnd() // VSync End (22 hsyncs)
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__forceinline void VSyncEnd() // VSync End (22 hsyncs)
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{
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iFrame++;
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*(u32*)(PS2MEM_GS+0x1000) ^= 0x2000; // swap the vsync field
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@ -378,16 +375,100 @@ void VSyncEnd() // VSync End (22 hsyncs)
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if( PAD2update != NULL ) PAD2update(1);
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}
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hwIntcIrq(3); // HW Irq
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psxVSyncEnd(); // psxCounters vSync End
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if (gates) rcntEndGate(0x8); // Counters End Gate Code
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SysUpdate(); // check for and handle keyevents
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hwIntcIrq(3); // HW Irq
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frameLimit(); // limit FPS (also handles frameskip and VUskip)
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counters[5].mode ^= 0x10000; // Alternate vSync Start/End
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}
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__forceinline void VBlankStart()
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{
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psxVBlankStart(); // psxCounters vSync Start
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if (gates) rcntStartGate(0x8); // Counters Start Gate code
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}
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__forceinline void VBlankEnd()
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{
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psxVBlankEnd(); // psxCounters vBlank End
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if (gates) rcntEndGate(0x8); // Counters End Gate Code
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SysUpdate(); // check for and handle keyevents
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}
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int hScanline()
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{
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u32 difference = (cpuRegs.cycle - counters[4].sCycleT);
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if (counters[4].mode & MODE_HBLANK) { //HBLANK Start
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if (difference >= HBLANK_TIME_ ) {
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if (difference >= SCANLINE_)
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counters[4].count += (cpuRegs.cycle - counters[4].sCycleT) / SCANLINE_;
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rcntStartGate(0);
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psxCheckStartGate(0);
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counters[4].sCycleT = cpuRegs.cycle;
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counters[4].mode ^= MODE_HBLANK;
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}
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}
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else { //HBLANK END / HRENDER Begin
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if (difference >= (HRENDER_TIME_)) {
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if (difference >= SCANLINE_)
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counters[4].count += difference / SCANLINE_;
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if (CSRw & 0x4) GSCSRr |= 4; // signal
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if (!(GSIMR&0x400)) gsIrq();
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if (gates) rcntEndGate(0);
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if (psxhblankgate) psxCheckEndGate(0);
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counters[4].count++; //increment counter!
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counters[4].sCycleT = cpuRegs.cycle;
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counters[4].mode ^= MODE_HBLANK;
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return 0;
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}
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}
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return 1;
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}
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void vSync()
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{
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if (hScanline()) return; // render the next scanline; if no-change, then exit function
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switch (counters[5].mode & 0x30000) {
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case MODE_VRENDER: //vRender is running
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if (counters[4].count > SCANLINES_VRENDER_) { // Check if should change state to VBlank
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//VRENDER END/VBlank START CODE HERE
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VBlankStart();
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counters[4].count -= SCANLINES_VRENDER_;
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counters[5].mode |= MODE_VBLANK; // Set to VBLANK MODE
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}
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break;
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case MODE_VBLANK: //vBlank is running
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if (counters[5].mode & MODE_VBLANK2) { //Check if should change state to VSYNC
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if (counters[4].count > SCANLINES_VBLANK2_) {
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//VBLANK END/VSYNC START CODE HERE
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VSyncStart();
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VBlankEnd();
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counters[4].count -= SCANLINES_VBLANK2_;
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counters[5].mode &= ~MODE_VBLANK; // Set to VSYNC MODE
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counters[5].mode ^= MODE_VBLANK2;
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}
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}
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else {
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if (counters[4].count > SCANLINES_VBLANK1_) { //Check if should change state to VSYNC
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//VBLANK END/VSYNC START CODE HERE
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VSyncStart();
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VBlankEnd();
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counters[4].count -= SCANLINES_VBLANK1_;
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counters[5].mode &= ~MODE_VBLANK; // Set to VSYNC MODE
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counters[5].mode ^= MODE_VBLANK2;
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}
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}
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break;
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case MODE_VSYNC: //vSync is running
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if (counters[4].count > SCANLINES_VSYNC_) { //Check if should change state to VRENDER
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//VSYNC END/RENDER START CODE HERE
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VSyncEnd();
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counters[4].count -= SCANLINES_VSYNC_;
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counters[5].mode |= MODE_VRENDER; // Set to VRENDER MODE
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}
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break;
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}
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}
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void rcntUpdate()
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{
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@ -405,48 +486,30 @@ void rcntUpdate()
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}
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else counters[i].sCycleT = cpuRegs.cycle;
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}
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if ((cpuRegs.cycle - counters[4].sCycleT) >= (u32)counters[4].CycleT) {
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/*
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if ((cpuRegs.cycle - counters[4].sCycleT) >= HBLANKCNT(0.5)) { //hBlank
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if (counters[4].mode & 0x10000) {
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if (CSRw & 0x4) GSCSRr |= 4; // signal
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if (!(GSIMR&0x400)) gsIrq();
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if (gates) rcntEndGate(0);
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if (psxhblankgate) psxCheckEndGate(0);
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counters[4].CycleT = HBLANKCNT(counters[4].count);
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}
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else {
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if(counters[4].count >= counters[4].Cycle) {
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//SysPrintf("%x of %x hblanks reorder in %x cycles cpuRegs.cycle = %x\n", counters[4].count, counters[4].Cycle, cpuRegs.cycle - counters[4].sCycleT, cpuRegs.cycle);
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counters[4].sCycleT += HBLANKCNT(counters[4].Cycle);
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counters[4].count -= counters[4].Cycle;
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}
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counters[4].count++;
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counters[4].CycleT = HBLANKCNT(counters[4].count) - (HBLANKCNT(0.5));
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rcntStartGate(0);
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psxCheckStartGate(0);
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}
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counters[4].mode ^= 0x10000; // Alternate HBLANK Start/End
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counters[4].sCycleT = cpuRegs.cycle;
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}
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if ((cpuRegs.cycle - counters[5].sCycleT) >= counters[5].CycleT) {
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if (counters[5].mode & 0x10000) {
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counters[5].CycleT = VBLANKCNT(counters[5].count);
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VSyncEnd();
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}
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else {
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if(counters[5].count >= counters[5].Cycle) { // If count >= 720
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counters[5].sCycleT += VBLANKCNT(counters[5].Cycle);
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counters[5].count -= counters[5].Cycle; // Count -= 720
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}
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counters[5].count++; // Count += 1
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counters[5].CycleT = VBLANKCNT(counters[5].count) - (VBLANKCNT(1) / 2);
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VSyncStart();
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}
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if ((cpuRegs.cycle - counters[5].sCycleT) >= (VBLANKCNT(1) / 2)) { //vBlank
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if (counters[5].mode & 0x10000) VSyncEnd();
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else VSyncStart();
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counters[5].sCycleT = cpuRegs.cycle;
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}
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*/
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vSync();
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for (i=0; i<=3; i++) {
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if (!(counters[i].mode & 0x80)) continue; // Stopped
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@ -539,10 +602,10 @@ void rcntWmode(int index, u32 value)
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}
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else gates &= ~(1<<index);
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if ((value & 0x580) == 0x580) { // If we need to compare the target value again, correct the target
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/*if ((value & 0x580) == 0x580) { // If we need to compare the target value again, correct the target
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//SysPrintf("EE Correcting target %x after mode write\n", index);
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counters[index].target &= 0xffff;
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}
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}*/
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rcntSet();
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}
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@ -576,6 +639,7 @@ void rcntStartGate(unsigned int mode) {
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}
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}
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}
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void rcntEndGate(unsigned int mode) {
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int i;
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@ -600,6 +664,7 @@ void rcntEndGate(unsigned int mode) {
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}
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}
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}
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void rcntWtarget(int index, u32 value) {
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EECNT_LOG("EE target write %d target %x value %x\n", index, counters[index].target, value);
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@ -26,6 +26,61 @@ typedef struct {
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u32 CycleT, sCycleT;
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} Counter;
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//------------------------------------------------------------------
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// NTSC Timing Information!!! (some scanline info is guessed)
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//------------------------------------------------------------------
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#define SCANLINE_NTSC 18743 //(PS2CLK / 15734.25)
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#define HRENDER_TIME_NTSC 15528 //time from hblank end to hblank start (PS2CLK / 18991.368423051722991900181367568)
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#define HBLANK_TIME_NTSC 3215 //time from hblank start to hblank end (PS2CLK / 91738.91105912572817760653181028)
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#define VSYNC_NTSC (PS2CLK / 59.94) //hz
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#define SCANLINES_TOTAL_NTSC 525 // total number of scanlines
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#define SCANLINES_VSYNC_NTSC 3 // scanlines that are used for syncing every half-frame
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#define SCANLINES_VRENDER_NTSC 240 // scanlines in a half-frame (because of interlacing)
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#define SCANLINES_VBLANK1_NTSC 19 // scanlines used for vblank1 (even interlace)
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#define SCANLINES_VBLANK2_NTSC 20 // scanlines used for vblank2 (odd interlace)
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//------------------------------------------------------------------
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// PAL Timing Information!!! (some scanline info is guessed)
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//------------------------------------------------------------------
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#define SCANLINE_PAL 18874
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#define HRENDER_TIME_PAL 15335 //time from hblank end to hblank start
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#define HBLANK_TIME_PAL 3539 //time from hblank start to hblank end
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#define VSYNC_PAL (PS2CLK / 50) //hz
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#define SCANLINES_TOTAL_PAL 625 // total number of scanlines
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#define SCANLINES_VSYNC_PAL 5 // scanlines that are used for syncing every half-frame
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#define SCANLINES_VRENDER_PAL 288 // scanlines in a half-frame (because of interlacing)
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#define SCANLINES_VBLANK1_PAL 19 // scanlines used for vblank1 (even interlace)
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#define SCANLINES_VBLANK2_PAL 20 // scanlines used for vblank2 (odd interlace)
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//------------------------------------------------------------------
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// PAL Timing Information!!!
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//------------------------------------------------------------------
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#define SCANLINE_ (u32)((Config.PsxType&1) ? SCANLINE_PAL : SCANLINE_NTSC)
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#define HRENDER_TIME_ (u32)((Config.PsxType&1) ? HRENDER_TIME_PAL : HRENDER_TIME_NTSC)
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#define HBLANK_TIME_ (u32)((Config.PsxType&1) ? HBLANK_TIME_PAL : HBLANK_TIME_NTSC)
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#define VSYNC_ (u32)((Config.PsxType&1) ? VSYNC_PAL : VSYNC_NTSC)
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#define SCANLINES_TOTAL_ (u32)((Config.PsxType&1) ? SCANLINES_TOTAL_PAL : SCANLINES_TOTAL_NTSC)
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#define SCANLINES_VSYNC_ (u32)((Config.PsxType&1) ? SCANLINES_VSYNC_PAL : SCANLINES_VSYNC_NTSC)
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#define SCANLINES_VRENDER_ (u32)((Config.PsxType&1) ? SCANLINES_VRENDER_PAL : SCANLINES_VRENDER_NTSC)
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#define SCANLINES_VBLANK1_ (u32)((Config.PsxType&1) ? SCANLINES_VBLANK1_PAL : SCANLINES_VBLANK1_NTSC)
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#define SCANLINES_VBLANK2_ (u32)((Config.PsxType&1) ? SCANLINES_VBLANK2_PAL : SCANLINES_VBLANK2_NTSC)
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//------------------------------------------------------------------
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// vSync and hBlank Timing Modes
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//------------------------------------------------------------------
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#define MODE_VRENDER 0x10000 //Set during the Render/Frame Scanlines
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#define MODE_VSYNC 0x00000 //Set during the Syncing Scanlines
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#define MODE_VBLANK 0x30000 //Set during the Blanking Scanlines
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#define MODE_VBLANK2 0x40000 //Set during the Blanking Scanlines (half-frame 2)
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//#define MODE_DO_ONCE 0x80000 //Do the code once per change of state
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#define MODE_HRENDER 0x00000 //Set for ~5/6 of 1 Scanline
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#define MODE_HBLANK 0x10000 //Set for the remaining ~1/6 of 1 Scanline
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extern Counter counters[6];
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extern u32 nextCounter, nextsCounter;
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@ -148,18 +148,19 @@ void psxRcntInit() {
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psxRcntSet();
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}
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void psxVSyncStart() {
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void psxVBlankStart() {
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cdvdVsync();
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psxHu32(0x1070)|= 1;
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if(psxvblankgate & 1) psxCheckStartGate(1);
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if(psxvblankgate & (1 << 3)) psxCheckStartGate(3);
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}
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void psxVSyncEnd() {
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void psxVBlankEnd() {
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psxHu32(0x1070)|= 0x800;
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if(psxvblankgate & 1) psxCheckEndGate(1);
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if(psxvblankgate & (1 << 3)) psxCheckEndGate(3);
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}
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void psxCheckEndGate(int counter) { //Check Gate events when Vsync Ends
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int i = counter;
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//SysPrintf("End Gate %x\n", counter);
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@ -48,8 +48,8 @@ u32 psxRcntRcount32(int index);
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u64 psxRcntCycles(int index);
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int psxRcntFreeze(gzFile f, int Mode);
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void psxVSyncStart();
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void psxVSyncEnd();
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void psxVBlankStart();
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void psxVBlankEnd();
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void psxCheckStartGate(int counter);
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void psxCheckEndGate(int counter);
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