mirror of https://github.com/PCSX2/pcsx2.git
aligned_stack: Linux has never worked so well!
* made a workaround for some obscure GCC templating bug * Fixes the assert from PersistentThread when starting the emu git-svn-id: http://pcsx2.googlecode.com/svn/branches/aligned_stack@2047 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
Jake.Stine
parent
00461fdac6
commit
54f8f33257
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@ -1,6 +1,6 @@
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/* PCSX2 - PS2 Emulator for PCs
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* Copyright (C) 2002-2009 PCSX2 Dev Team
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*
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*
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* PCSX2 is free software: you can redistribute it and/or modify it under the terms
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* of the GNU Lesser General Public License as published by the Free Software Found-
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* ation, either version 3 of the License, or (at your option) any later version.
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@ -18,6 +18,15 @@
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// Implementations found here: CALL and JMP! (unconditional only)
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// Note: This header is meant to be included from within the x86Emitter::Internal namespace.
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#ifdef __GNUG__
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// GCC has a bug that causes the templated function handler for Jmp/Call emitters to generate
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// bad asm code. (error is something like "7#*_uber_379s_mangled_$&02_name is already defined!")
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// Using GCC's always_inline attribute fixes it. This differs from __forceinline in that it
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// inlines *even in debug builds* which is (usually) undesirable.
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// ... except when it avoidx compiler bugs.
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# define __always_inline_tmpl_fail __attribute__((always_inline))
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#endif
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// ------------------------------------------------------------------------
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template< bool isJmp >
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class xImpl_JmpCall
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@ -30,11 +39,11 @@ public:
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__forceinline void operator()( const xRegister16& absreg ) const { xOpWrite( 0x66, 0xff, isJmp ? 4 : 2, absreg ); }
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__forceinline void operator()( const ModSibStrict<u16>& src ) const { xOpWrite( 0x66, 0xff, isJmp ? 4 : 2, src ); }
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// Special form for calling functions. This form automatically resolves the
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// correct displacement based on the size of the instruction being generated.
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template< typename T >
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__forceinline void operator()( T* func ) const
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template< typename T > __forceinline __always_inline_tmpl_fail
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void operator()( T* func ) const
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{
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if( isJmp )
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xJccKnownTarget( Jcc_Unconditional, (void*)(uptr)func, false ); // double cast to/from (uptr) needed to appease GCC
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@ -42,7 +51,7 @@ public:
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{
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// calls are relative to the instruction after this one, and length is
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// always 5 bytes (16 bit calls are bad mojo, so no bother to do special logic).
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sptr dest = (sptr)func - ((sptr)xGetPtr() + 5);
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xWrite8( 0xe8 );
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xWrite32( dest );
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@ -389,10 +389,10 @@ void Threading::PersistentThread::OnStartInThread()
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void Threading::PersistentThread::_internal_execute()
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{
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m_lock_InThread.Lock();
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_DoSetThreadName( m_name );
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OnStartInThread();
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_DoSetThreadName( m_name );
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_try_virtual_invoke( &PersistentThread::ExecuteTaskInThread );
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}
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@ -411,7 +411,7 @@ void Threading::PersistentThread::OnCleanupInThread()
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// callback function
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void* Threading::PersistentThread::_internal_callback( void* itsme )
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{
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jASSUME( itsme != NULL );
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pxAssert( itsme != NULL );
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PersistentThread& owner = *((PersistentThread*)itsme);
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pthread_cleanup_push( _pt_callback_cleanup, itsme );
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@ -27,8 +27,6 @@ extern "C"
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void so_resume(void);
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void so_exit(void);
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void recRecompile( u32 startpc );
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// aR3000A.S
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void iopRecRecompile(u32 startpc);
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}
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@ -40,7 +38,6 @@ extern "C"
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// aVUzerorec.S
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void* SuperVUGetProgram(u32 startpc, int vuindex);
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void SuperVUCleanupProgram(u32 startpc, int vuindex);
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void svudispfn();
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// aR3000A.S
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void iopJITCompile();
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@ -313,6 +313,8 @@ u32* recGetImm64(u32 hi, u32 lo)
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// R5900 Dispatchers
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// =====================================================================================================
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static void recRecompile( const u32 startpc );
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static u32 g_lastpc = 0;
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static u32 s_store_ebp, s_store_esp;
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@ -1086,7 +1088,7 @@ static u32 eeScaleBlockCycles()
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static void iBranchTest(u32 newpc)
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{
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_DynGen_StackFrameCheck();
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if( g_ExecBiosHack ) CheckForBIOSEnd();
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// Check the Event scheduler if our "cycle target" has been reached.
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@ -1314,7 +1316,7 @@ void __fastcall dyna_block_discard(u32 start,u32 sz)
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recClear(start, sz);
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// Stack trick: This function was invoked via a direct jmp, so manually pop the
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// EBP/stackframe before issuing a RET, else esp/ebp will be incorrect.
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// EBP/stackframe before issuing a RET, else esp/ebp will be incorrect.
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#ifdef _MSC_VER
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__asm leave __asm jmp [ExitRecompiledCode]
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@ -1338,7 +1340,7 @@ void __fastcall dyna_page_reset(u32 start,u32 sz)
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#endif
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}
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void recRecompile( const u32 startpc )
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static void recRecompile( const u32 startpc )
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{
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u32 i = 0;
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u32 branchTo;
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@ -1,6 +1,6 @@
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/* PCSX2 - PS2 Emulator for PCs
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* Copyright (C) 2002-2009 PCSX2 Dev Team
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*
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*
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* PCSX2 is free software: you can redistribute it and/or modify it under the terms
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* of the GNU Lesser General Public License as published by the Free Software Found-
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* ation, either version 3 of the License, or (at your option) any later version.
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@ -57,7 +57,7 @@ extern void iDumpVU1Registers();
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#define SUPERVU_PROPAGATEFLAGS // the correct behavior of VUs, for some reason superman breaks gfx with it on...
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// use x86reg caching (faster) (not really. rather lots slower :p (rama) )
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// use x86reg caching (faster) (not really. rather lots slower :p (rama) )
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// ... and buggy too since we disabled EBP. Causes GoW2 to hang. Let's get rid of it,
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// sVU is only here to serve as a regression model for Nan/INF behavior anyway. (--air)
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//#define SUPERVU_X86CACHING
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@ -65,7 +65,7 @@ extern void iDumpVU1Registers();
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// registers won't be flushed at block boundaries (faster) (nothing noticable speed-wise, causes SPS in Ratchet and clank (Nneeve) )
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#ifndef PCSX2_DEBUG
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//#define SUPERVU_INTERCACHING
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//#define SUPERVU_INTERCACHING
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#endif
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#define SUPERVU_CHECKCONDITION 0 // has to be 0!!
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@ -75,8 +75,8 @@ extern void iDumpVU1Registers();
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#define _Imm11_ (s32)( (vucode & 0x400) ? (0xfffffc00 | (vucode & 0x3ff)) : (vucode & 0x3ff) )
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#define _UImm11_ (s32)(vucode & 0x7ff)
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#define _Ft_ ((VU->code >> 16) & 0x1F) // The rt part of the instruction register
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#define _Fs_ ((VU->code >> 11) & 0x1F) // The rd part of the instruction register
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#define _Ft_ ((VU->code >> 16) & 0x1F) // The rt part of the instruction register
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#define _Fs_ ((VU->code >> 11) & 0x1F) // The rd part of the instruction register
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#define _Fd_ ((VU->code >> 6) & 0x1F) // The sa part of the instruction register
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#define _It_ (_Ft_ & 15)
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#define _Is_ (_Fs_ & 15)
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@ -351,7 +351,7 @@ void SuperVUAlloc(int vuindex)
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// upper 4 bits must be zero!
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// Changed "first try base" to 0xf1e0000, since 0x0c000000 liked to fail a lot. (cottonvibes)
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s_recVUMem = SysMmapEx(0xf1e0000, VU_EXESIZE, 0x10000000, "SuperVUAlloc");
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if (s_recVUMem == NULL)
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{
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throw Exception::OutOfMemory(
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@ -382,27 +382,27 @@ void SuperVUAlloc(int vuindex)
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void DestroyCachedHeaders(int vuindex, int j)
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{
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list<VuFunctionHeader*>::iterator it = s_plistCachedHeaders[vuindex][j].begin();
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while (it != s_plistCachedHeaders[vuindex][j].end())
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{
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delete *it;
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it++;
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}
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s_plistCachedHeaders[vuindex][j].clear();
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s_plistCachedHeaders[vuindex][j].clear();
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}
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void DestroyVUHeaders(int vuindex)
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{
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list<VuFunctionHeader*>::iterator it = s_listVUHeaders[vuindex].begin();
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while (it != s_listVUHeaders[vuindex].end())
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{
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delete *it;
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it++;
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}
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s_listVUHeaders[vuindex].clear();
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s_listVUHeaders[vuindex].clear();
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}
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// destroy VU resources
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@ -595,7 +595,7 @@ void SuperVUDumpBlock(list<VuBaseBlock*>& blocks, int vuindex)
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{
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eff.Printf( "block:%c %x-%x; children: ", ((*itblock)->type&BLOCKTYPE_HASEOP) ? '*' : ' ',
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(*itblock)->startpc, (*itblock)->endpc - 8);
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for(itchild = (*itblock)->blocks.begin(); itchild != (*itblock)->blocks.end(); itchild++)
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{
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eff.Printf("%x ", (*itchild)->startpc);
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@ -643,9 +643,9 @@ void SuperVUDumpBlock(list<VuBaseBlock*>& blocks, int vuindex)
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eff.Printf( "STR: ");
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for (i = 0; i < iREGCNT_GPR; ++i)
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{
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if (pregs[i].inuse)
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if (pregs[i].inuse)
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eff.Printf( "%.2d ", pregs[i].reg);
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else
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else
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eff.Printf( "-1 ");
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}
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eff.Printf( "\n");
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@ -657,9 +657,9 @@ void SuperVUDumpBlock(list<VuBaseBlock*>& blocks, int vuindex)
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pregs = &s_vecRegArray[(*itblock)->nEndx86];
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for (i = 0; i < iREGCNT_GPR; ++i)
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{
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if (pregs[i].inuse)
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if (pregs[i].inuse)
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eff.Printf( "%.2d ", pregs[i].reg);
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else
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else
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eff.Printf( "-1 ");
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}
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eff.Printf( "\n");
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@ -687,7 +687,7 @@ void SuperVUDumpBlock(list<VuBaseBlock*>& blocks, int vuindex)
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}
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}
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//
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//
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#if 0 // __LINUX__
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// dump the asm
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@ -756,9 +756,9 @@ void* SuperVUGetProgram(u32 startpc, int vuindex)
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assert(s_TotalVUCycles > 0);
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if (vuindex)
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VU1.VI[REG_TPC].UL = startpc;
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else
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else
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VU0.VI[REG_TPC].UL = startpc;
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return (void*)SuperVUEndProgram;
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}
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@ -2156,16 +2156,16 @@ void VuBaseBlock::AssignVFRegs()
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itinst->vfread0[i] = itinst->vfread1[i] = itinst->vfwrite[i] = itinst->vfacc[i] = -1;
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itinst->vfflush[i] = -1;
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if (regs->VFread0)
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if (regs->VFread0)
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itinst->vfread0[i] = _allocVFtoXMMreg(VU, -1, regs->VFread0, 0);
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else if (regs->VIread & (1 << REG_VF0_FLAG))
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else if (regs->VIread & (1 << REG_VF0_FLAG))
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itinst->vfread0[i] = _allocVFtoXMMreg(VU, -1, 0, 0);
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if (regs->VFread1)
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if (regs->VFread1)
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itinst->vfread1[i] = _allocVFtoXMMreg(VU, -1, regs->VFread1, 0);
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else if ((regs->VIread & (1 << REG_VF0_FLAG)) && regs->VFr1xyzw != 0xff)
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else if ((regs->VIread & (1 << REG_VF0_FLAG)) && regs->VFr1xyzw != 0xff)
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itinst->vfread1[i] = _allocVFtoXMMreg(VU, -1, 0, 0);
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if (regs->VIread & (1 << REG_ACC_FLAG)) itinst->vfacc[i] = _allocACCtoXMMreg(VU, -1, 0);
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int reusereg = -1; // 0 - VFwrite, 1 - VFAcc
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@ -2224,15 +2224,15 @@ void VuBaseBlock::AssignVFRegs()
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{
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if (itnext == insts.end() || (itnext->livevars[1]®s->VFread0)) _freeXMMreg(itinst->vfread0[i]);
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xmmregs[itinst->vfread0[i]].inuse = 1;
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xmmregs[itinst->vfread0[i]].reg = reg;
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xmmregs[itinst->vfread0[i]].type = type;
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xmmregs[itinst->vfread0[i]].mode = 0;
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if (reusereg)
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itinst->vfacc[i] = itinst->vfread0[i];
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else
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else
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itinst->vfwrite[i] = itinst->vfread0[i];
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}
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else if (itinst->vfread1[i] >= 0 && lastwrite != itinst->vfread1[i] &&
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@ -2240,21 +2240,21 @@ void VuBaseBlock::AssignVFRegs()
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{
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if (itnext == insts.end() || (itnext->livevars[1]®s->VFread1)) _freeXMMreg(itinst->vfread1[i]);
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xmmregs[itinst->vfread1[i]].inuse = 1;
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xmmregs[itinst->vfread1[i]].reg = reg;
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xmmregs[itinst->vfread1[i]].type = type;
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xmmregs[itinst->vfread1[i]].mode = 0;
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if (reusereg)
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if (reusereg)
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itinst->vfacc[i] = itinst->vfread1[i];
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else
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else
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itinst->vfwrite[i] = itinst->vfread1[i];
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}
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else
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{
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if (reusereg)
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if (reusereg)
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itinst->vfacc[i] = _allocACCtoXMMreg(VU, -1, 0);
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else
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else
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itinst->vfwrite[i] = _allocVFtoXMMreg(VU, -1, regs->VFwrite, 0);
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}
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}
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@ -2276,7 +2276,7 @@ void VuBaseBlock::AssignVFRegs()
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{
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// CLIP inst, need two extra regs
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if (free0 < 0) free0 = _allocTempXMMreg(XMMT_FPS, -1);
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free1 = _allocTempXMMreg(XMMT_FPS, -1);
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free2 = _allocTempXMMreg(XMMT_FPS, -1);
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_freeXMMreg(free1);
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|
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@ -2361,12 +2361,12 @@ void VuBaseBlock::AssignVIRegs(int parent)
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if (parents.size() > 0)
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{
|
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u32 usedvars2 = 0xffffffff;
|
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|
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for(itparent = parents.begin(); itparent != parents.end(); itparent++)
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{
|
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usedvars2 &= (*itparent)->insts.front().usedvars[0];
|
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}
|
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|
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|
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usedvars |= usedvars2;
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}
|
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|
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|
@ -2413,7 +2413,7 @@ void VuBaseBlock::AssignVIRegs(int parent)
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|
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s_markov.children.push_back(this);
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type |= BLOCKTYPE_ANALYZED;
|
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|
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|
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for(itparent = parents.begin(); itparent != parents.end(); itparent++)
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{
|
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(*itparent)->AssignVIRegs(1);
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|
|
@ -2628,17 +2628,11 @@ __declspec(naked) static void SuperVUEndProgram()
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mov esi, s_vu1esi
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mov edi, s_vuedi
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mov ebx, s_vuebx
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}
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|
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#ifdef PCSX2_DEBUG
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__asm
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{
|
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sub s_vu1esp, esp
|
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}
|
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#endif
|
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|
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__asm
|
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{
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call SuperVUCleanupProgram
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jmp s_callstack // so returns correctly
|
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}
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|
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@ -2723,9 +2717,9 @@ static void SuperVURecompile()
|
|||
{
|
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(*itblock)->type &= ~BLOCKTYPE_ANALYZED;
|
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}
|
||||
|
||||
|
||||
s_listBlocks.front()->Recompile();
|
||||
|
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|
||||
// make sure everything compiled
|
||||
for(itblock = s_listBlocks.begin(); itblock != s_listBlocks.end(); itblock++)
|
||||
{
|
||||
|
|
@ -2761,7 +2755,7 @@ static void SuperVURecompile()
|
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JMP32((uptr)SuperVUEndProgram - ((uptr)x86Ptr + 5));
|
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}
|
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// only other case is when there are two branches
|
||||
else
|
||||
else
|
||||
{
|
||||
assert((*itblock)->insts.back().regs[0].pipe == VUPIPE_BRANCH);
|
||||
}
|
||||
|
|
@ -2776,7 +2770,7 @@ static void SuperVURecompile()
|
|||
(*itblock)->pChildJumps[i] = (u32*)((uptr)(*itblock)->pChildJumps[i] & 0x7fffffff);
|
||||
*(*itblock)->pChildJumps[i] = (uptr)(*itchild)->pcode - ((uptr)(*itblock)->pChildJumps[i] + 4);
|
||||
}
|
||||
else
|
||||
else
|
||||
{
|
||||
*(*itblock)->pChildJumps[i] = (uptr)(*itchild)->pcode;
|
||||
}
|
||||
|
|
@ -2860,7 +2854,7 @@ void SuperVUFreeXMMregs(u32* livevars)
|
|||
SSE_MOVHPS_XMM_to_M64(addr, (x86SSERegType)i);
|
||||
SSE_SHUFPS_M128_to_XMM((x86SSERegType)i, addr, 0xc4);
|
||||
}
|
||||
else
|
||||
else
|
||||
{
|
||||
SSE_MOVHPS_M64_to_XMM((x86SSERegType)i, addr + 8);
|
||||
}
|
||||
|
|
@ -2907,7 +2901,7 @@ void VuBaseBlock::Recompile()
|
|||
MOV32ItoM((uptr)&s_vufnheader, s_pFnHeader->startpc);
|
||||
MOV32ItoM((uptr)&VU->VI[REG_TPC], startpc);
|
||||
MOV32ItoM((uptr)&s_svulast, startpc);
|
||||
|
||||
|
||||
list<VuBaseBlock*>::iterator itparent;
|
||||
for (itparent = parents.begin(); itparent != parents.end(); ++itparent)
|
||||
{
|
||||
|
|
@ -3023,9 +3017,9 @@ void VuBaseBlock::Recompile()
|
|||
_freeX86regs();
|
||||
AND32ItoM((uptr)&VU0.VI[ REG_VPU_STAT ].UL, s_vu ? ~0x100 : ~0x001); // E flag
|
||||
AND32ItoM((uptr)&VU->vifRegs->stat, ~VIF1_STAT_VEW);
|
||||
|
||||
|
||||
if (!branch) MOV32ItoM((uptr)&VU->VI[REG_TPC], endpc);
|
||||
|
||||
|
||||
JMP32((uptr)SuperVUEndProgram - ((uptr)x86Ptr + 5));
|
||||
}
|
||||
else
|
||||
|
|
@ -3111,7 +3105,7 @@ void VuBaseBlock::Recompile()
|
|||
else
|
||||
x86regs[i].inuse = 0;
|
||||
}
|
||||
else
|
||||
else
|
||||
#endif
|
||||
{
|
||||
_freeX86reg(i);
|
||||
|
|
@ -3427,7 +3421,7 @@ void VuInstruction::Recompile(list<VuInstruction>::iterator& itinst, u32 vuxyz)
|
|||
// else
|
||||
// MOV32MtoR(EAX, (uptr)&VU->VI[REG_STATUS_FLAG]);
|
||||
// s_StatusRead = tempstatus;
|
||||
|
||||
|
||||
if (s_StatusRead == 0)
|
||||
s_StatusRead = (uptr) & VU->VI[REG_STATUS_FLAG];
|
||||
|
||||
|
|
@ -3787,7 +3781,7 @@ void VuInstruction::Recompile(list<VuInstruction>::iterator& itinst, u32 vuxyz)
|
|||
|
||||
_freeX86reg(x86temp);
|
||||
}
|
||||
|
||||
|
||||
// waitq
|
||||
if (ptr[0] == 0x800003bf) SuperVUFlush(0, 1);
|
||||
// waitp
|
||||
|
|
@ -4368,12 +4362,12 @@ void recVUMI_XGKICK(VURegs *VU, int info)
|
|||
SHL32ItoR(isreg, 4);
|
||||
AND32ItoR(isreg, 0x3fff);
|
||||
s_XGKICKReg = isreg;
|
||||
|
||||
|
||||
if (!SUPERVU_XGKICKDELAY || pc == s_pCurBlock->endpc) {
|
||||
recVUMI_XGKICK_(VU);
|
||||
}
|
||||
else {
|
||||
s_ScheduleXGKICK = (CHECK_XGKICKHACK) ? (min((u32)4, (s_pCurBlock->endpc-pc)/8)) : 2;
|
||||
s_ScheduleXGKICK = (CHECK_XGKICKHACK) ? (min((u32)4, (s_pCurBlock->endpc-pc)/8)) : 2;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue