Reverted r4942 as some games need this to work..

Fixes Metal Saga menus and should fix Fahrenheit, too.

git-svn-id: http://pcsx2.googlecode.com/svn/trunk@4962 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
ramapcsx2 2011-11-07 16:08:30 +00:00
parent 278e4af235
commit 54688f1f98
8 changed files with 73 additions and 3 deletions

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@ -24,7 +24,7 @@
// the lower 16 bit value. IF the change is breaking of all compatibility with old
// states, increment the upper 16 bit value, and clear the lower 16 bits to 0.
static const u32 g_SaveVersion = (0x9A05 << 16) | 0x0000;
static const u32 g_SaveVersion = (0x9A06 << 16) | 0x0000;
// this function is meant to be used in the place of GSfreeze, and provides a safe layer
// between the GS saving function and the MTGS's needs. :)

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@ -47,7 +47,9 @@ void SaveStateBase::vif0Freeze()
FreezeTag("VIF0dma");
Freeze(g_vif0Cycles);
Freeze(g_vu0Cycles);
Freeze(g_packetsizeonvu0);
Freeze(vif0);
Freeze(nVif[0].bSize);
@ -59,6 +61,8 @@ void SaveStateBase::vif1Freeze()
FreezeTag("VIF1dma");
Freeze(g_vif1Cycles);
Freeze(g_vu1Cycles);
Freeze(g_packetsizeonvu1);
Freeze(vif1);

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@ -25,6 +25,21 @@ u32 g_vif0Cycles = 0;
// because its vif stalling not the EE core...
__fi void vif0FLUSH()
{
if(g_packetsizeonvu0 > vif0.vifpacketsize && g_vu0Cycles > 0)
{
//DevCon.Warning("Adding on same packet");
if( ((g_packetsizeonvu0 - vif0.vifpacketsize) >> 1) > g_vu0Cycles)
g_vu0Cycles -= (g_packetsizeonvu0 - vif0.vifpacketsize) >> 1;
else g_vu0Cycles = 0;
}
if(g_vu0Cycles > 0)
{
//DevCon.Warning("Adding %x cycles to VIF0", g_vu0Cycles * BIAS);
g_vif0Cycles += g_vu0Cycles;
g_vu0Cycles = 0;
}
g_vu0Cycles = 0;
if (!(VU0.VI[REG_VPU_STAT].UL & 1)) return;
if(VU0.flags & VUFLAG_MFLAGSET)
{
@ -235,6 +250,7 @@ void dmaVIF0()
vif0ch.tadr, vif0ch.asr0, vif0ch.asr1);
g_vif0Cycles = 0;
g_vu0Cycles = 0;
//if(vif0.irqoffset != 0 && vif0.vifstalled == true) DevCon.Warning("Offset on VIF0 start! offset %x, Progress %x", vif0.irqoffset, vif0.vifstalled);
/*vif0.irqoffset = 0;
vif0.vifstalled = false;

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@ -25,6 +25,21 @@ u32 g_vif1Cycles = 0;
__fi void vif1FLUSH()
{
if(g_packetsizeonvu1 > vif1.vifpacketsize && g_vu1Cycles > 0)
{
//DevCon.Warning("Adding on same packet");
if( ((g_packetsizeonvu1 - vif1.vifpacketsize) >> 1) > g_vu1Cycles)
g_vu1Cycles -= (g_packetsizeonvu1 - vif1.vifpacketsize) >> 1;
else g_vu1Cycles = 0;
}
if(g_vu1Cycles > 0)
{
//DevCon.Warning("Adding %x cycles to VIF1", g_vu1Cycles * BIAS);
g_vif1Cycles += g_vu1Cycles;
g_vu1Cycles = 0;
}
g_vu1Cycles = 0;//else DevCon.Warning("VIF1 Different Packet, how can i work this out :/");
if (VU0.VI[REG_VPU_STAT].UL & 0x100)
{
int _cycles = VU1.cycle;
@ -329,6 +344,7 @@ __fi void vif1Interrupt()
vif1ch.chcr.STR = false;
vif1.vifstalled = false;
g_vif1Cycles = 0;
g_vu1Cycles = 0;
DMA_LOG("VIF1 DMA End");
hwDmacIrq(DMAC_VIF1);
@ -348,6 +364,7 @@ void dmaVIF1()
vif1.vifstalled = false;
vif1.inprogress = 0;*/
g_vif1Cycles = 0;
g_vu1Cycles = 0;
#ifdef PCSX2_DEVBUILD
if (dmacRegs.ctrl.STD == STD_VIF1)

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@ -20,7 +20,10 @@
#include "Vif_Dma.h"
u16 vifqwc = 0;
u32 g_vu0Cycles = 0;
u32 g_vu1Cycles = 0;
u32 g_packetsizeonvu0 = 0;
u32 g_packetsizeonvu1 = 0;
static u32 qwctag(u32 mask)
{

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@ -41,6 +41,7 @@ static __fi void vifFlush(int idx) {
static __fi void vuExecMicro(int idx, u32 addr) {
VIFregisters& vifRegs = vifXRegs;
int startcycles = 0;
//vifFlush(idx);
//if(vifX.vifstalled == true) return;
@ -69,9 +70,17 @@ static __fi void vuExecMicro(int idx, u32 addr) {
}
}
if (!idx) startcycles = VU0.cycle;
else startcycles = VU1.cycle;
if (!idx) vu0ExecMicro(addr);
else vu1ExecMicro(addr);
if (!idx || !THREAD_VU1) {
if (!idx) { g_vu0Cycles += (VU0.cycle-startcycles); g_packetsizeonvu0 = vif0.vifpacketsize; }
else { g_vu1Cycles += (VU1.cycle-startcycles); g_packetsizeonvu1 = vif1.vifpacketsize; }
}
//DevCon.Warning("Ran VU%x, VU0 Cycles %x, VU1 Cycles %x, start %x cycle %x", idx, g_vu0Cycles, g_vu1Cycles, startcycles, VU1.cycle);
GetVifX.vifstalled = true;
}

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@ -119,6 +119,10 @@ static const unsigned int VIF1intc = 5;
extern u32 g_vif0Cycles;
extern u32 g_vif1Cycles;
extern u32 g_vu0Cycles;
extern u32 g_vu1Cycles;
extern u32 g_packetsizeonvu0;
extern u32 g_packetsizeonvu1;
extern void vif0FLUSH();
extern void vif1FLUSH();

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@ -122,6 +122,23 @@ _vifT static __fi bool vifTransfer(u32 *data, int size, bool TTE) {
transferred += size - vifX.vifpacketsize;
if (!idx) {
g_packetsizeonvu0 = size;
g_vif0Cycles +=((transferred * BIAS) >> 2) ; /* guessing */
}
else {
g_packetsizeonvu1 = size;
g_vif1Cycles +=((transferred * BIAS) >> 2) ; /* guessing */
}
if(!idx && g_vu0Cycles > 0) {
if (g_vif0Cycles < g_vu0Cycles) g_vu0Cycles -= g_vif0Cycles;
elif(g_vif0Cycles >= g_vu0Cycles) g_vu0Cycles = 0;
}
if (idx && g_vu1Cycles > 0) {
if (g_vif1Cycles < g_vu1Cycles) g_vu1Cycles -= g_vif1Cycles;
elif(g_vif1Cycles >= g_vu1Cycles) g_vu1Cycles = 0;
}
vifX.irqoffset = transferred % 4; // cannot lose the offset
if (!TTE) {// *WARNING* - Tags CAN have interrupts! so lets just ignore the dma modifying stuffs (GT4)