mirror of https://github.com/PCSX2/pcsx2.git
Another experimental fix for GCC/Linux exception propagation out of the recompiler; using inline asm to invoke a jmp to an external asm function (to set up stackframe pointers), plus disabling EBP in the recompilers (which is just a plain bad idea in any reality or alternate universe).
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@2003 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
Jake.Stine
parent
0a117b1b99
commit
52d34a0616
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@ -1,6 +1,6 @@
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/* PCSX2 - PS2 Emulator for PCs
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* Copyright (C) 2002-2009 PCSX2 Dev Team
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*
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*
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* PCSX2 is free software: you can redistribute it and/or modify it under the terms
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* of the GNU Lesser General Public License as published by the Free Software Found-
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* ation, either version 3 of the License, or (at your option) any later version.
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@ -44,64 +44,64 @@ void _initX86regs() {
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u32 _x86GetAddr(int type, int reg)
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{
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u32 ret = 0;
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switch(type&~X86TYPE_VU1)
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switch(type&~X86TYPE_VU1)
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{
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case X86TYPE_GPR:
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ret = (u32)&cpuRegs.GPR.r[reg];
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case X86TYPE_GPR:
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ret = (u32)&cpuRegs.GPR.r[reg];
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break;
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case X86TYPE_VI:
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case X86TYPE_VI:
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if (type & X86TYPE_VU1)
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ret = (u32)&VU1.VI[reg];
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else
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ret = (u32)&VU0.VI[reg];
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break;
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case X86TYPE_MEMOFFSET:
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case X86TYPE_MEMOFFSET:
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ret = 0;
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break;
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case X86TYPE_VIMEMOFFSET:
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case X86TYPE_VIMEMOFFSET:
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ret = 0;
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break;
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case X86TYPE_VUQREAD:
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if (type & X86TYPE_VU1)
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ret = (u32)&VU1.VI[REG_Q];
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else
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ret = (u32)&VU0.VI[REG_Q];
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break;
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case X86TYPE_VUPREAD:
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case X86TYPE_VUPREAD:
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if (type & X86TYPE_VU1)
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ret = (u32)&VU1.VI[REG_P];
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else
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ret = (u32)&VU0.VI[REG_P];
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break;
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case X86TYPE_VUQWRITE:
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case X86TYPE_VUQWRITE:
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if (type & X86TYPE_VU1)
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ret = (u32)&VU1.q;
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else
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ret = (u32)&VU0.q;
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break;
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case X86TYPE_VUPWRITE:
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case X86TYPE_VUPWRITE:
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if (type & X86TYPE_VU1)
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ret = (u32)&VU1.p;
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else
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ret = (u32)&VU0.p;
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break;
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case X86TYPE_PSX:
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case X86TYPE_PSX:
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ret = (u32)&psxRegs.GPR.r[reg];
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break;
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case X86TYPE_PCWRITEBACK:
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ret = (u32)&g_recWriteback;
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break;
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case X86TYPE_VUJUMP:
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ret = (u32)&g_recWriteback;
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break;
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@ -121,9 +121,9 @@ int _getFreeX86reg(int mode)
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for (int i=0; i<iREGCNT_GPR; i++) {
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int reg = (g_x86checknext+i)%iREGCNT_GPR;
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if( reg == 0 || reg == ESP ) continue;
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if( reg == 0 || reg == ESP || reg == EBP ) continue;
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if( reg >= maxreg ) continue;
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if( (mode&MODE_NOFRAME) && reg==EBP ) continue;
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//if( (mode&MODE_NOFRAME) && reg==EBP ) continue;
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if (x86regs[reg].inuse == 0) {
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g_x86checknext = (reg+1)%iREGCNT_GPR;
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@ -132,8 +132,8 @@ int _getFreeX86reg(int mode)
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}
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for (int i=1; i<maxreg; i++) {
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if( i == ESP ) continue;
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if( (mode&MODE_NOFRAME) && i==EBP ) continue;
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if( i == ESP || i==EBP ) continue;
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//if( (mode&MODE_NOFRAME) && i==EBP ) continue;
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if (x86regs[i].needed) continue;
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if (x86regs[i].type != X86TYPE_TEMP) {
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@ -189,9 +189,9 @@ void _flushConstRegs()
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for (int i = 1, j = 0; i < 32; j++ && ++i, j %= 2) {
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if (!GPR_IS_CONST1(i) || g_cpuFlushedConstReg & (1<<i)) continue;
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if (g_cpuConstRegs[i].SL[j] != 0) continue;
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if (eaxval != 0) XOR32RtoR(EAX, EAX), eaxval = 0;
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MOV32RtoM((uptr)&cpuRegs.GPR.r[i].SL[j], EAX);
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done[j] |= 1<<i;
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zero_cnt++;
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@ -202,10 +202,10 @@ void _flushConstRegs()
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for (int i = 1, j = 0; i < 32; j++ && ++i, j %= 2) {
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if (!GPR_IS_CONST1(i) || g_cpuFlushedConstReg & (1<<i)) continue;
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if (g_cpuConstRegs[i].SL[j] != -1) continue;
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if (eaxval > 0) XOR32RtoR(EAX, EAX), eaxval = 0;
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if (eaxval == 0) NOT32R(EAX), eaxval = -1;
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MOV32RtoM((uptr)&cpuRegs.GPR.r[i].SL[j], EAX);
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done[j + 2] |= 1<<i;
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minusone_cnt++;
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@ -225,7 +225,7 @@ void _flushConstRegs()
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MOV32ItoM((uptr)&cpuRegs.GPR.r[i].UL[0], g_cpuConstRegs[i].UL[0]);
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if (!(done[1] & (1<<i)))
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MOV32ItoM((uptr)&cpuRegs.GPR.r[i].UL[1], g_cpuConstRegs[i].UL[1]);
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g_cpuFlushedConstReg |= 1<<i;
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}
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if (g_cpuHasConstReg == g_cpuFlushedConstReg) break;
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@ -237,10 +237,10 @@ int _allocX86reg(int x86reg, int type, int reg, int mode)
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{
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int i;
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assert( reg >= 0 && reg < 32 );
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// don't alloc EAX and ESP,EBP if MODE_NOFRAME
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int oldmode = mode;
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int noframe = mode & MODE_NOFRAME;
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//int noframe = mode & MODE_NOFRAME;
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int maxreg = (mode & MODE_8BITREG) ? 4 : iREGCNT_GPR;
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mode &= ~(MODE_NOFRAME|MODE_8BITREG);
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int readfromreg = -1;
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@ -248,7 +248,7 @@ int _allocX86reg(int x86reg, int type, int reg, int mode)
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if ( type != X86TYPE_TEMP ) {
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if ( maxreg < iREGCNT_GPR ) {
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// make sure reg isn't in the higher regs
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for(i = maxreg; i < iREGCNT_GPR; ++i) {
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if (!x86regs[i].inuse || x86regs[i].type != type || x86regs[i].reg != reg) continue;
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@ -265,12 +265,12 @@ int _allocX86reg(int x86reg, int type, int reg, int mode)
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}
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for (i=1; i<maxreg; i++) {
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if ( i == ESP ) continue;
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if ( i == ESP || i == EBP ) continue;
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if (!x86regs[i].inuse || x86regs[i].type != type || x86regs[i].reg != reg) continue;
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if( (noframe && i == EBP) || (i >= maxreg) ) {
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if( i >= maxreg ) {
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if (x86regs[i].mode & MODE_READ) readfromreg = i;
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mode |= x86regs[i].mode&MODE_WRITE;
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x86regs[i].inuse = 0;
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break;
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@ -289,10 +289,10 @@ int _allocX86reg(int x86reg, int type, int reg, int mode)
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if( type != X86TYPE_TEMP && !(x86regs[i].mode & MODE_READ) && (mode&MODE_READ)) {
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if( type == X86TYPE_GPR ) _flushConstReg(reg);
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if( X86_ISVI(type) && reg < 16 )
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if( X86_ISVI(type) && reg < 16 )
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MOVZX32M16toR(i, _x86GetAddr(type, reg));
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else
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else
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MOV32MtoR(i, _x86GetAddr(type, reg));
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x86regs[i].mode |= MODE_READ;
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@ -304,9 +304,9 @@ int _allocX86reg(int x86reg, int type, int reg, int mode)
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}
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}
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if (x86reg == -1)
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if (x86reg == -1)
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x86reg = _getFreeX86reg(oldmode);
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else
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else
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_freeX86reg(x86reg);
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x86regs[x86reg].type = type;
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@ -316,7 +316,7 @@ int _allocX86reg(int x86reg, int type, int reg, int mode)
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x86regs[x86reg].inuse = 1;
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if( mode & MODE_READ ) {
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if( readfromreg >= 0 )
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if( readfromreg >= 0 )
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MOV32RtoR(x86reg, readfromreg);
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else {
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if( type == X86TYPE_GPR ) {
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@ -328,18 +328,18 @@ int _allocX86reg(int x86reg, int type, int reg, int mode)
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_flushConstReg(reg);
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_deleteMMXreg(MMX_GPR+reg, 1);
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_deleteGPRtoXMMreg(reg, 1);
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_eeMoveGPRtoR(x86reg, reg);
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_deleteMMXreg(MMX_GPR+reg, 0);
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_deleteGPRtoXMMreg(reg, 0);
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}
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}
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else {
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if( X86_ISVI(type) && reg < 16 ) {
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if( reg == 0 )
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if( reg == 0 )
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XOR32RtoR(x86reg, x86reg);
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else
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else
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MOVZX32M16toR(x86reg, _x86GetAddr(type, reg));
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}
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else MOV32MtoR(x86reg, _x86GetAddr(type, reg));
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@ -358,9 +358,9 @@ int _checkX86reg(int type, int reg, int mode)
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if (x86regs[i].inuse && x86regs[i].reg == reg && x86regs[i].type == type) {
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if( !(x86regs[i].mode & MODE_READ) && (mode&MODE_READ) ) {
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if( X86_ISVI(type) )
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if( X86_ISVI(type) )
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MOVZX32M16toR(i, _x86GetAddr(type, reg));
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else
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else
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MOV32MtoR(i, _x86GetAddr(type, reg));
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}
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@ -408,21 +408,21 @@ void _deleteX86reg(int type, int reg, int flush)
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case 0:
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_freeX86reg(i);
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break;
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case 1:
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if( x86regs[i].mode & MODE_WRITE) {
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if( X86_ISVI(type) && x86regs[i].reg < 16 )
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if( X86_ISVI(type) && x86regs[i].reg < 16 )
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MOV16RtoM(_x86GetAddr(type, x86regs[i].reg), i);
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else
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MOV32RtoM(_x86GetAddr(type, x86regs[i].reg), i);
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// get rid of MODE_WRITE since don't want to flush again
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x86regs[i].mode &= ~MODE_WRITE;
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x86regs[i].mode |= MODE_READ;
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}
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return;
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case 2:
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x86regs[i].inuse = 0;
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break;
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@ -472,7 +472,7 @@ void _initMMXregs()
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__forceinline void* _MMXGetAddr(int reg)
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{
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assert( reg != MMX_TEMP );
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if( reg == MMX_LO ) return &cpuRegs.LO;
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if( reg == MMX_HI ) return &cpuRegs.HI;
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if( reg == MMX_FPUACC ) return &fpuRegs.ACC;
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@ -480,7 +480,7 @@ __forceinline void* _MMXGetAddr(int reg)
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if( reg >= MMX_GPR && reg < MMX_GPR+32 ) return &cpuRegs.GPR.r[reg&31];
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if( reg >= MMX_FPU && reg < MMX_FPU+32 ) return &fpuRegs.fpr[reg&31];
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if( reg >= MMX_COP0 && reg < MMX_COP0+32 ) return &cpuRegs.CP0.r[reg&31];
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assert( 0 );
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return NULL;
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}
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@ -589,7 +589,7 @@ int _allocMMXreg(int mmxreg, int reg, int mode)
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}
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if (mmxreg == -1) mmxreg = _getFreeMMXreg();
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mmxregs[mmxreg].inuse = 1;
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mmxregs[mmxreg].reg = reg;
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mmxregs[mmxreg].mode = mode&~MODE_READHALF;
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@ -697,7 +697,7 @@ void _deleteMMXreg(int reg, int flush)
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if (mmxregs[i].inuse && mmxregs[i].reg == reg ) {
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switch(flush) {
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switch(flush) {
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case 0: // frees all of the reg
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_freeMMXreg(i);
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break;
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@ -769,14 +769,14 @@ void _freeMMXreg(int mmxreg)
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{
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assert( mmxreg < iREGCNT_MMX );
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if (!mmxregs[mmxreg].inuse) return;
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if (mmxregs[mmxreg].mode & MODE_WRITE ) {
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// Not sure if this line is accurate, since if the 32 was 34, it would be MMX_ISGPR.
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if ( /*mmxregs[mmxreg].reg >= MMX_GPR &&*/ mmxregs[mmxreg].reg < MMX_GPR+32 ) // Checking if a u32 is >=0 is pointless.
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assert( !(g_cpuHasConstReg & (1<<(mmxregs[mmxreg].reg-MMX_GPR))) );
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assert( mmxregs[mmxreg].reg != MMX_GPR );
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if( MMX_IS32BITS(mmxregs[mmxreg].reg) )
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MOVDMMXtoM((u32)_MMXGetAddr(mmxregs[mmxreg].reg), mmxreg);
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else
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@ -854,11 +854,11 @@ void SetFPUstate() {
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_freeMMXreg(7);
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if (x86FpuState == MMX_STATE) {
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if (x86caps.has3DNOWInstructionExtensions)
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if (x86caps.has3DNOWInstructionExtensions)
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FEMMS();
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else
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EMMS();
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x86FpuState = FPU_STATE;
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}
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}
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@ -956,13 +956,13 @@ void _signExtendSFtoM(u32 mem)
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int _signExtendMtoMMX(x86MMXRegType to, u32 mem)
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{
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int t0reg = _allocMMXreg(-1, MMX_TEMP, 0);
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MOVDMtoMMX(t0reg, mem);
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MOVQRtoR(to, t0reg);
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PSRADItoR(t0reg, 31);
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PUNPCKLDQRtoR(to, t0reg);
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_freeMMXreg(t0reg);
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return to;
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}
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@ -987,7 +987,7 @@ int _signExtendGPRMMXtoMMX(x86MMXRegType to, u32 gprreg, x86MMXRegType from, u32
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SetMMXstate();
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if( g_pCurInstInfo->regs[gprreg] & EEINST_MMX ) {
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if( EEINST_ISLIVE64(gprfromreg) ) {
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_freeMMXreg(from);
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}
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@ -1061,7 +1061,7 @@ int _signExtendGPRtoMMX(x86MMXRegType to, u32 gprreg, int shift)
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int _allocCheckGPRtoMMX(EEINST* pinst, int reg, int mode)
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{
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if( pinst->regs[reg] & EEINST_MMX ) return _allocMMXreg(-1, MMX_GPR+reg, mode);
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return _checkMMXreg(MMX_GPR+reg, mode);
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}
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@ -562,6 +562,17 @@ static void __naked DispatcherEvent()
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}
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#endif
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static void DispatcherRegC()
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{
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#ifdef _MSC_VER
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__asm jmp DispatcherReg;
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#else
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__asm__ __volatile__(
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"jmp DispatcherReg\n"
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);
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#endif
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}
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static void recExecute()
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{
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// Implementation Notes:
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@ -600,7 +611,7 @@ static void recExecute()
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}
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#else // _MSC_VER
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DispatcherReg();
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DispatcherRegC();
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#endif
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}
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catch( Exception::ForceDispatcherReg& )
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