mirror of https://github.com/PCSX2/pcsx2.git
iop: remove unused iPsxMem.cpp file
This commit is contained in:
Gregory Hainaut
parent
afdf5cdfe2
commit
52b4604d3b
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@ -501,7 +501,6 @@ set(pcsx2x86Sources
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x86/iFPUd.cpp
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x86/iMisc.cpp
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x86/iMMI.cpp
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x86/iPsxMem.cpp
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x86/iR3000A.cpp
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x86/iR3000Atables.cpp
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x86/iR5900Misc.cpp
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@ -1,869 +0,0 @@
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/* PCSX2 - PS2 Emulator for PCs
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* Copyright (C) 2002-2009 PCSX2 Dev Team
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*
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* PCSX2 is free software: you can redistribute it and/or modify it under the terms
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* of the GNU Lesser General Public License as published by the Free Software Found-
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* ation, either version 3 of the License, or (at your option) any later version.
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*
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* PCSX2 is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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* PURPOSE. See the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along with PCSX2.
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* If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "PrecompiledHeader.h"
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#include "IopCommon.h"
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#include "iR3000A.h"
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#include "VU.h"
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extern int g_psxWriteOk;
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extern u32 g_psxMaxRecMem;
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static u32 writectrl;
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#ifdef PCSX2_VIRTUAL_MEM
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#ifdef _DEBUG
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#define ASSERT_WRITEOK \
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{ \
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__asm cmp g_psxWriteOk, 1 \
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__asm je WriteOk \
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__asm int 10 \
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} \
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WriteOk: \
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#else
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#define ASSERT_WRITEOK
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#endif
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__declspec(naked) void psxRecMemRead8()
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{
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__asm {
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mov edx, ecx
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shr edx, 16
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cmp dx, 0x1f80
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je hwread
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cmp dx, 0x1f40
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je hw4read
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cmp dx, 0x1000
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je devread
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cmp dx, 0x1f00
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je spuread
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}
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ASSERT_WRITEOK
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__asm {
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memread:
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// rom reads, has to be PS2MEM_BASE_
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mov eax, dword ptr [ecx+PS2MEM_BASE_]
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ret
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hwread:
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cmp cx, 0x1000
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jb memread
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push ecx
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call psxHwRead8
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add esp, 4
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ret
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hw4read:
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push ecx
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call psxHw4Read8
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add esp, 4
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ret
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devread:
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push ecx
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call DEV9read8
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// stack already incremented
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ret
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spuread:
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push ecx
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call SPU2read
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// stack already incremented
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ret
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}
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}
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int psxRecMemConstRead8(u32 x86reg, u32 mem, u32 sign)
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{
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u32 t = (mem >> 16) & 0x1fff;
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switch(t) {
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case 0x1f80:
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return psxHwConstRead8(x86reg, mem&0x1fffffff, sign);
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#ifdef _DEBUG
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case 0x1d00: assert(0);
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#endif
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case 0x1f40:
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return psxHw4ConstRead8(x86reg, mem&0x1fffffff, sign);
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case 0x1000:
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xPUSH(mem&0x1fffffff);
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xCALL((void*)(uptr)DEV9read8);
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if( sign ) xMOVSX(xRegister32(x86reg), al);
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else xMOVZX(xRegister32(x86reg), al);
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return 0;
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default:
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_eeReadConstMem8(x86reg, (u32)PSXM(mem), sign);
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return 0;
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}
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}
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__declspec(naked) void psxRecMemRead16()
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{
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__asm {
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mov edx, ecx
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shr edx, 16
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cmp dx, 0x1f80
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je hwread
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cmp dx, 0x1f90
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je spuread
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cmp dx, 0x1d00
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je sifread
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cmp dx, 0x1000
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je devread
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}
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ASSERT_WRITEOK
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__asm {
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memread:
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// rom reads, has to be PS2MEM_BASE_
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mov eax, dword ptr [ecx+PS2MEM_BASE_]
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ret
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hwread:
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cmp cx, 0x1000
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jb memread
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push ecx
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call psxHwRead16
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add esp, 4
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ret
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sifread:
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mov edx, ecx
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and edx, 0xf0
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cmp dl, 0x60
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je Sif60
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mov eax, dword ptr [edx+PS2MEM_BASE_+0x1000f200]
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cmp dl, 0x40
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jne End
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// 0x40
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or eax, 2
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jmp End
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Sif60:
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xor eax, eax
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jmp End
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spuread:
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push ecx
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call SPU2read
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// stack already incremented
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End:
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ret
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devread:
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push ecx
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call DEV9read16
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// stack already incremented
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ret
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}
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}
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int psxRecMemConstRead16(u32 x86reg, u32 mem, u32 sign)
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{
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u32 t = (mem >> 16) & 0x1fff;
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switch(t) {
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case 0x1f80: return psxHwConstRead16(x86reg, mem&0x1fffffff, sign);
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case 0x1d00:
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switch(mem & 0xF0)
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{
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case 0x40:
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_eeReadConstMem16(x86reg, (u32)PS2MEM_HW+0xF240, sign);
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xOR(xRegister32(x86reg), 0x0002);
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break;
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case 0x60:
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xXOR(xRegister32(x86reg), xRegister32(x86reg));
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break;
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default:
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_eeReadConstMem16(x86reg, (u32)PS2MEM_HW+0xf200+(mem&0xf0), sign);
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break;
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}
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return 0;
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case 0x1f90:
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xPUSH(mem&0x1fffffff);
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xCALL((void*)(uptr)SPU2read);
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if( sign ) xMOVSX(xRegister32(x86reg), ax);
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else xMOVZX(xRegister32(x86reg), ax);
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return 0;
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case 0x1000:
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xPUSH(mem&0x1fffffff);
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xCALL((void*)(uptr)DEV9read16);
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if( sign ) xMOVSX(xRegister32(x86reg), ax);
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else xMOVZX(xRegister32(x86reg), ax);
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return 0;
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default:
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assert( g_psxWriteOk );
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_eeReadConstMem16(x86reg, (u32)PSXM(mem), sign);
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return 0;
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}
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return 0;
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}
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__declspec(naked) void psxRecMemRead32()
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{
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__asm {
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mov edx, ecx
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shr edx, 16
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cmp dx, 0x1f80
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je hwread
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cmp dx, 0x1d00
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je sifread
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cmp dx, 0x1000
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je devread
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cmp ecx, 0x1ffe0130
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je WriteCtrlRead
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}
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ASSERT_WRITEOK
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__asm {
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memread:
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// rom reads, has to be PS2MEM_BASE_
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mov eax, dword ptr [ecx+PS2MEM_BASE_]
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ret
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hwread:
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cmp cx, 0x1000
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jb memread
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push ecx
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call psxHwRead32
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add esp, 4
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ret
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sifread:
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mov edx, ecx
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and edx, 0xf0
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cmp dl, 0x60
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je Sif60
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// do the read from ps2 mem
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mov eax, dword ptr [edx+PS2MEM_BASE_+0x1000f200]
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cmp dl, 0x40
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jne End
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// 0x40
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or eax, 0xf0000002
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jmp End
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Sif60:
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xor eax, eax
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End:
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ret
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devread:
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push ecx
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call DEV9read32
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// stack already incremented
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ret
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WriteCtrlRead:
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mov eax, writectrl
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ret
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}
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}
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int psxRecMemConstRead32(u32 x86reg, u32 mem)
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{
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u32 t = (mem >> 16) & 0x1fff;
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switch(t) {
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case 0x1f80: return psxHwConstRead32(x86reg, mem&0x1fffffff);
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case 0x1d00:
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switch(mem & 0xF0)
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{
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case 0x40:
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_eeReadConstMem32(x86reg, (u32)PS2MEM_HW+0xF240);
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xOR(xRegister32(x86reg), 0xf0000002);
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break;
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case 0x60:
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xXOR(xRegister32(x86reg), xRegister32(x86reg));
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break;
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default:
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_eeReadConstMem32(x86reg, (u32)PS2MEM_HW+0xf200+(mem&0xf0));
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break;
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}
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return 0;
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case 0x1000:
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xPUSH(mem&0x1fffffff);
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xCALL((void*)(uptr)DEV9read32);
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return 1;
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default:
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if( mem == 0xfffe0130 )
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xMOV(xRegister32(x86reg), ptr[&writectrl]);
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else {
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xXOR(xRegister32(x86reg), xRegister32(x86reg));
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xCMP(ptr32[&g_psxWriteOk], 0);
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CMOVNE32MtoR(x86reg, (u32)PSXM(mem));
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}
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return 0;
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}
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}
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__declspec(naked) void psxRecMemWrite8()
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{
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__asm {
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mov edx, ecx
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shr edx, 16
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cmp dx, 0x1f80
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je hwwrite
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cmp dx, 0x1f40
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je hw4write
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cmp dx, 0x1000
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je devwrite
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}
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ASSERT_WRITEOK
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__asm {
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memwrite:
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// rom writes, has to be PS2MEM_BASE_
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mov byte ptr [ecx+PS2MEM_BASE_], al
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ret
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hwwrite:
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cmp cx, 0x1000
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jb memwrite
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push eax
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push ecx
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call psxHwWrite8
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add esp, 8
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ret
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hw4write:
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push eax
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push ecx
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call psxHw4Write8
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add esp, 8
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ret
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devwrite:
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push eax
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push ecx
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call DEV9write8
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// stack alwritey incremented
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ret
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}
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}
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int psxRecMemConstWrite8(u32 mem, int mmreg)
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{
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u32 t = (mem >> 16) & 0x1fff;
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switch(t) {
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case 0x1f80:
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psxHwConstWrite8(mem&0x1fffffff, mmreg);
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return 0;
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case 0x1f40:
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psxHw4ConstWrite8(mem&0x1fffffff, mmreg);
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return 0;
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case 0x1d00:
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assert(0);
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_eeWriteConstMem8((u32)(PS2MEM_HW+0xf200+(mem&0xff)), mmreg);
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return 0;
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case 0x1000:
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_recPushReg(mmreg);
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xPUSH(mem&0x1fffffff);
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xCALL((void*)(uptr)DEV9write8);
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return 0;
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default:
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_eeWriteConstMem8((u32)PSXM(mem), mmreg);
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return 1;
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}
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}
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__declspec(naked) void psxRecMemWrite16()
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{
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__asm {
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mov edx, ecx
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shr edx, 16
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cmp dx, 0x1f80
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je hwwrite
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cmp dx, 0x1f90
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je spuwrite
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cmp dx, 0x1d00
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je sifwrite
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cmp dx, 0x1000
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je devwrite
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cmp dx, 0x1600
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je ignorewrite
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}
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ASSERT_WRITEOK
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__asm {
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memwrite:
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// rom writes, has to be PS2MEM_BASE_
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mov word ptr [ecx+PS2MEM_BASE_], ax
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ret
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hwwrite:
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cmp cx, 0x1000
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jb memwrite
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push eax
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push ecx
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call psxHwWrite16
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add esp, 8
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ret
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sifwrite:
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mov edx, ecx
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and edx, 0xf0
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cmp dl, 0x60
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je Sif60
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cmp dl, 0x40
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je Sif40
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mov word ptr [edx+PS2MEM_BASE_+0x1000f200], ax
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ret
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Sif40:
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mov bx, word ptr [edx+PS2MEM_BASE_+0x1000f200]
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test ax, 0xa0
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jz Sif40_2
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// psHu16(0x1000F240) &= ~0xF000;
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// psHu16(0x1000F240) |= 0x2000;
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and bx, 0x0fff
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or bx, 0x2000
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Sif40_2:
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// if(psHu16(0x1000F240) & temp) psHu16(0x1000F240) &= ~temp;
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// else psHu16(0x1000F240) |= temp;
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and ax, 0xf0
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test bx, ax
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jz Sif40_3
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not ax
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and bx, ax
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jmp Sif40_4
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Sif40_3:
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or bx, ax
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Sif40_4:
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mov word ptr [edx+PS2MEM_BASE_+0x1000f200], bx
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ret
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Sif60:
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mov word ptr [edx+PS2MEM_BASE_+0x1000f200], 0
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ret
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spuwrite:
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push eax
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push ecx
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call SPU2write
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// stack alwritey incremented
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ret
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devwrite:
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push eax
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push ecx
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call DEV9write16
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// stack alwritey incremented
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ret
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ignorewrite:
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ret
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}
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}
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int psxRecMemConstWrite16(u32 mem, int mmreg)
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{
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u32 t = (mem >> 16) & 0x1fff;
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switch(t) {
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case 0x1600:
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//HACK: DEV9 VM crash fix
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return 0;
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case 0x1f80:
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psxHwConstWrite16(mem&0x1fffffff, mmreg);
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return 0;
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case 0x1d00:
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switch (mem & 0xf0) {
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case 0x10:
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// write to ps2 mem
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_eeWriteConstMem16((u32)(PS2MEM_HW+0xf210), mmreg);
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return 0;
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case 0x40:
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{
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// delete x86reg
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_eeMoveMMREGtoR(EAX, mmreg);
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assert( mmreg != EBX );
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xMOV(bx, ptr[(void*)((u32)PS2MEM_HW+0xf240)]);
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xTEST(ax, 0xa0);
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j8Ptr[0] = JZ8(0);
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xAND(bx, 0x0fff);
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xOR(bx, 0x2000);
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x86SetJ8(j8Ptr[0]);
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xAND(ax, 0xf0);
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xTEST(ax, xRegister16(0xf0));
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j8Ptr[0] = JZ8(0);
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xNOT(eax);
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xAND(bx, ax);
|
||||
j8Ptr[1] = JMP8(0);
|
||||
|
||||
x86SetJ8(j8Ptr[0]);
|
||||
xOR(bx, ax);
|
||||
|
||||
x86SetJ8(j8Ptr[1]);
|
||||
|
||||
xMOV(ptr[(void*)((u32)PS2MEM_HW+0xf240)], bx);
|
||||
|
||||
return 0;
|
||||
}
|
||||
case 0x60:
|
||||
xMOV(ptr32[(u32*)((u32)(PS2MEM_HW+0xf260))], 0);
|
||||
return 0;
|
||||
default:
|
||||
assert(0);
|
||||
}
|
||||
return 0;
|
||||
|
||||
case 0x1f90:
|
||||
_recPushReg(mmreg);
|
||||
xPUSH(mem&0x1fffffff);
|
||||
xCALL((void*)(uptr)SPU2write);
|
||||
return 0;
|
||||
|
||||
case 0x1000:
|
||||
_recPushReg(mmreg);
|
||||
xPUSH(mem&0x1fffffff);
|
||||
xCALL((void*)(uptr)DEV9write16);
|
||||
return 0;
|
||||
|
||||
default:
|
||||
_eeWriteConstMem16((u32)PSXM(mem), mmreg);
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
||||
__declspec(naked) void psxRecMemWrite32()
|
||||
{
|
||||
__asm {
|
||||
mov edx, ecx
|
||||
shr edx, 16
|
||||
cmp dx, 0x1f80
|
||||
je hwwrite
|
||||
cmp dx, 0x1d00
|
||||
je sifwrite
|
||||
cmp dx, 0x1000
|
||||
je devwrite
|
||||
cmp dx, 0x1ffe
|
||||
je WriteCtrl
|
||||
}
|
||||
|
||||
__asm {
|
||||
// rom writes, has to be PS2MEM_BASE_
|
||||
test g_psxWriteOk, 1
|
||||
jz endwrite
|
||||
|
||||
memwrite:
|
||||
mov dword ptr [ecx+PS2MEM_BASE_], eax
|
||||
endwrite:
|
||||
ret
|
||||
|
||||
hwwrite:
|
||||
cmp cx, 0x1000
|
||||
jb memwrite
|
||||
|
||||
push eax
|
||||
push ecx
|
||||
call psxHwWrite32
|
||||
add esp, 8
|
||||
ret
|
||||
|
||||
sifwrite:
|
||||
mov edx, ecx
|
||||
and edx, 0xf0
|
||||
cmp dl, 0x60
|
||||
je Sif60
|
||||
cmp dl, 0x40
|
||||
je Sif40
|
||||
cmp dl, 0x30
|
||||
je Sif30
|
||||
cmp dl, 0x20
|
||||
je Sif20
|
||||
|
||||
mov dword ptr [edx+PS2MEM_BASE_+0x1000f200], eax
|
||||
ret
|
||||
|
||||
Sif40:
|
||||
mov bx, word ptr [edx+PS2MEM_BASE_+0x1000f200]
|
||||
test ax, 0xa0
|
||||
jz Sif40_2
|
||||
// psHu16(0x1000F240) &= ~0xF000;
|
||||
// psHu16(0x1000F240) |= 0x2000;
|
||||
and bx, 0x0fff
|
||||
or bx, 0x2000
|
||||
|
||||
Sif40_2:
|
||||
// if(psHu16(0x1000F240) & temp) psHu16(0x1000F240) &= ~temp;
|
||||
// else psHu16(0x1000F240) |= temp;
|
||||
and ax, 0xf0
|
||||
test bx, ax
|
||||
jz Sif40_3
|
||||
|
||||
not ax
|
||||
and bx, ax
|
||||
jmp Sif40_4
|
||||
Sif40_3:
|
||||
or bx, ax
|
||||
Sif40_4:
|
||||
mov word ptr [edx+PS2MEM_BASE_+0x1000f200], bx
|
||||
ret
|
||||
|
||||
Sif30:
|
||||
or dword ptr [edx+PS2MEM_BASE_+0x1000f200], eax
|
||||
ret
|
||||
Sif20:
|
||||
not eax
|
||||
and dword ptr [edx+PS2MEM_BASE_+0x1000f200], eax
|
||||
ret
|
||||
Sif60:
|
||||
mov dword ptr [edx+PS2MEM_BASE_+0x1000f200], 0
|
||||
ret
|
||||
|
||||
devwrite:
|
||||
push eax
|
||||
push ecx
|
||||
call DEV9write32
|
||||
// stack alwritey incremented
|
||||
ret
|
||||
|
||||
WriteCtrl:
|
||||
cmp ecx, 0x1ffe0130
|
||||
jne End
|
||||
|
||||
mov writectrl, eax
|
||||
|
||||
cmp eax, 0x800
|
||||
je SetWriteNotOk
|
||||
cmp eax, 0x804
|
||||
je SetWriteNotOk
|
||||
cmp eax, 0xc00
|
||||
je SetWriteNotOk
|
||||
cmp eax, 0xc04
|
||||
je SetWriteNotOk
|
||||
cmp eax, 0xcc0
|
||||
je SetWriteNotOk
|
||||
cmp eax, 0xcc4
|
||||
je SetWriteNotOk
|
||||
cmp eax, 0x0c4
|
||||
je SetWriteNotOk
|
||||
|
||||
// test ok
|
||||
cmp eax, 0x1e988
|
||||
je SetWriteOk
|
||||
cmp eax, 0x1edd8
|
||||
je SetWriteOk
|
||||
|
||||
End:
|
||||
ret
|
||||
|
||||
SetWriteNotOk:
|
||||
mov g_psxWriteOk, 0
|
||||
ret
|
||||
SetWriteOk:
|
||||
mov g_psxWriteOk, 1
|
||||
ret
|
||||
}
|
||||
}
|
||||
|
||||
int psxRecMemConstWrite32(u32 mem, int mmreg)
|
||||
{
|
||||
u32 t = (mem >> 16) & 0x1fff;
|
||||
switch(t) {
|
||||
case 0x1f80:
|
||||
psxHwConstWrite32(mem&0x1fffffff, mmreg);
|
||||
return 0;
|
||||
|
||||
case 0x1d00:
|
||||
switch (mem & 0xf0) {
|
||||
case 0x10:
|
||||
// write to ps2 mem
|
||||
_eeWriteConstMem32((u32)PS2MEM_HW+0xf210, mmreg);
|
||||
return 0;
|
||||
case 0x20:
|
||||
// write to ps2 mem
|
||||
// delete x86reg
|
||||
if( IS_PSXCONSTREG(mmreg) ) {
|
||||
xAND(ptr32[(u32*)((u32)PS2MEM_HW+0xf220)], ~g_psxConstRegs[(mmreg>>16)&0x1f]);
|
||||
}
|
||||
else {
|
||||
xNOT(xRegister32(mmreg));
|
||||
xAND(ptr[(void*)((u32)PS2MEM_HW+0xf220)], xRegister32(mmreg));
|
||||
}
|
||||
return 0;
|
||||
case 0x30:
|
||||
// write to ps2 mem
|
||||
_eeWriteConstMem32OP((u32)PS2MEM_HW+0xf230, mmreg, 1);
|
||||
return 0;
|
||||
case 0x40:
|
||||
{
|
||||
// delete x86reg
|
||||
assert( mmreg != EBX );
|
||||
|
||||
_eeMoveMMREGtoR(EAX, mmreg);
|
||||
|
||||
xMOV(bx, ptr[(void*)((u32)PS2MEM_HW+0xf240)]);
|
||||
xTEST(ax, 0xa0);
|
||||
j8Ptr[0] = JZ8(0);
|
||||
|
||||
xAND(bx, 0x0fff);
|
||||
xOR(bx, 0x2000);
|
||||
|
||||
x86SetJ8(j8Ptr[0]);
|
||||
|
||||
xAND(ax, 0xf0);
|
||||
xTEST(ax, xRegister16(0xf0));
|
||||
j8Ptr[0] = JZ8(0);
|
||||
|
||||
xNOT(eax);
|
||||
xAND(bx, ax);
|
||||
j8Ptr[1] = JMP8(0);
|
||||
|
||||
x86SetJ8(j8Ptr[0]);
|
||||
xOR(bx, ax);
|
||||
|
||||
x86SetJ8(j8Ptr[1]);
|
||||
|
||||
xMOV(ptr[(void*)((u32)PS2MEM_HW+0xf240)], bx);
|
||||
|
||||
return 0;
|
||||
}
|
||||
case 0x60:
|
||||
xMOV(ptr32[(u32*)((u32)(PS2MEM_HW+0xf260))], 0);
|
||||
return 0;
|
||||
default:
|
||||
assert(0);
|
||||
}
|
||||
return 0;
|
||||
|
||||
case 0x1000:
|
||||
_recPushReg(mmreg);
|
||||
xPUSH(mem&0x1fffffff);
|
||||
xCALL((void*)(uptr)DEV9write32);
|
||||
return 0;
|
||||
|
||||
case 0x1ffe:
|
||||
if( mem == 0xfffe0130 ) {
|
||||
u8* ptrs[9];
|
||||
|
||||
_eeWriteConstMem32((uptr)&writectrl, mmreg);
|
||||
|
||||
if( IS_PSXCONSTREG(mmreg) ) {
|
||||
switch (g_psxConstRegs[(mmreg>>16)&0x1f]) {
|
||||
case 0x800: case 0x804:
|
||||
case 0xc00: case 0xc04:
|
||||
case 0xcc0: case 0xcc4:
|
||||
case 0x0c4:
|
||||
xMOV(ptr32[&g_psxWriteOk], 0);
|
||||
break;
|
||||
case 0x1e988:
|
||||
case 0x1edd8:
|
||||
xMOV(ptr32[&g_psxWriteOk], 1);
|
||||
break;
|
||||
default:
|
||||
assert(0);
|
||||
}
|
||||
}
|
||||
else {
|
||||
// not ok
|
||||
xCMP(xRegister32(mmreg), 0x800);
|
||||
ptrs[0] = JE8(0);
|
||||
xCMP(xRegister32(mmreg), 0x804);
|
||||
ptrs[1] = JE8(0);
|
||||
xCMP(xRegister32(mmreg), 0xc00);
|
||||
ptrs[2] = JE8(0);
|
||||
xCMP(xRegister32(mmreg), 0xc04);
|
||||
ptrs[3] = JE8(0);
|
||||
xCMP(xRegister32(mmreg), 0xcc0);
|
||||
ptrs[4] = JE8(0);
|
||||
xCMP(xRegister32(mmreg), 0xcc4);
|
||||
ptrs[5] = JE8(0);
|
||||
xCMP(xRegister32(mmreg), 0x0c4);
|
||||
ptrs[6] = JE8(0);
|
||||
|
||||
// ok
|
||||
xCMP(xRegister32(mmreg), 0x1e988);
|
||||
ptrs[7] = JE8(0);
|
||||
xCMP(xRegister32(mmreg), 0x1edd8);
|
||||
ptrs[8] = JE8(0);
|
||||
|
||||
x86SetJ8(ptrs[0]);
|
||||
x86SetJ8(ptrs[1]);
|
||||
x86SetJ8(ptrs[2]);
|
||||
x86SetJ8(ptrs[3]);
|
||||
x86SetJ8(ptrs[4]);
|
||||
x86SetJ8(ptrs[5]);
|
||||
x86SetJ8(ptrs[6]);
|
||||
xMOV(ptr32[&g_psxWriteOk], 0);
|
||||
ptrs[0] = JMP8(0);
|
||||
|
||||
x86SetJ8(ptrs[7]);
|
||||
x86SetJ8(ptrs[8]);
|
||||
xMOV(ptr32[&g_psxWriteOk], 1);
|
||||
|
||||
x86SetJ8(ptrs[0]);
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
|
||||
default:
|
||||
xTEST(ptr8[(u8*)((uptr)&g_psxWriteOk)], 1);
|
||||
j8Ptr[0] = JZ8(0);
|
||||
_eeWriteConstMem32((u32)PSXM(mem), mmreg);
|
||||
x86SetJ8(j8Ptr[0]);
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue