diff --git a/pcsx2/Counters.cpp b/pcsx2/Counters.cpp
index 62398ea880..d8af6b3f80 100644
--- a/pcsx2/Counters.cpp
+++ b/pcsx2/Counters.cpp
@@ -336,12 +336,8 @@ static __forceinline void VSyncStart(u32 sCycle)
 	EECNT_LOG( "/////////  EE COUNTER VSYNC START  \\\\\\\\\\\\\\\\\\\\  (frame: %d)", iFrame );
 	vSyncDebugStuff( iFrame ); // EE Profiling and Debug code
 
-	if ((CSRw & 0x8)) 
-	{
-		CSRw &= ~0x8;
-		GSCSRr|= 0x8;
-		if (!(GSIMR&0x800)) gsIrq();
-	}
+	if ((CSRw & 0x8)) GSCSRr|= 0x8;
+	if (!(GSIMR&0x800)) gsIrq();
 
 	hwIntcIrq(INTC_VBLANK_S);
 	psxVBlankStart();
@@ -408,12 +404,8 @@ __forceinline void rcntUpdate_hScanline()
 		hsyncCounter.Mode = MODE_HRENDER;
 	}
 	else { //HBLANK END / HRENDER Begin
-		if (CSRw & 0x4) 
-		{
-			CSRw &= ~0x4;
-			GSCSRr |= 4; // signal
-			if (!(GSIMR&0x400)) gsIrq();
-		}
+		if (CSRw & 0x4) GSCSRr |= 4; // signal
+		if (!(GSIMR&0x400)) gsIrq();
 		if (gates) rcntEndGate(false, hsyncCounter.sCycle);
 		if (psxhblankgate) psxCheckEndGate16(0);
 
diff --git a/pcsx2/GS.cpp b/pcsx2/GS.cpp
index cb7e28edf6..189327790f 100644
--- a/pcsx2/GS.cpp
+++ b/pcsx2/GS.cpp
@@ -243,8 +243,7 @@ void gsReset()
 
 	memzero_obj(g_RealGSMem);
 
-	CSRw = 0;
-	GSCSRr = 0x551B400F;   // Set the FINISH bit to 1 for now
+	GSCSRr = 0x551B4000;   // Set the FINISH bit to 1 for now
 	GSIMR = 0x7f00;
 	psHu32(GIF_STAT) = 0;
 	psHu32(GIF_CTRL) = 0;
@@ -276,12 +275,14 @@ void gsGIFReset()
 {
 	// fixme - should this be here? (air)
 	//memzero_obj(g_RealGSMem);
+	// none of this should be here, its a GIF reset, not GS, only the dma side of it is reset. (Refraction)
 
 	// perform a soft reset (but do not do a full reset if the soft reset API is unavailable)
-	gsGIFSoftReset( 7 );
+	//gsGIFSoftReset( 7 );
 
-	GSCSRr = 0x551B400F;   // Set the FINISH bit to 1 for now
-	GSIMR = 0x7f00;
+
+	//GSCSRr = 0x551B4000;   // Set the FINISH bit to 1 for now
+	//GSIMR = 0x7f00;
 	psHu32(GIF_STAT) = 0;
 	psHu32(GIF_CTRL) = 0;
 	psHu32(GIF_MODE) = 0;
@@ -316,7 +317,7 @@ void gsCSRwrite(u32 value)
 				GSreset();
 		}
 
-		GSCSRr = 0x551B400F;   // Set the FINISH bit to 1 - GS is always at a finish state as we don't have a FIFO(saqib)
+		GSCSRr = 0x551B4000;   // Set the FINISH bit to 1 - GS is always at a finish state as we don't have a FIFO(saqib)
 		GSIMR = 0x7F00; //This is bits 14-8 thats all that should be 1
 	}
 }
@@ -324,7 +325,8 @@ void gsCSRwrite(u32 value)
 static void IMRwrite(u32 value)
 {
 	GSIMR = (value & 0x1f00)|0x6000;
-	CSRw |= ~(GSIMR >> 8) & 0x1f;
+
+	if((GSCSRr & 0x1f) & (~(GSIMR >> 8) & 0x1f)) gsIrq();
 	// don't update mtgs mem
 }
 
@@ -434,6 +436,8 @@ void __fastcall gsWrite64_page_00( u32 mem, const mem64_t* value )
 
 void __fastcall gsWrite64_page_01( u32 mem, const mem64_t* value )
 {
+	GIF_LOG("GS Write64 at %8.8lx with data %8.8x_%8.8x", mem, (u32*)value[1], (u32*)value[0]);
+
 	switch( mem )
 	{
 		case GS_CSR:
diff --git a/pcsx2/Gif.cpp b/pcsx2/Gif.cpp
index cb884ed0a1..65f27fea9d 100644
--- a/pcsx2/Gif.cpp
+++ b/pcsx2/Gif.cpp
@@ -57,6 +57,12 @@ __forceinline void gsInterrupt() {
 		//Console::WriteLn("Eh? why are you still interrupting! chcr %x, qwc %x, done = %x", params gif->chcr, gif->qwc, done);
 		return;
 	}
+
+	if((vif1.cmd & 0x7f) == 0x51 && Path3progress != 0)
+	{
+		vif1Regs->stat &= ~VIF1_STAT_VGW;
+	}
+
 	if(Path3progress == 2) psHu32(GIF_STAT)&= ~(GIF_STAT_APATH3 | GIF_STAT_OPH); // OPH=0 | APATH=0
 
 	if (gif->qwc > 0 || gspath3done == 0) {
@@ -193,7 +199,7 @@ void GIFdma()
 
 	if(((psHu32(GIF_STAT) & 0x100) || (vif1.cmd & 0x7f) == 0x50) && (psHu32(GIF_MODE) & 0x4) && Path3progress == 0) //Path2 gets priority in intermittent mode
 	{
-		//GIF_LOG("Waiting VU %x, PATH2 %x, GIFMODE %x Progress %x", psHu32(GIF_STAT) & 0x100, (vif1.cmd & 0x7f), psHu32(GIF_MODE), Path3progress);
+		GIF_LOG("Waiting VU %x, PATH2 %x, GIFMODE %x Progress %x", psHu32(GIF_STAT) & 0x100, (vif1.cmd & 0x7f), psHu32(GIF_MODE), Path3progress);
 		dmaGIFend();
 		return;
 	}
@@ -287,7 +293,7 @@ void GIFdma()
 					return;
 				}
 			}
-			GIFchain();	//Transfers the data set by the switch
+			//GIFchain();	//Transfers the data set by the switch
 
 			if ((gif->chcr & 0x80) && (ptag[0] >> 31)) { //Check TIE bit of CHCR and IRQ bit of tag
 				GIF_LOG("dmaIrq Set");
diff --git a/pcsx2/MTGS.cpp b/pcsx2/MTGS.cpp
index 17416eb8e3..5ec6f831c1 100644
--- a/pcsx2/MTGS.cpp
+++ b/pcsx2/MTGS.cpp
@@ -137,17 +137,15 @@ void SaveState::mtgsFreeze()
 
 static void RegHandlerSIGNAL(const u32* data)
 {
-	MTGS_LOG("MTGS SIGNAL data %x_%x CSRw %x\n",data[0], data[1], CSRw);
+	GIF_LOG("MTGS SIGNAL data %x_%x CSRw %x IMR %x CSRr\n",data[0], data[1], CSRw, GSIMR, GSCSRr);
 
 	GSSIGLBLID->SIGID = (GSSIGLBLID->SIGID&~data[1])|(data[0]&data[1]);
 	
 	if ((CSRw & 0x1)) 
-	{
-		CSRw &= ~0x1;
 		GSCSRr |= 1; // signal
-		if (!(GSIMR&0x100) ) 
-			gsIrq();
-	}
+			
+	if (!(GSIMR&0x100) ) 
+		gsIrq();
 }
 
 static void RegHandlerFINISH(const u32* data)
@@ -155,12 +153,11 @@ static void RegHandlerFINISH(const u32* data)
 	MTGS_LOG("MTGS FINISH data %x_%x CSRw %x\n",data[0], data[1], CSRw);
 
 	if ((CSRw & 0x2)) 
-	{
 		GSCSRr |= 2; // finish
-		CSRw &= ~0x2;
-		if (!(GSIMR&0x200) )
-			gsIrq();
-	}
+		
+	if (!(GSIMR&0x200) )
+		gsIrq();
+	
 }
 
 static void RegHandlerLABEL(const u32* data)
@@ -529,7 +526,7 @@ int mtgsThreadObject::Callback()
 	
 	Console::WriteLn( "MTGS > GSopen Finished, return code: 0x%x", params m_returncode );
 
-	GSCSRr = 0x551B400F; // 0x55190000
+	GSCSRr = 0x551B4000; // 0x55190000
 	m_post_InitDone.Post();
 	if (m_returncode != 0) { return m_returncode; }		// error msg will be issued to the user by Plugins.c
 
diff --git a/pcsx2/VifDma.cpp b/pcsx2/VifDma.cpp
index e6ca05a339..d7428c52ce 100644
--- a/pcsx2/VifDma.cpp
+++ b/pcsx2/VifDma.cpp
@@ -2120,7 +2120,7 @@ static void Vif1CMDDirectHL()  // DIRECT/HL
 	//FIXME: This should have timing in both cases, see note below.
 	if((vif1.cmd & 0x7f) == 0x51)
 	{
-		if(gif->chcr & 0x100 && (!vif1Regs->mskpath3 || Path3progress != 2)) //PATH3 is in image mode, so wait for end of transfer
+		if(gif->chcr & 0x100 && (!vif1Regs->mskpath3 && Path3progress == 0)) //PATH3 is in image mode, so wait for end of transfer
 		{
 			//DevCon::Notice("DirectHL gif chcr %x gif qwc %x mskpth3 %x", params gif->chcr, gif->qwc, vif1Regs->mskpath3);
 			/*if(vif1Regs->mskpath3)*/vif1Regs->stat |= VIF1_STAT_VGW;