diff --git a/pcsx2/x86/microVU.cpp b/pcsx2/x86/microVU.cpp index a58200a911..4adcf883a9 100644 --- a/pcsx2/x86/microVU.cpp +++ b/pcsx2/x86/microVU.cpp @@ -35,7 +35,7 @@ declareAllVariables // Declares All Global Variables :D //------------------------------------------------------------------ // Only run this once per VU! ;) -microVUt(void) mVUinit(VURegs* vuRegsPtr) { +microVUf(void) mVUinit(VURegs* vuRegsPtr) { microVU* mVU = mVUx; mVU->regs = vuRegsPtr; @@ -71,8 +71,8 @@ microVUx(void) mVUreset() { // Setup Entrance/Exit Points x86SetPtr(mVU->cache); - mVUdispatcherA(); - mVUdispatcherB(); + mVUdispatcherA(mVU); + mVUdispatcherB(mVU); // Clear All Program Data memset(&mVU->prog, 0, sizeof(mVU->prog)); @@ -98,7 +98,7 @@ microVUx(void) mVUreset() { } // Free Allocated Resources -microVUt(void) mVUclose() { +microVUf(void) mVUclose() { microVU* mVU = mVUx; mVUprint((vuIndex) ? "microVU1: close" : "microVU0: close"); @@ -116,7 +116,7 @@ microVUt(void) mVUclose() { } // Clears Block Data in specified range -microVUt(void) mVUclear(u32 addr, u32 size) { +microVUf(void) mVUclear(u32 addr, u32 size) { microVU* mVU = mVUx; if (!mVU->prog.cleared) { memset(&mVU->prog.lpState, 0, sizeof(mVU->prog.lpState)); @@ -129,7 +129,7 @@ microVUt(void) mVUclear(u32 addr, u32 size) { //------------------------------------------------------------------ // Clears program data (Sets used to 1 because calling this function implies the program will be used at least once) -microVUt(void) mVUclearProg(int progIndex) { +microVUf(void) mVUclearProg(int progIndex) { microVU* mVU = mVUx; mVU->prog.prog[progIndex].used = 1; mVU->prog.prog[progIndex].last_used = 3; @@ -144,22 +144,22 @@ microVUt(void) mVUclearProg(int progIndex) { } // Caches Micro Program -microVUt(void) mVUcacheProg(int progIndex) { +microVUf(void) mVUcacheProg(int progIndex) { microVU* mVU = mVUx; memcpy_fast(mVU->prog.prog[progIndex].data, mVU->regs->Micro, mVU->microSize); mVUdumpProg(progIndex); - mVUcheckSflag(progIndex); + mVUcheckSflag(mVU, progIndex); } // Finds the least used program, (if program list full clears and returns an old program; if not-full, returns free program) -microVUt(int) mVUfindLeastUsedProg() { +microVUf(int) mVUfindLeastUsedProg() { microVU* mVU = mVUx; if (mVU->prog.total < mVU->prog.max) { mVU->prog.total++; mVUcacheProg(mVU->prog.total); // Cache Micro Program mVU->prog.prog[mVU->prog.total].used = 1; mVU->prog.prog[mVU->prog.total].last_used = 3; - DevCon::Notice("microVU%d: Cached MicroPrograms = %d", params vuIndex, mVU->prog.total+1); + Console::Notice("microVU%d: Cached MicroPrograms = %d", params vuIndex, mVU->prog.total+1); return mVU->prog.total; } else { @@ -192,7 +192,7 @@ microVUt(int) mVUfindLeastUsedProg() { // frame-based decrementing system in combination with a program-execution-based incrementing // system. In english: if last_used >= 2 it means the program has been used for the current // or prev frame. if it's 0, the program hasn't been used for a while. -microVUt(void) mVUvsyncUpdate() { +microVUf(void) mVUvsyncUpdate() { microVU* mVU = mVUx; if (mVU->prog.total < mVU->prog.max) return; @@ -211,7 +211,7 @@ microVUt(void) mVUvsyncUpdate() { } // Compare Cached microProgram to mVU->regs->Micro -microVUt(int) mVUcmpProg(int progIndex, bool progUsed, bool needOverflowCheck, bool cmpWholeProg) { +microVUf(int) mVUcmpProg(int progIndex, bool progUsed, bool needOverflowCheck, bool cmpWholeProg) { microVU* mVU = mVUx; if (progUsed) { @@ -231,7 +231,7 @@ microVUt(int) mVUcmpProg(int progIndex, bool progUsed, bool needOverflowCheck, b } // Searches for Cached Micro Program and sets prog.cur to it (returns 1 if program found, else returns 0) -microVUt(int) mVUsearchProg() { +microVUf(int) mVUsearchProg() { microVU* mVU = mVUx; if (mVU->prog.cleared) { // If cleared, we need to search for new program diff --git a/pcsx2/x86/microVU.h b/pcsx2/x86/microVU.h index 7a9c3326d3..c2445a93d4 100644 --- a/pcsx2/x86/microVU.h +++ b/pcsx2/x86/microVU.h @@ -137,24 +137,24 @@ extern void (*mVU_LOWER_OPCODE[128])( VURegs* VU, s32 info ); extern int mVUdebugNow; // Main Functions -microVUt(void) mVUinit(VURegs*); +microVUf(void) mVUinit(VURegs*); microVUx(void) mVUreset(); -microVUt(void) mVUclose(); -microVUt(void) mVUclear(u32, u32); +microVUf(void) mVUclose(); +microVUf(void) mVUclear(u32, u32); // Prototypes for Linux void __fastcall mVUcleanUpVU0(); void __fastcall mVUcleanUpVU1(); void* __fastcall mVUcompileVU0(u32 startPC, uptr pState); void* __fastcall mVUcompileVU1(u32 startPC, uptr pState); -microVUf(void) mVUopU(mF); -microVUf(void) mVUopL(mF); +mVUop(mVUopU); +mVUop(mVUopL); // Private Functions -microVUt(void) mVUclearProg(microVU* mVU, int progIndex); -microVUt(int) mVUfindLeastUsedProg(microVU* mVU); -microVUt(int) mVUsearchProg(); -microVUt(void) mVUcacheProg(int progIndex); +microVUf(void) mVUclearProg(microVU* mVU, int progIndex); +microVUf(int) mVUfindLeastUsedProg(microVU* mVU); +microVUf(int) mVUsearchProg(); +microVUf(void) mVUcacheProg(int progIndex); void* __fastcall mVUexecuteVU0(u32 startPC, u32 cycles); void* __fastcall mVUexecuteVU1(u32 startPC, u32 cycles); diff --git a/pcsx2/x86/microVU_Alloc.inl b/pcsx2/x86/microVU_Alloc.inl index 8556a6ec6a..0ab348f8be 100644 --- a/pcsx2/x86/microVU_Alloc.inl +++ b/pcsx2/x86/microVU_Alloc.inl @@ -26,23 +26,22 @@ // FMAC1 - Normal FMAC Opcodes //------------------------------------------------------------------ -#define getReg(reg, _reg_) { \ - mVUloadReg(reg, (uptr)&mVU->regs->VF[_reg_].UL[0], _X_Y_Z_W); \ - if (CHECK_VU_EXTRA_OVERFLOW) mVUclamp2(reg, xmmT2, _X_Y_Z_W); \ +#define getReg(reg, _reg_) { \ + mVUloadReg(reg, (uptr)&mVU->regs->VF[_reg_].UL[0], _X_Y_Z_W); \ + if (CHECK_VU_EXTRA_OVERFLOW) mVUclamp2(reg, xmmT2, _X_Y_Z_W); \ } -#define getZero(reg) { \ - if (_W) { mVUloadReg(reg, (uptr)&mVU->regs->VF[0].UL[0], _X_Y_Z_W); } \ - else { SSE_XORPS_XMM_to_XMM(reg, reg); } \ +#define getZero(reg) { \ + if (_W) { mVUloadReg(reg, (uptr)&mVU->regs->VF[0].UL[0], _X_Y_Z_W); } \ + else { SSE_XORPS_XMM_to_XMM(reg, reg); } \ } -#define getReg6(reg, _reg_) { \ - if (!_reg_) { getZero(reg); } \ - else { getReg(reg, _reg_); } \ +#define getReg6(reg, _reg_) { \ + if (!_reg_) { getZero(reg); } \ + else { getReg(reg, _reg_); } \ } -microVUt(void) mVUallocFMAC1a(int& Fd, int& Fs, int& Ft) { - microVU* mVU = mVUx; +microVUt(void) mVUallocFMAC1a(mV, int& Fd, int& Fs, int& Ft) { Fs = xmmFs; Ft = xmmFt; Fd = xmmFs; @@ -51,61 +50,57 @@ microVUt(void) mVUallocFMAC1a(int& Fd, int& Fs, int& Ft) { else { getReg6(Ft, _Ft_); } } -microVUt(void) mVUallocFMAC1b(int& Fd) { - microVU* mVU = mVUx; +microVUt(void) mVUallocFMAC1b(mV, int& Fd) { if (!_Fd_) return; - if (CHECK_VU_OVERFLOW) mVUclamp1(Fd, xmmT1, _X_Y_Z_W); - mVUsaveReg(Fd, (uptr)&mVU->regs->VF[_Fd_].UL[0], _X_Y_Z_W, 1); + if (CHECK_VU_OVERFLOW) mVUclamp1(Fd, xmmT1, _X_Y_Z_W); + mVUsaveReg(Fd, (uptr)&mVU->regs->VF[_Fd_].UL[0], _X_Y_Z_W, 1); } //------------------------------------------------------------------ // FMAC2 - ABS/FTOI/ITOF Opcodes //------------------------------------------------------------------ -microVUt(void) mVUallocFMAC2a(int& Fs, int& Ft) { - microVU* mVU = mVUx; +microVUt(void) mVUallocFMAC2a(mV, int& Fs, int& Ft) { Fs = xmmFs; Ft = xmmFs; getReg6(Fs, _Fs_); } -microVUt(void) mVUallocFMAC2b(int& Ft) { - microVU* mVU = mVUx; +microVUt(void) mVUallocFMAC2b(mV, int& Ft) { if (!_Ft_) return; //if (CHECK_VU_OVERFLOW) mVUclamp1(Ft, xmmT1, _X_Y_Z_W); - mVUsaveReg(Ft, (uptr)&mVU->regs->VF[_Ft_].UL[0], _X_Y_Z_W, 1); + mVUsaveReg(Ft, (uptr)&mVU->regs->VF[_Ft_].UL[0], _X_Y_Z_W, 1); } //------------------------------------------------------------------ // FMAC3 - BC(xyzw) FMAC Opcodes //------------------------------------------------------------------ -#define getReg3SS(reg, _reg_) { \ - mVUloadReg(reg, (uptr)&mVU->regs->VF[_reg_].UL[0], (1 << (3 - _bc_))); \ - if (CHECK_VU_EXTRA_OVERFLOW) mVUclamp2(reg, xmmT2, (1 << (3 - _bc_))); \ +#define getReg3SS(reg, _reg_) { \ + mVUloadReg(reg, (uptr)&mVU->regs->VF[_reg_].UL[0], (1 << (3 - _bc_))); \ + if (CHECK_VU_EXTRA_OVERFLOW) mVUclamp2(reg, xmmT2, (1 << (3 - _bc_))); \ } -#define getReg3(reg, _reg_) { \ - mVUloadReg(reg, (uptr)&mVU->regs->VF[_reg_].UL[0], (1 << (3 - _bc_))); \ - if (CHECK_VU_EXTRA_OVERFLOW) mVUclamp2(reg, xmmT2, (1 << (3 - _bc_))); \ - mVUunpack_xyzw(reg, reg, 0); \ +#define getReg3(reg, _reg_) { \ + mVUloadReg(reg, (uptr)&mVU->regs->VF[_reg_].UL[0], (1 << (3 - _bc_))); \ + if (CHECK_VU_EXTRA_OVERFLOW) mVUclamp2(reg, xmmT2, (1 << (3 - _bc_))); \ + mVUunpack_xyzw(reg, reg, 0); \ } -#define getZero3SS(reg) { \ - if (_bc_w) { mVUloadReg(reg, (uptr)&mVU->regs->VF[0].UL[0], 1); } \ - else { SSE_XORPS_XMM_to_XMM(reg, reg); } \ +#define getZero3SS(reg) { \ + if (_bc_w) { mVUloadReg(reg, (uptr)&mVU->regs->VF[0].UL[0], 1); } \ + else { SSE_XORPS_XMM_to_XMM(reg, reg); } \ } -#define getZero3(reg) { \ - if (_bc_w) { \ - mVUloadReg(reg, (uptr)&mVU->regs->VF[0].UL[0], 1); \ - mVUunpack_xyzw(reg, reg, 0); \ - } \ - else { SSE_XORPS_XMM_to_XMM(reg, reg); } \ +#define getZero3(reg) { \ + if (_bc_w) { \ + mVUloadReg(reg, (uptr)&mVU->regs->VF[0].UL[0], 1); \ + mVUunpack_xyzw(reg, reg, 0); \ + } \ + else { SSE_XORPS_XMM_to_XMM(reg, reg); } \ } -microVUt(void) mVUallocFMAC3a(int& Fd, int& Fs, int& Ft) { - microVU* mVU = mVUx; +microVUt(void) mVUallocFMAC3a(mV, int& Fd, int& Fs, int& Ft) { Fs = xmmFs; Ft = xmmFt; Fd = xmmFs; @@ -124,26 +119,25 @@ microVUt(void) mVUallocFMAC3a(int& Fd, int& Fs, int& Ft) { } } -microVUt(void) mVUallocFMAC3b(int& Fd) { - mVUallocFMAC1b(Fd); +microVUt(void) mVUallocFMAC3b(mV, int& Fd) { + mVUallocFMAC1b(mVU, Fd); } //------------------------------------------------------------------ // FMAC4 - FMAC Opcodes Storing Result to ACC //------------------------------------------------------------------ -#define getReg4(reg, _reg_) { \ - mVUloadReg(reg, (uptr)&mVU->regs->VF[_reg_].UL[0], _xyzw_ACC); \ - if (CHECK_VU_EXTRA_OVERFLOW) mVUclamp2(reg, xmmT2, _xyzw_ACC); \ +#define getReg4(reg, _reg_) { \ + mVUloadReg(reg, (uptr)&mVU->regs->VF[_reg_].UL[0], _xyzw_ACC); \ + if (CHECK_VU_EXTRA_OVERFLOW) mVUclamp2(reg, xmmT2, _xyzw_ACC); \ } -#define getZero4(reg) { \ - if (_W) { mVUloadReg(reg, (uptr)&mVU->regs->VF[0].UL[0], _xyzw_ACC); } \ - else { SSE_XORPS_XMM_to_XMM(reg, reg); } \ +#define getZero4(reg) { \ + if (_W) { mVUloadReg(reg, (uptr)&mVU->regs->VF[0].UL[0], _xyzw_ACC); } \ + else { SSE_XORPS_XMM_to_XMM(reg, reg); } \ } -microVUt(void) mVUallocFMAC4a(int& ACC, int& Fs, int& Ft) { - microVU* mVU = mVUx; +microVUt(void) mVUallocFMAC4a(mV, int& ACC, int& Fs, int& Ft) { ACC = xmmACC; Fs = (_X_Y_Z_W == 15) ? xmmACC : xmmFs; Ft = xmmFt; @@ -162,9 +156,8 @@ microVUt(void) mVUallocFMAC4a(int& ACC, int& Fs, int& Ft) { } } -microVUt(void) mVUallocFMAC4b(int& ACC, int& Fs) { - microVU* mVU = mVUx; - if (CHECK_VU_OVERFLOW) mVUclamp1(Fs, xmmT1, _xyzw_ACC); +microVUt(void) mVUallocFMAC4b(mV, int& ACC, int& Fs) { + if (CHECK_VU_OVERFLOW) mVUclamp1(Fs, xmmT1, _xyzw_ACC); mVUmergeRegs(ACC, Fs, _X_Y_Z_W); } @@ -172,8 +165,7 @@ microVUt(void) mVUallocFMAC4b(int& ACC, int& Fs) { // FMAC5 - FMAC BC(xyzw) Opcodes Storing Result to ACC //------------------------------------------------------------------ -microVUt(void) mVUallocFMAC5a(int& ACC, int& Fs, int& Ft) { - microVU* mVU = mVUx; +microVUt(void) mVUallocFMAC5a(mV, int& ACC, int& Fs, int& Ft) { ACC = xmmACC; Fs = (_X_Y_Z_W == 15) ? xmmACC : xmmFs; Ft = xmmFt; @@ -192,23 +184,22 @@ microVUt(void) mVUallocFMAC5a(int& ACC, int& Fs, int& Ft) { } } -microVUt(void) mVUallocFMAC5b(int& ACC, int& Fs) { - mVUallocFMAC4b(ACC, Fs); +microVUt(void) mVUallocFMAC5b(mV, int& ACC, int& Fs) { + mVUallocFMAC4b(mVU, ACC, Fs); } //------------------------------------------------------------------ // FMAC6 - Normal FMAC Opcodes (I Reg) //------------------------------------------------------------------ -#define getIreg(reg, modXYZW) { \ - MOV32MtoR(gprT1, (uptr)&mVU->regs->VI[REG_I].UL); \ - SSE2_MOVD_R_to_XMM(reg, gprT1); \ - if (CHECK_VU_EXTRA_OVERFLOW) mVUclamp2(reg, xmmT2, 8); \ - if (!((_XYZW_SS && modXYZW) || (_X_Y_Z_W == 8))) { mVUunpack_xyzw(reg, reg, 0); } \ +#define getIreg(reg, modXYZW) { \ + MOV32MtoR(gprT1, (uptr)&mVU->regs->VI[REG_I].UL); \ + SSE2_MOVD_R_to_XMM(reg, gprT1); \ + if (CHECK_VU_EXTRA_OVERFLOW) mVUclamp2(reg, xmmT2, 8); \ + if (!((_XYZW_SS && modXYZW) || (_X_Y_Z_W == 8))) { mVUunpack_xyzw(reg, reg, 0); } \ } -microVUt(void) mVUallocFMAC6a(int& Fd, int& Fs, int& Ft) { - microVU* mVU = mVUx; +microVUt(void) mVUallocFMAC6a(mV, int& Fd, int& Fs, int& Ft) { Fs = xmmFs; Ft = xmmFt; Fd = xmmFs; @@ -216,16 +207,15 @@ microVUt(void) mVUallocFMAC6a(int& Fd, int& Fs, int& Ft) { getReg6(Fs, _Fs_); } -microVUt(void) mVUallocFMAC6b(int& Fd) { - mVUallocFMAC1b(Fd); +microVUt(void) mVUallocFMAC6b(mV, int& Fd) { + mVUallocFMAC1b(mVU, Fd); } //------------------------------------------------------------------ // FMAC7 - FMAC Opcodes Storing Result to ACC (I Reg) //------------------------------------------------------------------ -microVUt(void) mVUallocFMAC7a(int& ACC, int& Fs, int& Ft) { - microVU* mVU = mVUx; +microVUt(void) mVUallocFMAC7a(mV, int& ACC, int& Fs, int& Ft) { ACC = xmmACC; Fs = (_X_Y_Z_W == 15) ? xmmACC : xmmFs; Ft = xmmFt; @@ -235,16 +225,15 @@ microVUt(void) mVUallocFMAC7a(int& ACC, int& Fs, int& Ft) { else { getReg4(Fs, _Fs_); } } -microVUt(void) mVUallocFMAC7b(int& ACC, int& Fs) { - mVUallocFMAC4b(ACC, Fs); +microVUt(void) mVUallocFMAC7b(mV, int& ACC, int& Fs) { + mVUallocFMAC4b(mVU, ACC, Fs); } //------------------------------------------------------------------ // FMAC8 - MADD FMAC Opcode Storing Result to Fd //------------------------------------------------------------------ -microVUt(void) mVUallocFMAC8a(int& Fd, int& ACC, int& Fs, int& Ft) { - microVU* mVU = mVUx; +microVUt(void) mVUallocFMAC8a(mV, int& Fd, int& ACC, int& Fs, int& Ft) { Fs = xmmFs; Ft = xmmFt; Fd = xmmFs; @@ -264,19 +253,17 @@ microVUt(void) mVUallocFMAC8a(int& Fd, int& ACC, int& Fs, int& Ft) { } } -microVUt(void) mVUallocFMAC8b(int& Fd) { - microVU* mVU = mVUx; +microVUt(void) mVUallocFMAC8b(mV, int& Fd) { if (!_Fd_) return; - if (CHECK_VU_OVERFLOW) mVUclamp1(Fd, xmmT1, _xyzw_ACC); - mVUsaveReg(Fd, (uptr)&mVU->regs->VF[_Fd_].UL[0], _X_Y_Z_W, 0); + if (CHECK_VU_OVERFLOW) mVUclamp1(Fd, xmmT1, _xyzw_ACC); + mVUsaveReg(Fd, (uptr)&mVU->regs->VF[_Fd_].UL[0], _X_Y_Z_W, 0); } //------------------------------------------------------------------ // FMAC9 - MSUB FMAC Opcode Storing Result to Fd //------------------------------------------------------------------ -microVUt(void) mVUallocFMAC9a(int& Fd, int& ACC, int& Fs, int& Ft) { - microVU* mVU = mVUx; +microVUt(void) mVUallocFMAC9a(mV, int& Fd, int& ACC, int& Fs, int& Ft) { Fs = xmmFs; Ft = xmmFt; Fd = xmmT1; @@ -297,19 +284,17 @@ microVUt(void) mVUallocFMAC9a(int& Fd, int& ACC, int& Fs, int& Ft) { SSE_MOVAPS_XMM_to_XMM(ACC, xmmACC); } -microVUt(void) mVUallocFMAC9b(int& Fd) { - microVU* mVU = mVUx; +microVUt(void) mVUallocFMAC9b(mV, int& Fd) { if (!_Fd_) return; - if (CHECK_VU_OVERFLOW) mVUclamp1(Fd, xmmFt, _xyzw_ACC); - mVUsaveReg(Fd, (uptr)&mVU->regs->VF[_Fd_].UL[0], _X_Y_Z_W, 0); + if (CHECK_VU_OVERFLOW) mVUclamp1(Fd, xmmFt, _xyzw_ACC); + mVUsaveReg(Fd, (uptr)&mVU->regs->VF[_Fd_].UL[0], _X_Y_Z_W, 0); } //------------------------------------------------------------------ // FMAC10 - MADD FMAC BC(xyzw) Opcode Storing Result to Fd //------------------------------------------------------------------ -microVUt(void) mVUallocFMAC10a(int& Fd, int& ACC, int& Fs, int& Ft) { - microVU* mVU = mVUx; +microVUt(void) mVUallocFMAC10a(mV, int& Fd, int& ACC, int& Fs, int& Ft) { Fs = xmmFs; Ft = xmmFt; Fd = xmmFs; @@ -329,16 +314,15 @@ microVUt(void) mVUallocFMAC10a(int& Fd, int& ACC, int& Fs, int& Ft) { } } -microVUt(void) mVUallocFMAC10b(int& Fd) { - mVUallocFMAC8b(Fd); +microVUt(void) mVUallocFMAC10b(mV, int& Fd) { + mVUallocFMAC8b(mVU, Fd); } //------------------------------------------------------------------ // FMAC11 - MSUB FMAC BC(xyzw) Opcode Storing Result to Fd //------------------------------------------------------------------ -microVUt(void) mVUallocFMAC11a(int& Fd, int& ACC, int& Fs, int& Ft) { - microVU* mVU = mVUx; +microVUt(void) mVUallocFMAC11a(mV, int& Fd, int& ACC, int& Fs, int& Ft) { Fs = xmmFs; Ft = xmmFt; Fd = xmmT1; @@ -359,16 +343,15 @@ microVUt(void) mVUallocFMAC11a(int& Fd, int& ACC, int& Fs, int& Ft) { SSE_MOVAPS_XMM_to_XMM(ACC, xmmACC); } -microVUt(void) mVUallocFMAC11b(int& Fd) { - mVUallocFMAC9b(Fd); +microVUt(void) mVUallocFMAC11b(mV, int& Fd) { + mVUallocFMAC9b(mVU, Fd); } //------------------------------------------------------------------ // FMAC12 - MADD FMAC Opcode Storing Result to Fd (I Reg) //------------------------------------------------------------------ -microVUt(void) mVUallocFMAC12a(int& Fd, int& ACC, int& Fs, int& Ft) { - microVU* mVU = mVUx; +microVUt(void) mVUallocFMAC12a(mV, int& Fd, int& ACC, int& Fs, int& Ft) { Fs = xmmFs; Ft = xmmFt; Fd = xmmFs; @@ -379,16 +362,15 @@ microVUt(void) mVUallocFMAC12a(int& Fd, int& ACC, int& Fs, int& Ft) { else { getReg4(Fs, _Fs_); } } -microVUt(void) mVUallocFMAC12b(int& Fd) { - mVUallocFMAC8b(Fd); +microVUt(void) mVUallocFMAC12b(mV, int& Fd) { + mVUallocFMAC8b(mVU, Fd); } //------------------------------------------------------------------ // FMAC13 - MSUB FMAC Opcode Storing Result to Fd (I Reg) //------------------------------------------------------------------ -microVUt(void) mVUallocFMAC13a(int& Fd, int& ACC, int& Fs, int& Ft) { - microVU* mVU = mVUx; +microVUt(void) mVUallocFMAC13a(mV, int& Fd, int& ACC, int& Fs, int& Ft) { Fs = xmmFs; Ft = xmmFt; Fd = xmmT1; @@ -400,16 +382,15 @@ microVUt(void) mVUallocFMAC13a(int& Fd, int& ACC, int& Fs, int& Ft) { SSE_MOVAPS_XMM_to_XMM(ACC, xmmACC); } -microVUt(void) mVUallocFMAC13b(int& Fd) { - mVUallocFMAC9b(Fd); +microVUt(void) mVUallocFMAC13b(mV, int& Fd) { + mVUallocFMAC9b(mVU, Fd); } //------------------------------------------------------------------ // FMAC14 - MADDA/MSUBA FMAC Opcodes //------------------------------------------------------------------ -microVUt(void) mVUallocFMAC14a(int& ACCw, int& ACCr, int& Fs, int& Ft) { - microVU* mVU = mVUx; +microVUt(void) mVUallocFMAC14a(mV, int& ACCw, int& ACCr, int& Fs, int& Ft) { Fs = xmmFs; Ft = xmmFt; ACCw = xmmACC; @@ -431,9 +412,8 @@ microVUt(void) mVUallocFMAC14a(int& ACCw, int& ACCr, int& Fs, int& Ft) { SSE_MOVAPS_XMM_to_XMM(ACCr, xmmACC); } -microVUt(void) mVUallocFMAC14b(int& ACCw, int& ACCr) { - microVU* mVU = mVUx; - if (CHECK_VU_OVERFLOW) mVUclamp1(ACCr, xmmFt, _xyzw_ACC); +microVUt(void) mVUallocFMAC14b(mV, int& ACCw, int& ACCr) { + if (CHECK_VU_OVERFLOW) mVUclamp1(ACCr, xmmFt, _xyzw_ACC); mVUmergeRegs(ACCw, ACCr, _X_Y_Z_W); } @@ -441,8 +421,7 @@ microVUt(void) mVUallocFMAC14b(int& ACCw, int& ACCr) { // FMAC15 - MADDA/MSUBA BC(xyzw) FMAC Opcode //------------------------------------------------------------------ -microVUt(void) mVUallocFMAC15a(int& ACCw, int& ACCr, int& Fs, int& Ft) { - microVU* mVU = mVUx; +microVUt(void) mVUallocFMAC15a(mV, int& ACCw, int& ACCr, int& Fs, int& Ft) { Fs = xmmFs; Ft = xmmFt; ACCw = xmmACC; @@ -464,16 +443,15 @@ microVUt(void) mVUallocFMAC15a(int& ACCw, int& ACCr, int& Fs, int& Ft) { SSE_MOVAPS_XMM_to_XMM(ACCr, xmmACC); } -microVUt(void) mVUallocFMAC15b(int& ACCw, int& ACCr) { - mVUallocFMAC14b(ACCw, ACCr); +microVUt(void) mVUallocFMAC15b(mV, int& ACCw, int& ACCr) { + mVUallocFMAC14b(mVU, ACCw, ACCr); } //------------------------------------------------------------------ // FMAC16 - MADDA/MSUBA FMAC Opcode (I Reg) //------------------------------------------------------------------ -microVUt(void) mVUallocFMAC16a(int& ACCw, int& ACCr, int& Fs, int& Ft) { - microVU* mVU = mVUx; +microVUt(void) mVUallocFMAC16a(mV, int& ACCw, int& ACCr, int& Fs, int& Ft) { Fs = xmmFs; Ft = xmmFt; ACCw = xmmACC; @@ -485,22 +463,21 @@ microVUt(void) mVUallocFMAC16a(int& ACCw, int& ACCr, int& Fs, int& Ft) { SSE_MOVAPS_XMM_to_XMM(ACCr, xmmACC); } -microVUt(void) mVUallocFMAC16b(int& ACCw, int& ACCr) { - mVUallocFMAC14b(ACCw, ACCr); +microVUt(void) mVUallocFMAC16b(mV, int& ACCw, int& ACCr) { + mVUallocFMAC14b(mVU, ACCw, ACCr); } //------------------------------------------------------------------ // FMAC17 - CLIP FMAC Opcode //------------------------------------------------------------------ -#define getReg9(reg, _reg_) { \ - mVUloadReg(reg, (uptr)&mVU->regs->VF[_reg_].UL[0], 1); \ - if (CHECK_VU_EXTRA_OVERFLOW) mVUclamp2(reg, xmmT2, 1); \ - mVUunpack_xyzw(reg, reg, 0); \ +#define getReg9(reg, _reg_) { \ + mVUloadReg(reg, (uptr)&mVU->regs->VF[_reg_].UL[0], 1); \ + if (CHECK_VU_EXTRA_OVERFLOW) mVUclamp2(reg, xmmT2, 1); \ + mVUunpack_xyzw(reg, reg, 0); \ } -microVUt(void) mVUallocFMAC17a(int& Fs, int& Ft) { - microVU* mVU = mVUx; +microVUt(void) mVUallocFMAC17a(mV, int& Fs, int& Ft) { Fs = xmmFs; Ft = xmmFt; getReg6(Fs, _Fs_); @@ -511,8 +488,7 @@ microVUt(void) mVUallocFMAC17a(int& Fs, int& Ft) { // FMAC18 - OPMULA FMAC Opcode //------------------------------------------------------------------ -microVUt(void) mVUallocFMAC18a(int& ACC, int& Fs, int& Ft) { - microVU* mVU = mVUx; +microVUt(void) mVUallocFMAC18a(mV, int& ACC, int& Fs, int& Ft) { Fs = xmmFs; Ft = xmmFt; ACC = xmmACC; @@ -527,16 +503,15 @@ microVUt(void) mVUallocFMAC18a(int& ACC, int& Fs, int& Ft) { SSE2_PSHUFD_XMM_to_XMM(Ft, Ft, 0xD2); // WYXZ } -microVUt(void) mVUallocFMAC18b(int& ACC, int& Fs) { - mVUallocFMAC4b(ACC, Fs); +microVUt(void) mVUallocFMAC18b(mV, int& ACC, int& Fs) { + mVUallocFMAC4b(mVU, ACC, Fs); } //------------------------------------------------------------------ // FMAC19 - OPMSUB FMAC Opcode //------------------------------------------------------------------ -microVUt(void) mVUallocFMAC19a(int& Fd, int& ACC, int& Fs, int& Ft) { - microVU* mVU = mVUx; +microVUt(void) mVUallocFMAC19a(mV, int& Fd, int& ACC, int& Fs, int& Ft) { Fs = xmmFs; Ft = xmmFt; Fd = xmmT1; @@ -553,21 +528,20 @@ microVUt(void) mVUallocFMAC19a(int& Fd, int& ACC, int& Fs, int& Ft) { SSE_MOVAPS_XMM_to_XMM(ACC, xmmACC); } -microVUt(void) mVUallocFMAC19b(int& Fd) { - mVUallocFMAC9b(Fd); +microVUt(void) mVUallocFMAC19b(mV, int& Fd) { + mVUallocFMAC9b(mVU, Fd); } //------------------------------------------------------------------ // FMAC22 - Normal FMAC Opcodes (Q Reg) //------------------------------------------------------------------ -#define getQreg(reg) { \ - mVUunpack_xyzw(reg, xmmPQ, readQ); \ - /*if (CHECK_VU_EXTRA_OVERFLOW) mVUclamp2(reg, xmmT1, 15);*/ \ +#define getQreg(reg) { \ + mVUunpack_xyzw(reg, xmmPQ, readQ); \ + /*if (CHECK_VU_EXTRA_OVERFLOW) mVUclamp2(reg, xmmT1, 15);*/ \ } -microVUt(void) mVUallocFMAC22a(int& Fd, int& Fs, int& Ft) { - microVU* mVU = mVUx; +microVUt(void) mVUallocFMAC22a(mV, int& Fd, int& Fs, int& Ft) { Fs = xmmFs; Ft = xmmFt; Fd = xmmFs; @@ -575,16 +549,15 @@ microVUt(void) mVUallocFMAC22a(int& Fd, int& Fs, int& Ft) { getReg6(Fs, _Fs_); } -microVUt(void) mVUallocFMAC22b(int& Fd) { - mVUallocFMAC1b(Fd); +microVUt(void) mVUallocFMAC22b(mV, int& Fd) { + mVUallocFMAC1b(mVU, Fd); } //------------------------------------------------------------------ // FMAC23 - FMAC Opcodes Storing Result to ACC (Q Reg) //------------------------------------------------------------------ -microVUt(void) mVUallocFMAC23a(int& ACC, int& Fs, int& Ft) { - microVU* mVU = mVUx; +microVUt(void) mVUallocFMAC23a(mV, int& ACC, int& Fs, int& Ft) { ACC = xmmACC; Fs = (_X_Y_Z_W == 15) ? xmmACC : xmmFs; Ft = xmmFt; @@ -594,16 +567,15 @@ microVUt(void) mVUallocFMAC23a(int& ACC, int& Fs, int& Ft) { else { getReg4(Fs, _Fs_); } } -microVUt(void) mVUallocFMAC23b(int& ACC, int& Fs) { - mVUallocFMAC4b(ACC, Fs); +microVUt(void) mVUallocFMAC23b(mV, int& ACC, int& Fs) { + mVUallocFMAC4b(mVU, ACC, Fs); } //------------------------------------------------------------------ // FMAC24 - MADD FMAC Opcode Storing Result to Fd (Q Reg) //------------------------------------------------------------------ -microVUt(void) mVUallocFMAC24a(int& Fd, int& ACC, int& Fs, int& Ft) { - microVU* mVU = mVUx; +microVUt(void) mVUallocFMAC24a(mV, int& Fd, int& ACC, int& Fs, int& Ft) { Fs = xmmFs; Ft = xmmFt; Fd = xmmFs; @@ -614,16 +586,15 @@ microVUt(void) mVUallocFMAC24a(int& Fd, int& ACC, int& Fs, int& Ft) { else { getReg4(Fs, _Fs_); } } -microVUt(void) mVUallocFMAC24b(int& Fd) { - mVUallocFMAC8b(Fd); +microVUt(void) mVUallocFMAC24b(mV, int& Fd) { + mVUallocFMAC8b(mVU, Fd); } //------------------------------------------------------------------ // FMAC25 - MSUB FMAC Opcode Storing Result to Fd (Q Reg) //------------------------------------------------------------------ -microVUt(void) mVUallocFMAC25a(int& Fd, int& ACC, int& Fs, int& Ft) { - microVU* mVU = mVUx; +microVUt(void) mVUallocFMAC25a(mV, int& Fd, int& ACC, int& Fs, int& Ft) { Fs = xmmFs; Ft = xmmFt; Fd = xmmT1; @@ -635,16 +606,15 @@ microVUt(void) mVUallocFMAC25a(int& Fd, int& ACC, int& Fs, int& Ft) { SSE_MOVAPS_XMM_to_XMM(ACC, xmmACC); } -microVUt(void) mVUallocFMAC25b(int& Fd) { - mVUallocFMAC9b(Fd); +microVUt(void) mVUallocFMAC25b(mV, int& Fd) { + mVUallocFMAC9b(mVU, Fd); } //------------------------------------------------------------------ // FMAC26 - MADDA/MSUBA FMAC Opcode (Q Reg) //------------------------------------------------------------------ -microVUt(void) mVUallocFMAC26a(int& ACCw, int& ACCr, int& Fs, int& Ft) { - microVU* mVU = mVUx; +microVUt(void) mVUallocFMAC26a(mV, int& ACCw, int& ACCr, int& Fs, int& Ft) { Fs = xmmFs; Ft = xmmFt; ACCw = xmmACC; @@ -656,8 +626,8 @@ microVUt(void) mVUallocFMAC26a(int& ACCw, int& ACCr, int& Fs, int& Ft) { SSE_MOVAPS_XMM_to_XMM(ACCr, xmmACC); } -microVUt(void) mVUallocFMAC26b(int& ACCw, int& ACCr) { - mVUallocFMAC14b(ACCw, ACCr); +microVUt(void) mVUallocFMAC26b(mV, int& ACCw, int& ACCr) { + mVUallocFMAC14b(mVU, ACCw, ACCr); } //------------------------------------------------------------------ @@ -688,24 +658,20 @@ microVUt(void) mVUallocSFLAGb(int reg, int fInstance) { MOV32RtoR(fInstance, reg); } -microVUt(void) mVUallocMFLAGa(int reg, int fInstance) { - microVU* mVU = mVUx; +microVUt(void) mVUallocMFLAGa(mV, int reg, int fInstance) { MOVZX32M16toR(reg, (uptr)&mVU->macFlag[fInstance]); } -microVUt(void) mVUallocMFLAGb(int reg, int fInstance) { - microVU* mVU = mVUx; +microVUt(void) mVUallocMFLAGb(mV, int reg, int fInstance) { //AND32ItoR(reg, 0xffff); MOV32RtoM((uptr)&mVU->macFlag[fInstance], reg); } -microVUt(void) mVUallocCFLAGa(int reg, int fInstance) { - microVU* mVU = mVUx; +microVUt(void) mVUallocCFLAGa(mV, int reg, int fInstance) { MOV32MtoR(reg, (uptr)&mVU->clipFlag[fInstance]); } -microVUt(void) mVUallocCFLAGb(int reg, int fInstance) { - microVU* mVU = mVUx; +microVUt(void) mVUallocCFLAGb(mV, int reg, int fInstance) { MOV32RtoM((uptr)&mVU->clipFlag[fInstance], reg); } @@ -713,18 +679,16 @@ microVUt(void) mVUallocCFLAGb(int reg, int fInstance) { // VI Reg Allocators //------------------------------------------------------------------ -microVUt(void) mVUallocVIa(int GPRreg, int _reg_) { - microVU* mVU = mVUx; +microVUt(void) mVUallocVIa(mV, int GPRreg, int _reg_) { if (!_reg_) { XOR32RtoR(GPRreg, GPRreg); } else if (isMMX(_reg_)) { MOVD32MMXtoR(GPRreg, mmVI(_reg_)); } else { MOVZX32Rm16toR(GPRreg, gprR, (_reg_ - 9) * 16); } } -microVUt(void) mVUallocVIb(int GPRreg, int _reg_) { - microVU* mVU = mVUx; +microVUt(void) mVUallocVIb(mV, int GPRreg, int _reg_) { if (backupVI) { // Backs up reg to memory (used when VI is modified b4 a branch) MOV32RtoM((uptr)&mVU->VIbackup[1], GPRreg); - mVUallocVIa(GPRreg, _reg_); + mVUallocVIa(mVU, GPRreg, _reg_); MOV32RtoM((uptr)&mVU->VIbackup[0], GPRreg); MOV32MtoR(GPRreg, (uptr)&mVU->VIbackup[1]); } @@ -737,34 +701,34 @@ microVUt(void) mVUallocVIb(int GPRreg, int _reg_) { // P Reg Allocator //------------------------------------------------------------------ -#define getPreg(reg) { \ - mVUunpack_xyzw(reg, xmmPQ, (2 + readP)); \ - /*if (CHECK_VU_EXTRA_OVERFLOW) mVUclamp2(reg, xmmT1, 15);*/ \ +#define getPreg(reg) { \ + mVUunpack_xyzw(reg, xmmPQ, (2 + readP)); \ + /*if (CHECK_VU_EXTRA_OVERFLOW) mVUclamp2(reg, xmmT1, 15);*/ \ } //------------------------------------------------------------------ // Lower Instruction Allocator Helpers //------------------------------------------------------------------ -#define getReg5(reg, _reg_, _fxf_) { \ - if (!_reg_) { \ - if (_fxf_ < 3) { SSE_XORPS_XMM_to_XMM(reg, reg); } \ - else { mVUloadReg(reg, (uptr)&mVU->regs->VF[_reg_].UL[0], 1); } \ - } \ - else { \ - mVUloadReg(reg, (uptr)&mVU->regs->VF[_reg_].UL[0], (1 << (3 - _fxf_))); \ - if (CHECK_VU_EXTRA_OVERFLOW) mVUclamp2(reg, xmmT2, (1 << (3 - _fxf_))); \ - } \ +#define getReg5(reg, _reg_, _fxf_) { \ + if (!_reg_) { \ + if (_fxf_ < 3) { SSE_XORPS_XMM_to_XMM(reg, reg); } \ + else { mVUloadReg(reg, (uptr)&mVU->regs->VF[_reg_].UL[0], 1); } \ + } \ + else { \ + mVUloadReg(reg, (uptr)&mVU->regs->VF[_reg_].UL[0], (1 << (3 - _fxf_))); \ + if (CHECK_VU_EXTRA_OVERFLOW) mVUclamp2(reg, xmmT2, (1 << (3 - _fxf_))); \ + } \ } // Doesn't Clamp -#define getReg7(reg, _reg_) { \ - if (!_reg_) { getZero(reg); } \ - else { mVUloadReg(reg, (uptr)&mVU->regs->VF[_reg_].UL[0], _X_Y_Z_W); } \ +#define getReg7(reg, _reg_) { \ + if (!_reg_) { getZero(reg); } \ + else { mVUloadReg(reg, (uptr)&mVU->regs->VF[_reg_].UL[0], _X_Y_Z_W); } \ } // VF to GPR -#define getReg8(GPRreg, _reg_, _fxf_) { \ - if (!_reg_ && (_fxf_ < 3)) { XOR32RtoR(GPRreg, GPRreg); } \ - else { MOV32MtoR(GPRreg, (uptr)&mVU->regs->VF[_reg_].UL[0]); } \ +#define getReg8(GPRreg, _reg_, _fxf_) { \ + if (!_reg_ && (_fxf_ < 3)) { XOR32RtoR(GPRreg, GPRreg); } \ + else { MOV32MtoR(GPRreg, (uptr)&mVU->regs->VF[_reg_].UL[0]); } \ } diff --git a/pcsx2/x86/microVU_Analyze.inl b/pcsx2/x86/microVU_Analyze.inl index cb32980690..0422662fba 100644 --- a/pcsx2/x86/microVU_Analyze.inl +++ b/pcsx2/x86/microVU_Analyze.inl @@ -61,8 +61,7 @@ } \ } -microVUt(void) mVUanalyzeFMAC1(int Fd, int Fs, int Ft) { - microVU* mVU = mVUx; +microVUt(void) mVUanalyzeFMAC1(mV, int Fd, int Fs, int Ft) { mVUinfo |= _doStatus; analyzeReg1(Fs); analyzeReg1(Ft); @@ -73,8 +72,7 @@ microVUt(void) mVUanalyzeFMAC1(int Fd, int Fs, int Ft) { // FMAC2 - ABS/FTOI/ITOF Opcodes //------------------------------------------------------------------ -microVUt(void) mVUanalyzeFMAC2(int Fs, int Ft) { - microVU* mVU = mVUx; +microVUt(void) mVUanalyzeFMAC2(mV, int Fs, int Ft) { analyzeReg1(Fs); analyzeReg2(Ft, 0); } @@ -92,8 +90,7 @@ microVUt(void) mVUanalyzeFMAC2(int Fs, int Ft) { } \ } -microVUt(void) mVUanalyzeFMAC3(int Fd, int Fs, int Ft) { - microVU* mVU = mVUx; +microVUt(void) mVUanalyzeFMAC3(mV, int Fd, int Fs, int Ft) { mVUinfo |= _doStatus; analyzeReg1(Fs); analyzeReg3(Ft); @@ -108,8 +105,7 @@ microVUt(void) mVUanalyzeFMAC3(int Fd, int Fs, int Ft) { if (reg) { mVUstall = aMax(mVUstall, aReg(reg).w); } \ } -microVUt(void) mVUanalyzeFMAC4(int Fs, int Ft) { - microVU* mVU = mVUx; +microVUt(void) mVUanalyzeFMAC4(mV, int Fs, int Ft) { mVUinfo |= _doClip; analyzeReg1(Fs); analyzeReg4(Ft); @@ -123,16 +119,14 @@ microVUt(void) mVUanalyzeFMAC4(int Fs, int Ft) { #define analyzeVIreg2(reg, aCycles) { if (reg) { mVUregsTemp.VIreg = reg; mVUregsTemp.VI = aCycles; mVUinfo |= _writesVI; mVU->VIbackup[0] = reg; } } #define analyzeVIreg3(reg, aCycles) { if (reg) { mVUregsTemp.VIreg = reg; mVUregsTemp.VI = aCycles; } } -microVUt(void) mVUanalyzeIALU1(int Id, int Is, int It) { - microVU* mVU = mVUx; +microVUt(void) mVUanalyzeIALU1(mV, int Id, int Is, int It) { if (!Id) { mVUinfo |= _isNOP; } analyzeVIreg1(Is); analyzeVIreg1(It); analyzeVIreg2(Id, 1); } -microVUt(void) mVUanalyzeIALU2(int Is, int It) { - microVU* mVU = mVUx; +microVUt(void) mVUanalyzeIALU2(mV, int Is, int It) { if (!It) { mVUinfo |= _isNOP; } analyzeVIreg1(Is); analyzeVIreg2(It, 1); @@ -159,8 +153,7 @@ microVUt(void) mVUanalyzeIALU2(int Is, int It) { } \ } -microVUt(void) mVUanalyzeMR32(int Fs, int Ft) { - microVU* mVU = mVUx; +microVUt(void) mVUanalyzeMR32(mV, int Fs, int Ft) { if (!Ft) { mVUinfo |= _isNOP; } analyzeReg6(Fs); analyzeReg2(Ft, 1); @@ -191,8 +184,7 @@ microVUt(void) mVUanalyzeMR32(int Fs, int Ft) { #define analyzeQreg(x) { mVUregsTemp.q = x; mVUstall = aMax(mVUstall, mVUregs.q); } #define analyzePreg(x) { mVUregsTemp.p = x; mVUstall = aMax(mVUstall, ((mVUregs.p) ? (mVUregs.p - 1) : 0)); } -microVUt(void) mVUanalyzeFDIV(int Fs, int Fsf, int Ft, int Ftf, u8 xCycles) { - microVU* mVU = mVUx; +microVUt(void) mVUanalyzeFDIV(mV, int Fs, int Fsf, int Ft, int Ftf, u8 xCycles) { mVUprint("microVU: DIV Opcode"); analyzeReg5(Fs, Fsf); analyzeReg5(Ft, Ftf); @@ -203,15 +195,13 @@ microVUt(void) mVUanalyzeFDIV(int Fs, int Fsf, int Ft, int Ftf, u8 xCycles) { // EFU - EFU Opcodes //------------------------------------------------------------------ -microVUt(void) mVUanalyzeEFU1(int Fs, int Fsf, u8 xCycles) { - microVU* mVU = mVUx; +microVUt(void) mVUanalyzeEFU1(mV, int Fs, int Fsf, u8 xCycles) { mVUprint("microVU: EFU Opcode"); analyzeReg5(Fs, Fsf); analyzePreg(xCycles); } -microVUt(void) mVUanalyzeEFU2(int Fs, u8 xCycles) { - microVU* mVU = mVUx; +microVUt(void) mVUanalyzeEFU2(mV, int Fs, u8 xCycles) { mVUprint("microVU: EFU Opcode"); analyzeReg1b(Fs); analyzePreg(xCycles); @@ -221,8 +211,7 @@ microVUt(void) mVUanalyzeEFU2(int Fs, u8 xCycles) { // MFP - MFP Opcode //------------------------------------------------------------------ -microVUt(void) mVUanalyzeMFP(int Ft) { - microVU* mVU = mVUx; +microVUt(void) mVUanalyzeMFP(mV, int Ft) { if (!Ft) { mVUinfo |= _isNOP; } analyzeReg2(Ft, 1); } @@ -231,8 +220,7 @@ microVUt(void) mVUanalyzeMFP(int Ft) { // MOVE - MOVE Opcode //------------------------------------------------------------------ -microVUt(void) mVUanalyzeMOVE(int Fs, int Ft) { - microVU* mVU = mVUx; +microVUt(void) mVUanalyzeMOVE(mV, int Fs, int Ft) { if (!Ft || (Ft == Fs)) { mVUinfo |= _isNOP; } analyzeReg1b(Fs); analyzeReg2(Ft, 1); @@ -243,8 +231,7 @@ microVUt(void) mVUanalyzeMOVE(int Fs, int Ft) { // LQx - LQ/LQD/LQI Opcodes //------------------------------------------------------------------ -microVUt(void) mVUanalyzeLQ(int Ft, int Is, bool writeIs) { - microVU* mVU = mVUx; +microVUt(void) mVUanalyzeLQ(mV, int Ft, int Is, bool writeIs) { analyzeVIreg1(Is); analyzeReg2(Ft, 1); if (!Ft) { mVUinfo |= (writeIs && Is) ? _noWriteVF : _isNOP; } @@ -255,8 +242,7 @@ microVUt(void) mVUanalyzeLQ(int Ft, int Is, bool writeIs) { // SQx - SQ/SQD/SQI Opcodes //------------------------------------------------------------------ -microVUt(void) mVUanalyzeSQ(int Fs, int It, bool writeIt) { - microVU* mVU = mVUx; +microVUt(void) mVUanalyzeSQ(mV, int Fs, int It, bool writeIt) { analyzeReg1b(Fs); analyzeVIreg1(It); if (writeIt) { analyzeVIreg2(It, 1); } @@ -268,14 +254,12 @@ microVUt(void) mVUanalyzeSQ(int Fs, int It, bool writeIt) { #define analyzeRreg() { mVUregsTemp.r = 1; } -microVUt(void) mVUanalyzeR1(int Fs, int Fsf) { - microVU* mVU = mVUx; +microVUt(void) mVUanalyzeR1(mV, int Fs, int Fsf) { analyzeReg5(Fs, Fsf); analyzeRreg(); } -microVUt(void) mVUanalyzeR2(int Ft, bool canBeNOP) { - microVU* mVU = mVUx; +microVUt(void) mVUanalyzeR2(mV, int Ft, bool canBeNOP) { if (!Ft) { mVUinfo |= ((canBeNOP) ? _isNOP : _noWriteVF); } analyzeReg2(Ft, 1); analyzeRreg(); @@ -285,8 +269,7 @@ microVUt(void) mVUanalyzeR2(int Ft, bool canBeNOP) { // Sflag - Status Flag Opcodes //------------------------------------------------------------------ -microVUt(void) mVUanalyzeSflag(int It) { - microVU* mVU = mVUx; +microVUt(void) mVUanalyzeSflag(mV, int It) { if (!It) { mVUinfo |= _isNOP; } else { mVUinfo |= _swapOps; @@ -300,8 +283,7 @@ microVUt(void) mVUanalyzeSflag(int It) { analyzeVIreg3(It, 1); } -microVUt(void) mVUanalyzeFSSET() { - microVU* mVU = mVUx; +microVUt(void) mVUanalyzeFSSET(mV) { mVUinfo |= _isFSSET; // mVUinfo &= ~_doStatus; // Note: I'm not entirely sure if the non-sticky flags @@ -314,8 +296,7 @@ microVUt(void) mVUanalyzeFSSET() { // Mflag - Mac Flag Opcodes //------------------------------------------------------------------ -microVUt(void) mVUanalyzeMflag(int Is, int It) { - microVU* mVU = mVUx; +microVUt(void) mVUanalyzeMflag(mV, int Is, int It) { if (!It) { mVUinfo |= _isNOP; } else { // Need set _doMac for 4 previous Ops (need to do all 4 because stalls could change the result needed) mVUinfo |= _swapOps; @@ -335,8 +316,7 @@ microVUt(void) mVUanalyzeMflag(int Is, int It) { // Cflag - Clip Flag Opcodes //------------------------------------------------------------------ -microVUt(void) mVUanalyzeCflag(int It) { - microVU* mVU = mVUx; +microVUt(void) mVUanalyzeCflag(mV, int It) { mVUinfo |= _swapOps; if (mVUcount < 4) { mVUpBlock->pState.needExactMatch |= 0xf << (/*mVUcount +*/ 8); } analyzeVIreg3(It, 1); @@ -349,8 +329,7 @@ microVUt(void) mVUanalyzeCflag(int It) { #define analyzeXGkick1() { mVUstall = aMax(mVUstall, mVUregs.xgkick); } #define analyzeXGkick2(x) { mVUregsTemp.xgkick = x; } -microVUt(void) mVUanalyzeXGkick(int Fs, int xCycles) { - microVU* mVU = mVUx; +microVUt(void) mVUanalyzeXGkick(mV, int Fs, int xCycles) { analyzeVIreg1(Fs); analyzeXGkick1(); analyzeXGkick2(xCycles); @@ -378,14 +357,12 @@ microVUt(void) mVUanalyzeXGkick(int Fs, int xCycles) { } \ } -microVUt(void) mVUanalyzeBranch1(int Is) { - microVU* mVU = mVUx; +microVUt(void) mVUanalyzeBranch1(mV, int Is) { if (mVUregs.VI[Is] || mVUstall) { analyzeVIreg1(Is); } else { analyzeBranchVI(Is, _memReadIs); } } -microVUt(void) mVUanalyzeBranch2(int Is, int It) { - microVU* mVU = mVUx; +microVUt(void) mVUanalyzeBranch2(mV, int Is, int It) { if (mVUregs.VI[Is] || mVUregs.VI[It] || mVUstall) { analyzeVIreg1(Is); analyzeVIreg1(It); } else { analyzeBranchVI(Is, _memReadIs); analyzeBranchVI(It, _memReadIt);} } diff --git a/pcsx2/x86/microVU_Compile.inl b/pcsx2/x86/microVU_Compile.inl index c54ee08bb8..857f001f72 100644 --- a/pcsx2/x86/microVU_Compile.inl +++ b/pcsx2/x86/microVU_Compile.inl @@ -23,7 +23,7 @@ //------------------------------------------------------------------ #define branchCase(JMPcc, nJMPcc) \ - mVUsetupBranch(xStatus, xMac, xClip, xCycles); \ + mVUsetupBranch(mVU, xStatus, xMac, xClip, xCycles); \ CMP16ItoM((uptr)&mVU->branch, 0); \ incPC2(1); \ if (!mVUblocks[iPC/2]) { mVUblocks[iPC/2] = new microBlockManager(); } \ @@ -54,8 +54,8 @@ #define tCycles(dest, src) { dest = aMax(dest, src); } #define incP() { mVU->p = (mVU->p+1) & 1; } #define incQ() { mVU->q = (mVU->q+1) & 1; } -#define doUpperOp() { mVUopU(1); mVUdivSet(); } -#define doLowerOp() { incPC(-1); mVUopL(1); incPC(1); } +#define doUpperOp() { mVUopU(mVU, 1); mVUdivSet(mVU); } +#define doLowerOp() { incPC(-1); mVUopL(mVU, 1); incPC(1); } #define doIbit() { if (curI & _Ibit_) { incPC(-1); MOV32ItoM((uptr)&mVU->regs->VI[REG_I].UL, curI); incPC(1); } } //------------------------------------------------------------------ @@ -63,20 +63,19 @@ //------------------------------------------------------------------ // Used by mVUsetupRange -microVUt(void) mVUcheckIsSame() { - microVU* mVU = mVUx; +microVUt(void) mVUcheckIsSame(mV) { if (mVU->prog.isSame == -1) { mVU->prog.isSame = !memcmp_mmx(mVU->prog.prog[mVU->prog.cur].data, mVU->regs->Micro, mVU->microSize); } if (mVU->prog.isSame == 0) { - mVUcacheProg(mVU->prog.cur); + if (!isVU1) mVUcacheProg<0>(mVU->prog.cur); + else mVUcacheProg<1>(mVU->prog.cur); } } // Sets up microProgram PC ranges based on whats been recompiled -microVUt(void) mVUsetupRange(u32 pc) { - microVU* mVU = mVUx; +microVUt(void) mVUsetupRange(mV, u32 pc) { if (mVUcurProg.range[0] == -1) { mVUcurProg.range[0] = (s32)pc; @@ -84,28 +83,26 @@ microVUt(void) mVUsetupRange(u32 pc) { } else if (mVUcurProg.range[0] > (s32)pc) { mVUcurProg.range[0] = (s32)pc; - mVUcheckIsSame(); + mVUcheckIsSame(mVU); } else if (mVUcurProg.range[1] < (s32)pc) { mVUcurProg.range[1] = (s32)pc; - mVUcheckIsSame(); + mVUcheckIsSame(mVU); } } // Recompiles Code for Proper Flags and Q/P regs on Block Linkings -microVUt(void) mVUsetupBranch(int* xStatus, int* xMac, int* xClip, int xCycles) { - microVU* mVU = mVUx; +microVUt(void) mVUsetupBranch(mV, int* xStatus, int* xMac, int* xClip, int xCycles) { mVUprint("mVUsetupBranch"); // Shuffle Flag Instances - mVUsetupFlags(xStatus, xMac, xClip, xCycles); + mVUsetupFlags(mVU, xStatus, xMac, xClip, xCycles); // Shuffle P/Q regs since every block starts at instance #0 if (mVU->p || mVU->q) { SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, shufflePQ); } } -microVUt(void) mVUincCycles(int x) { - microVU* mVU = mVUx; +microVUt(void) mVUincCycles(mV, int x) { mVUcycles += x; for (int z = 31; z > 0; z--) { calcCycles(mVUregs.VF[z].x, x); @@ -132,8 +129,7 @@ microVUt(void) mVUincCycles(int x) { calcCycles(mVUregs.r, x); } -microVUt(void) mVUsetCycles() { - microVU* mVU = mVUx; +microVUt(void) mVUsetCycles(mV) { incCycles(mVUstall); if (mVUregsTemp.VFreg[0] == mVUregsTemp.VFreg[1] && mVUregsTemp.VFreg[0]) { // If upper Op && lower Op write to same VF reg mVUinfo |= (mVUregsTemp.r || mVUregsTemp.VI) ? _noWriteVF : _isNOP; // If lower Op doesn't modify anything else, then make it a NOP @@ -155,13 +151,12 @@ microVUt(void) mVUsetCycles() { tCycles(mVUregs.xgkick, mVUregsTemp.xgkick); } -microVUt(void) mVUendProgram(int qInst, int pInst, int fStatus, int fMac, int fClip) { - microVU* mVU = mVUx; +microVUt(void) mVUendProgram(mV, int qInst, int pInst, int fStatus, int fMac, int fClip) { // Save P/Q Regs if (qInst) { SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, 0xe5); } SSE_MOVSS_XMM_to_M32((uptr)&mVU->regs->VI[REG_Q].UL, xmmPQ); - if (vuIndex) { + if (isVU1) { SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, pInst ? 3 : 2); SSE_MOVSS_XMM_to_M32((uptr)&mVU->regs->VI[REG_P].UL, xmmPQ); } @@ -171,13 +166,13 @@ microVUt(void) mVUendProgram(int qInst, int pInst, int fStatus, int fMac, int fC getFlagReg(fStatus, fStatus); MOV32RtoM((uptr)&mVU->regs->VI[REG_STATUS_FLAG].UL, fStatus); } - mVUallocMFLAGa(gprT1, fMac); - mVUallocCFLAGa(gprT2, fClip); + mVUallocMFLAGa(mVU, gprT1, fMac); + mVUallocCFLAGa(mVU, gprT2, fClip); MOV32RtoM((uptr)&mVU->regs->VI[REG_MAC_FLAG].UL, gprT1); MOV32RtoM((uptr)&mVU->regs->VI[REG_CLIP_FLAG].UL, gprT2); // Clear 'is busy' Flags, Save PC, and Jump to Exit Point - AND32ItoM((uptr)&VU0.VI[REG_VPU_STAT].UL, (vuIndex ? ~0x100 : ~0x001)); // VBS0/VBS1 flag + AND32ItoM((uptr)&VU0.VI[REG_VPU_STAT].UL, (isVU1 ? ~0x100 : ~0x001)); // VBS0/VBS1 flag AND32ItoM((uptr)&mVU->regs->vifRegs->stat, ~0x4); // Clear VU 'is busy' signal for vif MOV32ItoM((uptr)&mVU->regs->VI[REG_TPC].UL, xPC); JMP32((uptr)mVU->exitFunct - ((uptr)x86Ptr + 5)); @@ -191,17 +186,16 @@ void __fastcall mVUwarning1(u32 PC) { Console::Error("microVU1 Warning: Exiting void __fastcall mVUprintPC1(u32 PC) { Console::Write("Block PC [%04x] ", params PC); } void __fastcall mVUprintPC2(u32 PC) { Console::Write("[%04x]\n", params PC); } -microVUt(void) mVUtestCycles() { - microVU* mVU = mVUx; +microVUt(void) mVUtestCycles(mV) { iPC = mVUstartPC; mVUdebugNOW(0); SUB32ItoM((uptr)&mVU->cycles, mVUcycles); u8* jmp8 = JG8(0); MOV32ItoR(gprT2, xPC); - if (!vuIndex) CALLFunc((uptr)mVUwarning0); - else CALLFunc((uptr)mVUwarning1); + if (!isVU1) CALLFunc((uptr)mVUwarning0); + else CALLFunc((uptr)mVUwarning1); MOV32ItoR(gprR, Roffset); // Restore gprR - mVUendProgram(0, 0, sI, 0, cI); + mVUendProgram(mVU, 0, 0, sI, 0, cI); x86SetJ8(jmp8); } @@ -209,7 +203,7 @@ microVUt(void) mVUtestCycles() { // Recompiler //------------------------------------------------------------------ -microVUt(void*) __fastcall mVUcompile(u32 startPC, uptr pState) { +microVUf(void*) __fastcall mVUcompile(u32 startPC, uptr pState) { microVU* mVU = mVUx; u8* thisPtr = x86Ptr; @@ -225,7 +219,7 @@ microVUt(void*) __fastcall mVUcompile(u32 startPC, uptr pState) { if (pBlock) { return pBlock->x86ptrStart; } // Setup Program Bounds/Range - mVUsetupRange(startPC); + mVUsetupRange(mVU, startPC); // First Pass iPC = startPC / 4; @@ -250,25 +244,25 @@ microVUt(void*) __fastcall mVUcompile(u32 startPC, uptr pState) { mVUinfo = 0; startLoop(); incCycles(1); - mVUopU(0); + mVUopU(mVU, 0); if (curI & _Ebit_) { branch = 1; } if (curI & _MDTbit_) { branch = 4; } if (curI & _Ibit_) { mVUinfo |= _isNOP; } - else { incPC(-1); mVUopL(0); incPC(1); } - mVUsetCycles(); + else { incPC(-1); mVUopL(mVU, 0); incPC(1); } + mVUsetCycles(mVU); if (mVU->p) { mVUinfo |= _readP; } if (mVU->q) { mVUinfo |= _readQ; } if (branch >= 2) { mVUinfo |= _isEOB | ((branch == 3) ? _isBdelay : 0); mVUcount++; branchWarning(); break; } else if (branch == 1) { branch = 2; } - if (mVUbranch) { mVUsetFlagInfo(); branchEbit(); branch = 3; mVUbranch = 0; mVUinfo |= _isBranch; } + if (mVUbranch) { mVUsetFlagInfo(mVU); branchEbit(); branch = 3; mVUbranch = 0; mVUinfo |= _isBranch; } incPC(1); mVUcount++; } // Sets Up Flag instances int xStatus[4], xMac[4], xClip[4]; - int xCycles = mVUsetFlags(xStatus, xMac, xClip); - mVUtestCycles(); + int xCycles = mVUsetFlags(mVU, xStatus, xMac, xClip); + mVUtestCycles(mVU); // Second Pass iPC = mVUstartPC; @@ -279,14 +273,14 @@ microVUt(void*) __fastcall mVUcompile(u32 startPC, uptr pState) { if (isEOB) { x = 0xffff; } if (isNOP) { incPC(1); doUpperOp(); doIbit(); } else if (!swapOps) { incPC(1); doUpperOp(); doLowerOp(); } - else { mVUopL(1); incPC(1); doUpperOp(); } - if (doXGKICK) { mVU_XGKICK_DELAY(); } + else { mVUopL(mVU, 1); incPC(1); doUpperOp(); } + if (doXGKICK) { mVU_XGKICK_DELAY(mVU); } if (!isBdelay) { incPC(1); } else { microBlock* bBlock = NULL; u32* ajmp = 0; - mVUsetupRange(xPC); + mVUsetupRange(mVU, xPC); mVUdebugNOW(1); switch (mVUbranch) { @@ -302,7 +296,7 @@ microVUt(void*) __fastcall mVUcompile(u32 startPC, uptr pState) { incPC(-3); // Go back to branch opcode (to get branch imm addr) if (eBitBranch) { iPC = branchAddr/4; goto eBitTemination; } // E-bit Was Set on Branch - mVUsetupBranch(xStatus, xMac, xClip, xCycles); + mVUsetupBranch(mVU, xStatus, xMac, xClip, xCycles); if (mVUblocks[branchAddr/8] == NULL) mVUblocks[branchAddr/8] = new microBlockManager(); @@ -317,15 +311,15 @@ microVUt(void*) __fastcall mVUcompile(u32 startPC, uptr pState) { mVUprint("mVUcompile JR/JALR"); memcpy_fast(&pBlock->pStateEnd, &mVUregs, sizeof(microRegInfo)); - mVUsetupBranch(xStatus, xMac, xClip, xCycles); + mVUsetupBranch(mVU, xStatus, xMac, xClip, xCycles); - mVUbackupRegs(); + mVUbackupRegs(mVU); MOV32MtoR(gprT2, (uptr)&mVU->branch); // Get startPC (ECX first argument for __fastcall) MOV32ItoR(gprR, (u32)&pBlock->pStateEnd); // Get pState (EDX second argument for __fastcall) - if (!vuIndex) CALLFunc((uptr)mVUcompileVU0); //(u32 startPC, uptr pState) - else CALLFunc((uptr)mVUcompileVU1); - mVUrestoreRegs(); + if (!isVU1) CALLFunc((uptr)mVUcompileVU0); //(u32 startPC, uptr pState) + else CALLFunc((uptr)mVUcompileVU1); + mVUrestoreRegs(mVU); JMPR(gprT1); // Jump to rec-code address return thisPtr; } @@ -380,11 +374,11 @@ eBitTemination: AND32ItoR (flagReg, 0x0fcf); OR32MtoR (flagReg, (uptr)&mVU->divFlag); } - if (doXGKICK) { mVU_XGKICK_DELAY(); } + if (doXGKICK) { mVU_XGKICK_DELAY(mVU); } // Do E-bit end stuff here - mVUsetupRange(xPC - 8); - mVUendProgram(mVU->q, mVU->p, lStatus, lMac, lClip); + mVUsetupRange(mVU, xPC - 8); + mVUendProgram(mVU, mVU->q, mVU->p, lStatus, lMac, lClip); return thisPtr; } diff --git a/pcsx2/x86/microVU_Execute.inl b/pcsx2/x86/microVU_Execute.inl index 456dcb8003..0854b0bad3 100644 --- a/pcsx2/x86/microVU_Execute.inl +++ b/pcsx2/x86/microVU_Execute.inl @@ -23,13 +23,12 @@ //------------------------------------------------------------------ // Generates the code for entering recompiled blocks -microVUt(void) mVUdispatcherA() { - microVU* mVU = mVUx; +microVUt(void) mVUdispatcherA(mV) { mVU->startFunct = x86Ptr; // __fastcall = The first two DWORD or smaller arguments are passed in ECX and EDX registers; all other arguments are passed right to left. - if (!vuIndex) { CALLFunc((uptr)mVUexecuteVU0); } - else { CALLFunc((uptr)mVUexecuteVU1); } + if (!isVU1) { CALLFunc((uptr)mVUexecuteVU0); } + else { CALLFunc((uptr)mVUexecuteVU1); } // Backup cpu state PUSH32R(EBX); @@ -72,8 +71,7 @@ microVUt(void) mVUdispatcherA() { } // Generates the code to exit from recompiled blocks -microVUt(void) mVUdispatcherB() { - microVU* mVU = mVUx; +microVUt(void) mVUdispatcherB(mV) { mVU->exitFunct = x86Ptr; // Load EE's MXCSR state @@ -87,8 +85,8 @@ microVUt(void) mVUdispatcherB() { } // __fastcall = The first two DWORD or smaller arguments are passed in ECX and EDX registers; all other arguments are passed right to left. - if (!vuIndex) { CALLFunc((uptr)mVUcleanUpVU0); } - else { CALLFunc((uptr)mVUcleanUpVU1); } + if (!isVU1) { CALLFunc((uptr)mVUcleanUpVU0); } + else { CALLFunc((uptr)mVUcleanUpVU1); } // Restore cpu state POP32R(EDI); @@ -107,7 +105,7 @@ microVUt(void) mVUdispatcherB() { //------------------------------------------------------------------ // Executes for number of cycles -microVUt(void*) __fastcall mVUexecute(u32 startPC, u32 cycles) { +microVUx(void*) __fastcall mVUexecute(u32 startPC, u32 cycles) { microVU* mVU = mVUx; //mVUprint("microVU%x: startPC = 0x%x, cycles = 0x%x", params vuIndex, startPC, cycles); @@ -125,7 +123,7 @@ microVUt(void*) __fastcall mVUexecute(u32 startPC, u32 cycles) { // Cleanup Functions //------------------------------------------------------------------ -microVUt(void) mVUcleanUp() { +microVUx(void) mVUcleanUp() { microVU* mVU = mVUx; //mVUprint("microVU: Program exited successfully!"); //mVUprint("microVU: VF0 = {%x,%x,%x,%x}", params mVU->regs->VF[0].UL[0], mVU->regs->VF[0].UL[1], mVU->regs->VF[0].UL[2], mVU->regs->VF[0].UL[3]); diff --git a/pcsx2/x86/microVU_Flags.inl b/pcsx2/x86/microVU_Flags.inl index 3097d6c87b..09569e9240 100644 --- a/pcsx2/x86/microVU_Flags.inl +++ b/pcsx2/x86/microVU_Flags.inl @@ -19,8 +19,7 @@ #pragma once // Sets FDIV Flags at the proper time -microVUt(void) mVUdivSet() { - microVU* mVU = mVUx; +microVUt(void) mVUdivSet(mV) { int flagReg1, flagReg2; if (doDivFlag) { getFlagReg(flagReg1, fsInstance); @@ -31,8 +30,7 @@ microVUt(void) mVUdivSet() { } // Optimizes out unneeded status flag updates -microVUt(void) mVUstatusFlagOp() { - microVU* mVU = mVUx; +microVUt(void) mVUstatusFlagOp(mV) { int curPC = iPC; int i = mVUcount; bool runLoop = 1; @@ -52,7 +50,7 @@ microVUt(void) mVUstatusFlagOp() { } } iPC = curPC; - DevCon::Status("microVU%d: FSSET Optimization", params vuIndex); + DevCon::Status("microVU%d: FSSET Optimization", params getIndex); } int findFlagInst(int* fFlag, int cycles) { @@ -74,8 +72,7 @@ void sortFlag(int* fFlag, int* bFlag, int cycles) { #define sFlagCond ((doStatus && !mVUsFlagHack) || isFSSET || doDivFlag) // Note: Flag handling is 'very' complex, it requires full knowledge of how microVU recs work, so don't touch! -microVUt(int) mVUsetFlags(int* xStatus, int* xMac, int* xClip) { - microVU* mVU = mVUx; +microVUt(int) mVUsetFlags(mV, int* xStatus, int* xMac, int* xClip) { int endPC = iPC; u32 aCount = 1; // Amount of instructions needed to get valid mac flag instances for block linking @@ -120,9 +117,9 @@ microVUt(int) mVUsetFlags(int* xStatus, int* xMac, int* xClip) { for (mVUcount = 0; mVUcount < xCount; mVUcount++) { if (isFSSET) { if (__Status) { // Don't Optimize out on the last ~4+ instructions - if ((xCount - mVUcount) > aCount) { mVUstatusFlagOp(); } + if ((xCount - mVUcount) > aCount) { mVUstatusFlagOp(mVU); } } - else mVUstatusFlagOp(); + else mVUstatusFlagOp(mVU); } cycles += mVUstall; @@ -151,8 +148,7 @@ microVUt(int) mVUsetFlags(int* xStatus, int* xMac, int* xClip) { #define shuffleClip ((bClip[3]<<6)|(bClip[2]<<4)|(bClip[1]<<2)|bClip[0]) // Recompiles Code for Proper Flags on Block Linkings -microVUt(void) mVUsetupFlags(int* xStatus, int* xMac, int* xClip, int cycles) { - microVU* mVU = mVUx; +microVUt(void) mVUsetupFlags(mV, int* xStatus, int* xMac, int* xClip, int cycles) { if (__Status && !mVUflagHack) { int bStatus[4]; @@ -184,17 +180,16 @@ microVUt(void) mVUsetupFlags(int* xStatus, int* xMac, int* xClip, int cycles) { } } -#define shortBranch() { \ - if (branch == 3) { \ - mVUflagPass(aBranchAddr, (xCount - (mVUcount+1))); \ - mVUcount = 4; \ - } \ +#define shortBranch() { \ + if (branch == 3) { \ + mVUflagPass(mVU, aBranchAddr, (xCount - (mVUcount+1))); \ + mVUcount = 4; \ + } \ } // Scan through instructions and check if flags are read (FSxxx, FMxxx, FCxxx opcodes) -microVUx(void) mVUflagPass(u32 startPC, u32 xCount) { +void mVUflagPass(mV, u32 startPC, u32 xCount) { - microVU* mVU = mVUx; int oldPC = iPC; int oldCount = mVUcount; int oldBranch = mVUbranch; @@ -206,7 +201,7 @@ microVUx(void) mVUflagPass(u32 startPC, u32 xCount) { incPC(1); if ( curI & _Ebit_ ) { branch = 1; } if ( curI & _MDTbit_ ) { branch = 4; } - if (!(curI & _Ibit_) ) { incPC(-1); mVUopL(3); incPC(1); } + if (!(curI & _Ibit_) ) { incPC(-1); mVUopL(mVU, 3); incPC(1); } if (branch >= 2) { shortBranch(); break; } else if (branch == 1) { branch = 2; } if (mVUbranch) { branch = (mVUbranch >= 9) ? 5 : 3; aBranchAddr = branchAddr; mVUbranch = 0; } @@ -224,17 +219,16 @@ microVUx(void) mVUflagPass(u32 startPC, u32 xCount) { #define branchType3 else // Conditional Branch // Checks if the first 4 instructions of a block will read flags -microVUt(void) mVUsetFlagInfo() { - microVU* mVU = mVUx; - branchType1 { incPC(-1); mVUflagPass(branchAddr, 4); incPC(1); } +microVUt(void) mVUsetFlagInfo(mV) { + branchType1 { incPC(-1); mVUflagPass(mVU, branchAddr, 4); incPC(1); } branchType2 { mVUflagInfo |= 0xfff; } branchType3 { incPC(-1); - mVUflagPass(branchAddr, 4); + mVUflagPass(mVU, branchAddr, 4); int backupFlagInfo = mVUflagInfo; mVUflagInfo = 0; incPC(4); // Branch Not Taken - mVUflagPass(xPC, 4); + mVUflagPass(mVU, xPC, 4); incPC(-3); mVUflagInfo |= backupFlagInfo; } diff --git a/pcsx2/x86/microVU_Log.inl b/pcsx2/x86/microVU_Log.inl index bdbda985a1..9e5451a8fd 100644 --- a/pcsx2/x86/microVU_Log.inl +++ b/pcsx2/x86/microVU_Log.inl @@ -38,7 +38,7 @@ microVUx(void) __mVULog(const char* fmt, ...) { #define commaIf() { if (bitX[6]) { mVUlog(","); bitX[6] = 0; } } -microVUt(void) __mVUdumpProgram(int progIndex) { +microVUx(void) __mVUdumpProgram(int progIndex) { microVU* mVU = mVUx; bool bitX[7]; char str[30]; @@ -46,6 +46,7 @@ microVUt(void) __mVUdumpProgram(int progIndex) { int bBranch = mVUbranch; int bCode = mVU->code; int bPC = iPC; + int vuIndex = (mVU == µVU1) ? 1 : 0; mVUbranch = 0; sprintf(str, "%s\\microVU%d prog - %02d.html", LOGS_DIR, vuIndex, progIndex); @@ -88,7 +89,7 @@ microVUt(void) __mVUdumpProgram(int progIndex) { iPC = (i+1); mVUlog("", i*4); mVUlog("[%04x] (%08x) ", i*4, mVU->code); - mVUopU(); + mVUopU(mVU, 2); if (bitX[5]) { mVUlog(" ("); @@ -110,7 +111,7 @@ microVUt(void) __mVUdumpProgram(int progIndex) { } else { mVUlog("
\n[%04x] (%08x) ", i*4, mVU->code); - mVUopL(); + mVUopL(mVU, 2); mVUlog("\n\n

"); } } diff --git a/pcsx2/x86/microVU_Lower.inl b/pcsx2/x86/microVU_Lower.inl index 85bc94dce3..7da82eec97 100644 --- a/pcsx2/x86/microVU_Lower.inl +++ b/pcsx2/x86/microVU_Lower.inl @@ -42,9 +42,8 @@ x86SetJ8(aJump); \ } -microVUf(void) mVU_DIV(mF) { - microVU* mVU = mVUx; - pass1 { mVUanalyzeFDIV(_Fs_, _Fsf_, _Ft_, _Ftf_, 7); } +mVUop(mVU_DIV) { + pass1 { mVUanalyzeFDIV(mVU, _Fs_, _Fsf_, _Ft_, _Ftf_, 7); } pass2 { u8 *ajmp, *bjmp, *cjmp, *djmp; getReg5(xmmFs, _Fs_, _Fsf_); @@ -69,7 +68,7 @@ microVUf(void) mVU_DIV(mF) { x86SetJ8(cjmp); MOV32ItoM((uptr)&mVU->divFlag, 0); // Clear I/D flags SSE_DIVSS_XMM_to_XMM(xmmFs, xmmFt); - if (CHECK_VU_OVERFLOW) mVUclamp1(xmmFs, xmmFt, 8); + if (CHECK_VU_OVERFLOW) mVUclamp1(xmmFs, xmmFt, 8); x86SetJ8(djmp); if (writeQ) SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, 0xe1); @@ -79,9 +78,8 @@ microVUf(void) mVU_DIV(mF) { pass3 { mVUlog("DIV Q, vf%02d%s, vf%02d%s", _Fs_, _Fsf_String, _Ft_, _Ftf_String); } } -microVUf(void) mVU_SQRT(mF) { - microVU* mVU = mVUx; - pass1 { mVUanalyzeFDIV(0, 0, _Ft_, _Ftf_, 7); } +mVUop(mVU_SQRT) { + pass1 { mVUanalyzeFDIV(mVU, 0, 0, _Ft_, _Ftf_, 7); } pass2 { u8 *ajmp; getReg5(xmmFt, _Ft_, _Ftf_); @@ -98,9 +96,8 @@ microVUf(void) mVU_SQRT(mF) { pass3 { mVUlog("SQRT Q, vf%02d%s", _Ft_, _Ftf_String); } } -microVUf(void) mVU_RSQRT(mF) { - microVU* mVU = mVUx; - pass1 { mVUanalyzeFDIV(_Fs_, _Fsf_, _Ft_, _Ftf_, 13); } +mVUop(mVU_RSQRT) { + pass1 { mVUanalyzeFDIV(mVU, _Fs_, _Fsf_, _Ft_, _Ftf_, 13); } pass2 { u8 *ajmp, *bjmp, *cjmp, *djmp; getReg5(xmmFs, _Fs_, _Fsf_); @@ -127,7 +124,7 @@ microVUf(void) mVU_RSQRT(mF) { djmp = JMP8(0); x86SetJ8(ajmp); SSE_DIVSS_XMM_to_XMM(xmmFs, xmmFt); - if (CHECK_VU_OVERFLOW) mVUclamp1(xmmFs, xmmFt, 8); + if (CHECK_VU_OVERFLOW) mVUclamp1(xmmFs, xmmFt, 8); x86SetJ8(djmp); if (writeQ) SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, 0xe1); @@ -149,8 +146,7 @@ microVUf(void) mVU_RSQRT(mF) { SSE_ADDSS_XMM_to_XMM(xmmPQ, xmmFt); \ } -microVUt(void) mVU_EATAN_() { - microVU* mVU = mVUx; +microVUt(void) mVU_EATAN_(mV) { // ToDo: Can Be Optimized Further? (takes approximately (~115 cycles + mem access time) on a c2d) SSE_MOVSS_XMM_to_XMM(xmmPQ, xmmFs); @@ -169,9 +165,8 @@ microVUt(void) mVU_EATAN_() { SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, writeP ? 0x27 : 0xC6); } -microVUf(void) mVU_EATAN(mF) { - microVU* mVU = mVUx; - pass1 { mVUanalyzeEFU1(_Fs_, _Fsf_, 54); } +mVUop(mVU_EATAN) { + pass1 { mVUanalyzeEFU1(mVU, _Fs_, _Fsf_, 54); } pass2 { getReg5(xmmFs, _Fs_, _Fsf_); SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, writeP ? 0x27 : 0xC6); // Flip xmmPQ to get Valid P instance @@ -181,14 +176,13 @@ microVUf(void) mVU_EATAN(mF) { SSE_ADDSS_M32_to_XMM(xmmPQ, (uptr)mVU_one); SSE_DIVSS_XMM_to_XMM(xmmFs, xmmPQ); - mVU_EATAN_(); + mVU_EATAN_(mVU); } pass3 { mVUlog("EATAN P"); } } -microVUf(void) mVU_EATANxy(mF) { - microVU* mVU = mVUx; - pass1 { mVUanalyzeEFU2(_Fs_, 54); } +mVUop(mVU_EATANxy) { + pass1 { mVUanalyzeEFU2(mVU, _Fs_, 54); } pass2 { getReg6(xmmFt, _Fs_); SSE2_PSHUFD_XMM_to_XMM(xmmFs, xmmFt, 0x01); @@ -199,14 +193,13 @@ microVUf(void) mVU_EATANxy(mF) { SSE_ADDSS_XMM_to_XMM(xmmFt, xmmPQ); SSE_DIVSS_XMM_to_XMM(xmmFs, xmmFt); - mVU_EATAN_(); + mVU_EATAN_(mVU); } pass3 { mVUlog("EATANxy P"); } } -microVUf(void) mVU_EATANxz(mF) { - microVU* mVU = mVUx; - pass1 { mVUanalyzeEFU2(_Fs_, 54); } +mVUop(mVU_EATANxz) { + pass1 { mVUanalyzeEFU2(mVU, _Fs_, 54); } pass2 { getReg6(xmmFt, _Fs_); SSE2_PSHUFD_XMM_to_XMM(xmmFs, xmmFt, 0x02); @@ -217,7 +210,7 @@ microVUf(void) mVU_EATANxz(mF) { SSE_ADDSS_XMM_to_XMM(xmmFt, xmmPQ); SSE_DIVSS_XMM_to_XMM(xmmFs, xmmFt); - mVU_EATAN_(); + mVU_EATAN_(mVU); } pass3 { mVUlog("EATANxz P"); } } @@ -229,9 +222,8 @@ microVUf(void) mVU_EATANxz(mF) { SSE_ADDSS_XMM_to_XMM(xmmPQ, xmmFt); \ } -microVUf(void) mVU_EEXP(mF) { - microVU* mVU = mVUx; - pass1 { mVUanalyzeEFU1(_Fs_, _Fsf_, 44); } +mVUop(mVU_EEXP) { + pass1 { mVUanalyzeEFU1(mVU, _Fs_, _Fsf_, 44); } pass2 { getReg5(xmmFs, _Fs_, _Fsf_); SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, writeP ? 0x27 : 0xC6); // Flip xmmPQ to get Valid P instance @@ -278,22 +270,20 @@ microVUt(void) mVU_sumXYZ() { } } -microVUf(void) mVU_ELENG(mF) { - microVU* mVU = mVUx; - pass1 { mVUanalyzeEFU2(_Fs_, 18); } +mVUop(mVU_ELENG) { + pass1 { mVUanalyzeEFU2(mVU, _Fs_, 18); } pass2 { getReg6(xmmFs, _Fs_); SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, writeP ? 0x27 : 0xC6); // Flip xmmPQ to get Valid P instance - mVU_sumXYZ(); + mVU_sumXYZ(); SSE_SQRTSS_XMM_to_XMM(xmmPQ, xmmPQ); SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, writeP ? 0x27 : 0xC6); // Flip back } pass3 { mVUlog("ELENG P"); } } -microVUf(void) mVU_ERCPR(mF) { - microVU* mVU = mVUx; - pass1 { mVUanalyzeEFU1(_Fs_, _Fsf_, 12); } +mVUop(mVU_ERCPR) { + pass1 { mVUanalyzeEFU1(mVU, _Fs_, _Fsf_, 12); } pass2 { getReg5(xmmFs, _Fs_, _Fsf_); SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, writeP ? 0x27 : 0xC6); // Flip xmmPQ to get Valid P instance @@ -306,13 +296,12 @@ microVUf(void) mVU_ERCPR(mF) { pass3 { mVUlog("ERCPR P"); } } -microVUf(void) mVU_ERLENG(mF) { - microVU* mVU = mVUx; - pass1 { mVUanalyzeEFU2(_Fs_, 24); } +mVUop(mVU_ERLENG) { + pass1 { mVUanalyzeEFU2(mVU, _Fs_, 24); } pass2 { getReg6(xmmFs, _Fs_); SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, writeP ? 0x27 : 0xC6); // Flip xmmPQ to get Valid P instance - mVU_sumXYZ(); + mVU_sumXYZ(); SSE_SQRTSS_XMM_to_XMM(xmmPQ, xmmPQ); SSE_MOVSS_M32_to_XMM(xmmFs, (uptr)mVU_one); SSE_DIVSS_XMM_to_XMM(xmmFs, xmmPQ); @@ -322,13 +311,12 @@ microVUf(void) mVU_ERLENG(mF) { pass3 { mVUlog("ERLENG P"); } } -microVUf(void) mVU_ERSADD(mF) { - microVU* mVU = mVUx; - pass1 { mVUanalyzeEFU2(_Fs_, 18); } +mVUop(mVU_ERSADD) { + pass1 { mVUanalyzeEFU2(mVU, _Fs_, 18); } pass2 { getReg6(xmmFs, _Fs_); SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, writeP ? 0x27 : 0xC6); // Flip xmmPQ to get Valid P instance - mVU_sumXYZ(); + mVU_sumXYZ(); //SSE_RCPSS_XMM_to_XMM(xmmPQ, xmmPQ); // Lower Precision is bad? SSE_MOVSS_M32_to_XMM(xmmFs, (uptr)mVU_one); SSE_DIVSS_XMM_to_XMM(xmmFs, xmmPQ); @@ -338,9 +326,8 @@ microVUf(void) mVU_ERSADD(mF) { pass3 { mVUlog("ERSADD P"); } } -microVUf(void) mVU_ERSQRT(mF) { - microVU* mVU = mVUx; - pass1 { mVUanalyzeEFU1(_Fs_, _Fsf_, 18); } +mVUop(mVU_ERSQRT) { + pass1 { mVUanalyzeEFU1(mVU, _Fs_, _Fsf_, 18); } pass2 { getReg5(xmmFs, _Fs_, _Fsf_); SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, writeP ? 0x27 : 0xC6); // Flip xmmPQ to get Valid P instance @@ -353,13 +340,12 @@ microVUf(void) mVU_ERSQRT(mF) { pass3 { mVUlog("ERSQRT P"); } } -microVUf(void) mVU_ESADD(mF) { - microVU* mVU = mVUx; - pass1 { mVUanalyzeEFU2(_Fs_, 11); } +mVUop(mVU_ESADD) { + pass1 { mVUanalyzeEFU2(mVU, _Fs_, 11); } pass2 { getReg6(xmmFs, _Fs_); SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, writeP ? 0x27 : 0xC6); // Flip xmmPQ to get Valid P instance - mVU_sumXYZ(); + mVU_sumXYZ(); SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, writeP ? 0x27 : 0xC6); // Flip back } pass3 { mVUlog("ESADD P"); } @@ -372,9 +358,8 @@ microVUf(void) mVU_ESADD(mF) { SSE_ADDSS_XMM_to_XMM(xmmPQ, xmmFs); \ } -microVUf(void) mVU_ESIN(mF) { - microVU* mVU = mVUx; - pass1 { mVUanalyzeEFU2(_Fs_, 29); } +mVUop(mVU_ESIN) { + pass1 { mVUanalyzeEFU2(mVU, _Fs_, 29); } pass2 { getReg5(xmmFs, _Fs_, _Fsf_); SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, writeP ? 0x27 : 0xC6); // Flip xmmPQ to get Valid P instance @@ -399,9 +384,8 @@ microVUf(void) mVU_ESIN(mF) { pass3 { mVUlog("ESIN P"); } } -microVUf(void) mVU_ESQRT(mF) { - microVU* mVU = mVUx; - pass1 { mVUanalyzeEFU1(_Fs_, _Fsf_, 12); } +mVUop(mVU_ESQRT) { + pass1 { mVUanalyzeEFU1(mVU, _Fs_, _Fsf_, 12); } pass2 { getReg5(xmmFs, _Fs_, _Fsf_); SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, writeP ? 0x27 : 0xC6); // Flip xmmPQ to get Valid P instance @@ -411,9 +395,8 @@ microVUf(void) mVU_ESQRT(mF) { pass3 { mVUlog("ESQRT P"); } } -microVUf(void) mVU_ESUM(mF) { - microVU* mVU = mVUx; - pass1 { mVUanalyzeEFU2(_Fs_, 12); } +mVUop(mVU_ESUM) { + pass1 { mVUanalyzeEFU2(mVU, _Fs_, 12); } pass2 { getReg6(xmmFs, _Fs_); SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, writeP ? 0x27 : 0xC6); // Flip xmmPQ to get Valid P instance @@ -431,66 +414,61 @@ microVUf(void) mVU_ESUM(mF) { // FCAND/FCEQ/FCGET/FCOR/FCSET //------------------------------------------------------------------ -microVUf(void) mVU_FCAND(mF) { - microVU* mVU = mVUx; - pass1 { mVUanalyzeCflag(1); } +mVUop(mVU_FCAND) { + pass1 { mVUanalyzeCflag(mVU, 1); } pass2 { - mVUallocCFLAGa(gprT1, fvcInstance); + mVUallocCFLAGa(mVU, gprT1, fvcInstance); AND32ItoR(gprT1, _Imm24_); ADD32ItoR(gprT1, 0xffffff); SHR32ItoR(gprT1, 24); - mVUallocVIb(gprT1, 1); + mVUallocVIb(mVU, gprT1, 1); } pass3 { mVUlog("FCAND vi01, $%x", _Imm24_); } pass4 { mVUflagInfo |= 0xf << (/*mVUcount +*/ 8); } } -microVUf(void) mVU_FCEQ(mF) { - microVU* mVU = mVUx; - pass1 { mVUanalyzeCflag(1); } +mVUop(mVU_FCEQ) { + pass1 { mVUanalyzeCflag(mVU, 1); } pass2 { - mVUallocCFLAGa(gprT1, fvcInstance); + mVUallocCFLAGa(mVU, gprT1, fvcInstance); XOR32ItoR(gprT1, _Imm24_); SUB32ItoR(gprT1, 1); SHR32ItoR(gprT1, 31); - mVUallocVIb(gprT1, 1); + mVUallocVIb(mVU, gprT1, 1); } pass3 { mVUlog("FCEQ vi01, $%x", _Imm24_); } pass4 { mVUflagInfo |= 0xf << (/*mVUcount +*/ 8); } } -microVUf(void) mVU_FCGET(mF) { - microVU* mVU = mVUx; - pass1 { mVUanalyzeCflag(_It_); } +mVUop(mVU_FCGET) { + pass1 { mVUanalyzeCflag(mVU, _It_); } pass2 { - mVUallocCFLAGa(gprT1, fvcInstance); + mVUallocCFLAGa(mVU, gprT1, fvcInstance); AND32ItoR(gprT1, 0xfff); - mVUallocVIb(gprT1, _It_); + mVUallocVIb(mVU, gprT1, _It_); } pass3 { mVUlog("FCGET vi%02d", _Ft_); } pass4 { mVUflagInfo |= 0xf << (/*mVUcount +*/ 8); } } -microVUf(void) mVU_FCOR(mF) { - microVU* mVU = mVUx; - pass1 { mVUanalyzeCflag(1); } +mVUop(mVU_FCOR) { + pass1 { mVUanalyzeCflag(mVU, 1); } pass2 { - mVUallocCFLAGa(gprT1, fvcInstance); + mVUallocCFLAGa(mVU, gprT1, fvcInstance); OR32ItoR(gprT1, _Imm24_); ADD32ItoR(gprT1, 1); // If 24 1's will make 25th bit 1, else 0 SHR32ItoR(gprT1, 24); // Get the 25th bit (also clears the rest of the garbage in the reg) - mVUallocVIb(gprT1, 1); + mVUallocVIb(mVU, gprT1, 1); } pass3 { mVUlog("FCOR vi01, $%x", _Imm24_); } pass4 { mVUflagInfo |= 0xf << (/*mVUcount +*/ 8); } } -microVUf(void) mVU_FCSET(mF) { - microVU* mVU = mVUx; +mVUop(mVU_FCSET) { pass1 { mVUinfo |= _doClip; } pass2 { MOV32ItoR(gprT1, _Imm24_); - mVUallocCFLAGb(gprT1, fcInstance); + mVUallocCFLAGb(mVU, gprT1, fcInstance); } pass3 { mVUlog("FCSET $%x", _Imm24_); } } @@ -499,42 +477,39 @@ microVUf(void) mVU_FCSET(mF) { // FMAND/FMEQ/FMOR //------------------------------------------------------------------ -microVUf(void) mVU_FMAND(mF) { - microVU* mVU = mVUx; - pass1 { mVUanalyzeMflag(_Is_, _It_); } +mVUop(mVU_FMAND) { + pass1 { mVUanalyzeMflag(mVU, _Is_, _It_); } pass2 { - mVUallocMFLAGa(gprT1, fvmInstance); - mVUallocVIa(gprT2, _Is_); + mVUallocMFLAGa(mVU, gprT1, fvmInstance); + mVUallocVIa(mVU, gprT2, _Is_); AND16RtoR(gprT1, gprT2); - mVUallocVIb(gprT1, _It_); + mVUallocVIb(mVU, gprT1, _It_); } pass3 { mVUlog("FMAND vi%02d, vi%02d", _Ft_, _Fs_); } pass4 { mVUflagInfo |= 0xf << (/*mVUcount +*/ 4); } } -microVUf(void) mVU_FMEQ(mF) { - microVU* mVU = mVUx; - pass1 { mVUanalyzeMflag(_Is_, _It_); } +mVUop(mVU_FMEQ) { + pass1 { mVUanalyzeMflag(mVU, _Is_, _It_); } pass2 { - mVUallocMFLAGa(gprT1, fvmInstance); - mVUallocVIa(gprT2, _Is_); + mVUallocMFLAGa(mVU, gprT1, fvmInstance); + mVUallocVIa(mVU, gprT2, _Is_); XOR32RtoR(gprT1, gprT2); SUB32ItoR(gprT1, 1); SHR32ItoR(gprT1, 31); - mVUallocVIb(gprT1, _It_); + mVUallocVIb(mVU, gprT1, _It_); } pass3 { mVUlog("FMEQ vi%02d, vi%02d", _Ft_, _Fs_); } pass4 { mVUflagInfo |= 0xf << (/*mVUcount +*/ 4); } } -microVUf(void) mVU_FMOR(mF) { - microVU* mVU = mVUx; - pass1 { mVUanalyzeMflag(_Is_, _It_); } +mVUop(mVU_FMOR) { + pass1 { mVUanalyzeMflag(mVU, _Is_, _It_); } pass2 { - mVUallocMFLAGa(gprT1, fvmInstance); - mVUallocVIa(gprT2, _Is_); + mVUallocMFLAGa(mVU, gprT1, fvmInstance); + mVUallocVIa(mVU, gprT2, _Is_); OR16RtoR(gprT1, gprT2); - mVUallocVIb(gprT1, _It_); + mVUallocVIb(mVU, gprT1, _It_); } pass3 { mVUlog("FMOR vi%02d, vi%02d", _Ft_, _Fs_); } pass4 { mVUflagInfo |= 0xf << (/*mVUcount +*/ 4); } @@ -544,47 +519,43 @@ microVUf(void) mVU_FMOR(mF) { // FSAND/FSEQ/FSOR/FSSET //------------------------------------------------------------------ -microVUf(void) mVU_FSAND(mF) { - microVU* mVU = mVUx; - pass1 { mVUanalyzeSflag(_It_); } +mVUop(mVU_FSAND) { + pass1 { mVUanalyzeSflag(mVU, _It_); } pass2 { - mVUallocSFLAGa(gprT1, fvsInstance); + mVUallocSFLAGa(gprT1, fvsInstance); AND16ItoR(gprT1, _Imm12_); - mVUallocVIb(gprT1, _It_); + mVUallocVIb(mVU, gprT1, _It_); } pass3 { mVUlog("FSAND vi%02d, $%x", _Ft_, _Imm12_); } pass4 { mVUflagInfo |= 0xf << (/*mVUcount +*/ 0); mVUsFlagHack = 0; } } -microVUf(void) mVU_FSEQ(mF) { - microVU* mVU = mVUx; - pass1 { mVUanalyzeSflag(_It_); } +mVUop(mVU_FSEQ) { + pass1 { mVUanalyzeSflag(mVU, _It_); } pass2 { - mVUallocSFLAGa(gprT1, fvsInstance); + mVUallocSFLAGa(gprT1, fvsInstance); XOR16ItoR(gprT1, _Imm12_); SUB16ItoR(gprT1, 1); SHR16ItoR(gprT1, 15); - mVUallocVIb(gprT1, _It_); + mVUallocVIb(mVU, gprT1, _It_); } pass3 { mVUlog("FSEQ vi%02d, $%x", _Ft_, _Imm12_); } pass4 { mVUflagInfo |= 0xf << (/*mVUcount +*/ 0); mVUsFlagHack = 0; } } -microVUf(void) mVU_FSOR(mF) { - microVU* mVU = mVUx; - pass1 { mVUanalyzeSflag(_It_); } +mVUop(mVU_FSOR) { + pass1 { mVUanalyzeSflag(mVU, _It_); } pass2 { - mVUallocSFLAGa(gprT1, fvsInstance); + mVUallocSFLAGa(gprT1, fvsInstance); OR16ItoR(gprT1, _Imm12_); - mVUallocVIb(gprT1, _It_); + mVUallocVIb(mVU, gprT1, _It_); } pass3 { mVUlog("FSOR vi%02d, $%x", _Ft_, _Imm12_); } pass4 { mVUflagInfo |= 0xf << (/*mVUcount +*/ 0); mVUsFlagHack = 0; } } -microVUf(void) mVU_FSSET(mF) { - microVU* mVU = mVUx; - pass1 { mVUanalyzeFSSET(); } +mVUop(mVU_FSSET) { + pass1 { mVUanalyzeFSSET(mVU); } pass2 { int flagReg1, flagReg2; getFlagReg(flagReg1, fsInstance); @@ -600,97 +571,90 @@ microVUf(void) mVU_FSSET(mF) { // IADD/IADDI/IADDIU/IAND/IOR/ISUB/ISUBIU //------------------------------------------------------------------ -microVUf(void) mVU_IADD(mF) { - microVU* mVU = mVUx; - pass1 { mVUanalyzeIALU1(_Id_, _Is_, _It_); } +mVUop(mVU_IADD) { + pass1 { mVUanalyzeIALU1(mVU, _Id_, _Is_, _It_); } pass2 { - mVUallocVIa(gprT1, _Is_); + mVUallocVIa(mVU, gprT1, _Is_); if (_It_ != _Is_) { - mVUallocVIa(gprT2, _It_); + mVUallocVIa(mVU, gprT2, _It_); ADD16RtoR(gprT1, gprT2); } else ADD16RtoR(gprT1, gprT1); - mVUallocVIb(gprT1, _Id_); + mVUallocVIb(mVU, gprT1, _Id_); } pass3 { mVUlog("IADD vi%02d, vi%02d, vi%02d", _Fd_, _Fs_, _Ft_); } } -microVUf(void) mVU_IADDI(mF) { - microVU* mVU = mVUx; - pass1 { mVUanalyzeIALU2(_Is_, _It_); } +mVUop(mVU_IADDI) { + pass1 { mVUanalyzeIALU2(mVU, _Is_, _It_); } pass2 { - mVUallocVIa(gprT1, _Is_); + mVUallocVIa(mVU, gprT1, _Is_); ADD16ItoR(gprT1, _Imm5_); - mVUallocVIb(gprT1, _It_); + mVUallocVIb(mVU, gprT1, _It_); } pass3 { mVUlog("IADDI vi%02d, vi%02d, %d", _Ft_, _Fs_, _Imm5_); } } -microVUf(void) mVU_IADDIU(mF) { - microVU* mVU = mVUx; - pass1 { mVUanalyzeIALU2(_Is_, _It_); } +mVUop(mVU_IADDIU) { + pass1 { mVUanalyzeIALU2(mVU, _Is_, _It_); } pass2 { - mVUallocVIa(gprT1, _Is_); + mVUallocVIa(mVU, gprT1, _Is_); ADD16ItoR(gprT1, _Imm15_); - mVUallocVIb(gprT1, _It_); + mVUallocVIb(mVU, gprT1, _It_); } pass3 { mVUlog("IADDIU vi%02d, vi%02d, %d", _Ft_, _Fs_, _Imm15_); } } -microVUf(void) mVU_IAND(mF) { - microVU* mVU = mVUx; - pass1 { mVUanalyzeIALU1(_Id_, _Is_, _It_); } +mVUop(mVU_IAND) { + pass1 { mVUanalyzeIALU1(mVU, _Id_, _Is_, _It_); } pass2 { - mVUallocVIa(gprT1, _Is_); + mVUallocVIa(mVU, gprT1, _Is_); if (_It_ != _Is_) { - mVUallocVIa(gprT2, _It_); + mVUallocVIa(mVU, gprT2, _It_); AND32RtoR(gprT1, gprT2); } - mVUallocVIb(gprT1, _Id_); + mVUallocVIb(mVU, gprT1, _Id_); } pass3 { mVUlog("IAND vi%02d, vi%02d, vi%02d", _Fd_, _Fs_, _Ft_); } } -microVUf(void) mVU_IOR(mF) { - microVU* mVU = mVUx; - pass1 { mVUanalyzeIALU1(_Id_, _Is_, _It_); } +mVUop(mVU_IOR) { + pass1 { mVUanalyzeIALU1(mVU, _Id_, _Is_, _It_); } pass2 { - mVUallocVIa(gprT1, _Is_); + mVUallocVIa(mVU, gprT1, _Is_); if (_It_ != _Is_) { - mVUallocVIa(gprT2, _It_); + mVUallocVIa(mVU, gprT2, _It_); OR32RtoR(gprT1, gprT2); } - mVUallocVIb(gprT1, _Id_); + mVUallocVIb(mVU, gprT1, _Id_); } pass3 { mVUlog("IOR vi%02d, vi%02d, vi%02d", _Fd_, _Fs_, _Ft_); } } -microVUf(void) mVU_ISUB(mF) { - microVU* mVU = mVUx; - pass1 { mVUanalyzeIALU1(_Id_, _Is_, _It_); } +mVUop(mVU_ISUB) { + pass1 { mVUanalyzeIALU1(mVU, _Id_, _Is_, _It_); } pass2 { if (_It_ != _Is_) { - mVUallocVIa(gprT1, _Is_); - mVUallocVIa(gprT2, _It_); + mVUallocVIa(mVU, gprT1, _Is_); + mVUallocVIa(mVU, gprT2, _It_); SUB16RtoR(gprT1, gprT2); - mVUallocVIb(gprT1, _Id_); + mVUallocVIb(mVU, gprT1, _Id_); } else if (!isMMX(_Id_)) { XOR32RtoR(gprT1, gprT1); - mVUallocVIb(gprT1, _Id_); + mVUallocVIb(mVU, gprT1, _Id_); } else { PXORRtoR(mmVI(_Id_), mmVI(_Id_)); } } pass3 { mVUlog("ISUB vi%02d, vi%02d, vi%02d", _Fd_, _Fs_, _Ft_); } } -microVUf(void) mVU_ISUBIU(mF) { - microVU* mVU = mVUx; - pass1 { mVUanalyzeIALU2(_Is_, _It_); } +mVUop(mVU_ISUBIU) { + pass1 { mVUanalyzeIALU2(mVU, _Is_, _It_); } pass2 { - mVUallocVIa(gprT1, _Is_); + mVUallocVIa(mVU, gprT1, _Is_); SUB16ItoR(gprT1, _Imm15_); - mVUallocVIb(gprT1, _It_); + mVUallocVIb(mVU, gprT1, _It_); } pass3 { mVUlog("ISUBIU vi%02d, vi%02d, %d", _Ft_, _Fs_, _Imm15_); } } @@ -699,56 +663,51 @@ microVUf(void) mVU_ISUBIU(mF) { // MFIR/MFP/MOVE/MR32/MTIR //------------------------------------------------------------------ -microVUf(void) mVU_MFIR(mF) { - microVU* mVU = mVUx; +mVUop(mVU_MFIR) { pass1 { if (!_Ft_) { mVUinfo |= _isNOP; } analyzeVIreg1(_Is_); analyzeReg2(_Ft_, 1); } pass2 { - mVUallocVIa(gprT1, _Is_); + mVUallocVIa(mVU, gprT1, _Is_); MOVSX32R16toR(gprT1, gprT1); SSE2_MOVD_R_to_XMM(xmmT1, gprT1); - if (!_XYZW_SS) { mVUunpack_xyzw(xmmT1, xmmT1, 0); } - mVUsaveReg(xmmT1, (uptr)&mVU->regs->VF[_Ft_].UL[0], _X_Y_Z_W, 1); + if (!_XYZW_SS) { mVUunpack_xyzw(xmmT1, xmmT1, 0); } + mVUsaveReg(xmmT1, (uptr)&mVU->regs->VF[_Ft_].UL[0], _X_Y_Z_W, 1); } pass3 { mVUlog("MFIR.%s vf%02d, vi%02d", _XYZW_String, _Ft_, _Fs_); } } -microVUf(void) mVU_MFP(mF) { - microVU* mVU = mVUx; - pass1 { mVUanalyzeMFP(_Ft_); } +mVUop(mVU_MFP) { + pass1 { mVUanalyzeMFP(mVU, _Ft_); } pass2 { getPreg(xmmFt); - mVUsaveReg(xmmFt, (uptr)&mVU->regs->VF[_Ft_].UL[0], _X_Y_Z_W, 1); + mVUsaveReg(xmmFt, (uptr)&mVU->regs->VF[_Ft_].UL[0], _X_Y_Z_W, 1); } pass3 { mVUlog("MFP.%s vf%02d, P", _XYZW_String, _Ft_); } } -microVUf(void) mVU_MOVE(mF) { - microVU* mVU = mVUx; - pass1 { mVUanalyzeMOVE(_Fs_, _Ft_); } +mVUop(mVU_MOVE) { + pass1 { mVUanalyzeMOVE(mVU, _Fs_, _Ft_); } pass2 { - mVUloadReg(xmmT1, (uptr)&mVU->regs->VF[_Fs_].UL[0], _X_Y_Z_W); - mVUsaveReg(xmmT1, (uptr)&mVU->regs->VF[_Ft_].UL[0], _X_Y_Z_W, 1); + mVUloadReg(xmmT1, (uptr)&mVU->regs->VF[_Fs_].UL[0], _X_Y_Z_W); + mVUsaveReg(xmmT1, (uptr)&mVU->regs->VF[_Ft_].UL[0], _X_Y_Z_W, 1); } pass3 { mVUlog("MOVE.%s vf%02d, vf%02d", _XYZW_String, _Ft_, _Fs_); } } -microVUf(void) mVU_MR32(mF) { - microVU* mVU = mVUx; - pass1 { mVUanalyzeMR32(_Fs_, _Ft_); } +mVUop(mVU_MR32) { + pass1 { mVUanalyzeMR32(mVU, _Fs_, _Ft_); } pass2 { - mVUloadReg(xmmT1, (uptr)&mVU->regs->VF[_Fs_].UL[0], (_X_Y_Z_W == 8) ? 4 : 15); + mVUloadReg(xmmT1, (uptr)&mVU->regs->VF[_Fs_].UL[0], (_X_Y_Z_W == 8) ? 4 : 15); if (_X_Y_Z_W != 8) { SSE2_PSHUFD_XMM_to_XMM(xmmT1, xmmT1, 0x39); } - mVUsaveReg(xmmT1, (uptr)&mVU->regs->VF[_Ft_].UL[0], _X_Y_Z_W, 0); + mVUsaveReg(xmmT1, (uptr)&mVU->regs->VF[_Ft_].UL[0], _X_Y_Z_W, 0); } pass3 { mVUlog("MR32.%s vf%02d, vf%02d", _XYZW_String, _Ft_, _Fs_); } } -microVUf(void) mVU_MTIR(mF) { - microVU* mVU = mVUx; +mVUop(mVU_MTIR) { pass1 { if (!_It_) { mVUinfo |= _isNOP; } analyzeReg5(_Fs_, _Fsf_); analyzeVIreg2(_It_, 1); } pass2 { MOVZX32M16toR(gprT1, (uptr)&mVU->regs->VF[_Fs_].UL[_Fsf_]); - mVUallocVIb(gprT1, _It_); + mVUallocVIb(mVU, gprT1, _It_); } pass3 { mVUlog("MTIR vi%02d, vf%02d%s", _Ft_, _Fs_, _Fsf_String); } } @@ -757,38 +716,36 @@ microVUf(void) mVU_MTIR(mF) { // ILW/ILWR //------------------------------------------------------------------ -microVUf(void) mVU_ILW(mF) { - microVU* mVU = mVUx; +mVUop(mVU_ILW) { pass1 { if (!_It_) { mVUinfo |= _isNOP; } analyzeVIreg1(_Is_); analyzeVIreg2(_It_, 4); } pass2 { if (!_Is_) { MOVZX32M16toR(gprT1, (uptr)mVU->regs->Mem + getVUmem(_Imm11_) + offsetSS); - mVUallocVIb(gprT1, _It_); + mVUallocVIb(mVU, gprT1, _It_); } else { - mVUallocVIa(gprT1, _Is_); + mVUallocVIa(mVU, gprT1, _Is_); ADD32ItoR(gprT1, _Imm11_); - mVUaddrFix(gprT1); + mVUaddrFix(mVU, gprT1); MOVZX32Rm16toR(gprT1, gprT1, (uptr)mVU->regs->Mem + offsetSS); - mVUallocVIb(gprT1, _It_); + mVUallocVIb(mVU, gprT1, _It_); } } pass3 { mVUlog("ILW.%s vi%02d, vi%02d + %d", _XYZW_String, _Ft_, _Fs_, _Imm11_); } } -microVUf(void) mVU_ILWR(mF) { - microVU* mVU = mVUx; +mVUop(mVU_ILWR) { pass1 { if (!_It_) { mVUinfo |= _isNOP; } analyzeVIreg1(_Is_); analyzeVIreg2(_It_, 4); } pass2 { if (!_Is_) { MOVZX32M16toR(gprT1, (uptr)mVU->regs->Mem + offsetSS); - mVUallocVIb(gprT1, _It_); + mVUallocVIb(mVU, gprT1, _It_); } else { - mVUallocVIa(gprT1, _Is_); - mVUaddrFix(gprT1); + mVUallocVIa(mVU, gprT1, _Is_); + mVUaddrFix(mVU, gprT1); MOVZX32Rm16toR(gprT1, gprT1, (uptr)mVU->regs->Mem + offsetSS); - mVUallocVIb(gprT1, _It_); + mVUallocVIb(mVU, gprT1, _It_); } } pass3 { mVUlog("ILWR.%s vi%02d, vi%02d", _XYZW_String, _Ft_, _Fs_); } @@ -798,23 +755,22 @@ microVUf(void) mVU_ILWR(mF) { // ISW/ISWR //------------------------------------------------------------------ -microVUf(void) mVU_ISW(mF) { - microVU* mVU = mVUx; +mVUop(mVU_ISW) { pass1 { analyzeVIreg1(_Is_); analyzeVIreg1(_It_); } pass2 { if (!_Is_) { int imm = getVUmem(_Imm11_); - mVUallocVIa(gprT1, _It_); + mVUallocVIa(mVU, gprT1, _It_); if (_X) MOV32RtoM((uptr)mVU->regs->Mem + imm, gprT1); if (_Y) MOV32RtoM((uptr)mVU->regs->Mem + imm + 4, gprT1); if (_Z) MOV32RtoM((uptr)mVU->regs->Mem + imm + 8, gprT1); if (_W) MOV32RtoM((uptr)mVU->regs->Mem + imm + 12, gprT1); } else { - mVUallocVIa(gprT1, _Is_); - mVUallocVIa(gprT2, _It_); + mVUallocVIa(mVU, gprT1, _Is_); + mVUallocVIa(mVU, gprT2, _It_); ADD32ItoR(gprT1, _Imm11_); - mVUaddrFix(gprT1); + mVUaddrFix(mVU, gprT1); if (_X) MOV32RtoRm(gprT1, gprT2, (uptr)mVU->regs->Mem); if (_Y) MOV32RtoRm(gprT1, gprT2, (uptr)mVU->regs->Mem+4); if (_Z) MOV32RtoRm(gprT1, gprT2, (uptr)mVU->regs->Mem+8); @@ -824,21 +780,20 @@ microVUf(void) mVU_ISW(mF) { pass3 { mVUlog("ISW.%s vi%02d, vi%02d + %d", _XYZW_String, _Ft_, _Fs_, _Imm11_); } } -microVUf(void) mVU_ISWR(mF) { - microVU* mVU = mVUx; +mVUop(mVU_ISWR) { pass1 { analyzeVIreg1(_Is_); analyzeVIreg1(_It_); } pass2 { if (!_Is_) { - mVUallocVIa(gprT1, _It_); + mVUallocVIa(mVU, gprT1, _It_); if (_X) MOV32RtoM((uptr)mVU->regs->Mem, gprT1); if (_Y) MOV32RtoM((uptr)mVU->regs->Mem+4, gprT1); if (_Z) MOV32RtoM((uptr)mVU->regs->Mem+8, gprT1); if (_W) MOV32RtoM((uptr)mVU->regs->Mem+12, gprT1); } else { - mVUallocVIa(gprT1, _Is_); - mVUallocVIa(gprT2, _It_); - mVUaddrFix(gprT1); + mVUallocVIa(mVU, gprT1, _Is_); + mVUallocVIa(mVU, gprT2, _It_); + mVUaddrFix(mVU, gprT1); if (_X) MOV32RtoRm(gprT1, gprT2, (uptr)mVU->regs->Mem); if (_Y) MOV32RtoRm(gprT1, gprT2, (uptr)mVU->regs->Mem+4); if (_Z) MOV32RtoRm(gprT1, gprT2, (uptr)mVU->regs->Mem+8); @@ -852,65 +807,62 @@ microVUf(void) mVU_ISWR(mF) { // LQ/LQD/LQI //------------------------------------------------------------------ -microVUf(void) mVU_LQ(mF) { - microVU* mVU = mVUx; - pass1 { mVUanalyzeLQ(_Ft_, _Is_, 0); } +mVUop(mVU_LQ) { + pass1 { mVUanalyzeLQ(mVU, _Ft_, _Is_, 0); } pass2 { if (!_Is_) { - mVUloadReg(xmmFt, (uptr)mVU->regs->Mem + getVUmem(_Imm11_), _X_Y_Z_W); - mVUsaveReg(xmmFt, (uptr)&mVU->regs->VF[_Ft_].UL[0], _X_Y_Z_W, 1); + mVUloadReg(xmmFt, (uptr)mVU->regs->Mem + getVUmem(_Imm11_), _X_Y_Z_W); + mVUsaveReg(xmmFt, (uptr)&mVU->regs->VF[_Ft_].UL[0], _X_Y_Z_W, 1); } else { - mVUallocVIa(gprT1, _Is_); + mVUallocVIa(mVU, gprT1, _Is_); ADD32ItoR(gprT1, _Imm11_); - mVUaddrFix(gprT1); - mVUloadReg2(xmmFt, gprT1, (uptr)mVU->regs->Mem, _X_Y_Z_W); - mVUsaveReg(xmmFt, (uptr)&mVU->regs->VF[_Ft_].UL[0], _X_Y_Z_W, 1); + mVUaddrFix(mVU, gprT1); + mVUloadReg2(xmmFt, gprT1, (uptr)mVU->regs->Mem, _X_Y_Z_W); + mVUsaveReg(xmmFt, (uptr)&mVU->regs->VF[_Ft_].UL[0], _X_Y_Z_W, 1); } } pass3 { mVUlog("LQ.%s vf%02d, vi%02d + %d", _XYZW_String, _Ft_, _Fs_, _Imm11_); } } -microVUf(void) mVU_LQD(mF) { - microVU* mVU = mVUx; - pass1 { mVUanalyzeLQ(_Ft_, _Is_, 1); } +mVUop(mVU_LQD) { + pass1 { mVUanalyzeLQ(mVU, _Ft_, _Is_, 1); } pass2 { if (!_Is_ && !noWriteVF) { - mVUloadReg(xmmFt, (uptr)mVU->regs->Mem, _X_Y_Z_W); - mVUsaveReg(xmmFt, (uptr)&mVU->regs->VF[_Ft_].UL[0], _X_Y_Z_W, 1); + mVUloadReg(xmmFt, (uptr)mVU->regs->Mem, _X_Y_Z_W); + mVUsaveReg(xmmFt, (uptr)&mVU->regs->VF[_Ft_].UL[0], _X_Y_Z_W, 1); } else { - mVUallocVIa(gprT1, _Is_); + mVUallocVIa(mVU, gprT1, _Is_); SUB16ItoR(gprT1, 1); - mVUallocVIb(gprT1, _Is_); + mVUallocVIb(mVU, gprT1, _Is_); if (!noWriteVF) { - mVUaddrFix(gprT1); - mVUloadReg2(xmmFt, gprT1, (uptr)mVU->regs->Mem, _X_Y_Z_W); - mVUsaveReg(xmmFt, (uptr)&mVU->regs->VF[_Ft_].UL[0], _X_Y_Z_W, 1); + mVUaddrFix(mVU, gprT1); + mVUloadReg2(xmmFt, gprT1, (uptr)mVU->regs->Mem, _X_Y_Z_W); + mVUsaveReg(xmmFt, (uptr)&mVU->regs->VF[_Ft_].UL[0], _X_Y_Z_W, 1); } } } pass3 { mVUlog("LQD.%s vf%02d, --vi%02d", _XYZW_String, _Ft_, _Is_); } } -microVUf(void) mVU_LQI(mF) { - microVU* mVU = mVUx; - pass1 { mVUanalyzeLQ(_Ft_, _Is_, 1); } +mVUop(mVU_LQI) { + pass1 { mVUanalyzeLQ(mVU, _Ft_, _Is_, 1); } pass2 { if (!_Is_ && !noWriteVF) { - mVUloadReg(xmmFt, (uptr)mVU->regs->Mem, _X_Y_Z_W); - mVUsaveReg(xmmFt, (uptr)&mVU->regs->VF[_Ft_].UL[0], _X_Y_Z_W, 1); + mVUloadReg(xmmFt, (uptr)mVU->regs->Mem, _X_Y_Z_W); + mVUsaveReg(xmmFt, (uptr)&mVU->regs->VF[_Ft_].UL[0], _X_Y_Z_W, 1); } else { - mVUallocVIa((!noWriteVF) ? gprT1 : gprT2, _Is_); + mVUallocVIa(mVU, (!noWriteVF) ? gprT1 : gprT2, _Is_); if (!noWriteVF) { MOV32RtoR(gprT2, gprT1); - mVUaddrFix(gprT1); - mVUloadReg2(xmmFt, gprT1, (uptr)mVU->regs->Mem, _X_Y_Z_W); - mVUsaveReg(xmmFt, (uptr)&mVU->regs->VF[_Ft_].UL[0], _X_Y_Z_W, 1); + mVUaddrFix(mVU, gprT1); + mVUloadReg2(xmmFt, gprT1, (uptr)mVU->regs->Mem, _X_Y_Z_W); + mVUsaveReg(xmmFt, (uptr)&mVU->regs->VF[_Ft_].UL[0], _X_Y_Z_W, 1); } ADD16ItoR(gprT2, 1); - mVUallocVIb(gprT2, _Is_); + mVUallocVIb(mVU, gprT2, _Is_); } } pass3 { mVUlog("LQI.%s vf%02d, vi%02d++", _XYZW_String, _Ft_, _Fs_); } @@ -920,61 +872,58 @@ microVUf(void) mVU_LQI(mF) { // SQ/SQD/SQI //------------------------------------------------------------------ -microVUf(void) mVU_SQ(mF) { - microVU* mVU = mVUx; - pass1 { mVUanalyzeSQ(_Fs_, _It_, 0); } +mVUop(mVU_SQ) { + pass1 { mVUanalyzeSQ(mVU, _Fs_, _It_, 0); } pass2 { if (!_It_) { getReg7(xmmFs, _Fs_); - mVUsaveReg(xmmFs, (uptr)mVU->regs->Mem + getVUmem(_Imm11_), _X_Y_Z_W, 1); + mVUsaveReg(xmmFs, (uptr)mVU->regs->Mem + getVUmem(_Imm11_), _X_Y_Z_W, 1); } else { - mVUallocVIa(gprT1, _It_); + mVUallocVIa(mVU, gprT1, _It_); ADD32ItoR(gprT1, _Imm11_); - mVUaddrFix(gprT1); + mVUaddrFix(mVU, gprT1); getReg7(xmmFs, _Fs_); - mVUsaveReg2(xmmFs, gprT1, (uptr)mVU->regs->Mem, _X_Y_Z_W); + mVUsaveReg2(xmmFs, gprT1, (uptr)mVU->regs->Mem, _X_Y_Z_W); } } pass3 { mVUlog("SQ.%s vf%02d, vi%02d + %d", _XYZW_String, _Fs_, _Ft_, _Imm11_); } } -microVUf(void) mVU_SQD(mF) { - microVU* mVU = mVUx; - pass1 { mVUanalyzeSQ(_Fs_, _It_, 1); } +mVUop(mVU_SQD) { + pass1 { mVUanalyzeSQ(mVU, _Fs_, _It_, 1); } pass2 { if (!_It_) { getReg7(xmmFs, _Fs_); - mVUsaveReg(xmmFs, (uptr)mVU->regs->Mem, _X_Y_Z_W, 1); + mVUsaveReg(xmmFs, (uptr)mVU->regs->Mem, _X_Y_Z_W, 1); } else { - mVUallocVIa(gprT1, _It_); + mVUallocVIa(mVU, gprT1, _It_); SUB16ItoR(gprT1, 1); - mVUallocVIb(gprT1, _It_); - mVUaddrFix(gprT1); + mVUallocVIb(mVU, gprT1, _It_); + mVUaddrFix(mVU, gprT1); getReg7(xmmFs, _Fs_); - mVUsaveReg2(xmmFs, gprT1, (uptr)mVU->regs->Mem, _X_Y_Z_W); + mVUsaveReg2(xmmFs, gprT1, (uptr)mVU->regs->Mem, _X_Y_Z_W); } } pass3 { mVUlog("SQD.%s vf%02d, --vi%02d", _XYZW_String, _Fs_, _Ft_); } } -microVUf(void) mVU_SQI(mF) { - microVU* mVU = mVUx; - pass1 { mVUanalyzeSQ(_Fs_, _It_, 1); } +mVUop(mVU_SQI) { + pass1 { mVUanalyzeSQ(mVU, _Fs_, _It_, 1); } pass2 { if (!_It_) { getReg7(xmmFs, _Fs_); - mVUsaveReg(xmmFs, (uptr)mVU->regs->Mem, _X_Y_Z_W, 1); + mVUsaveReg(xmmFs, (uptr)mVU->regs->Mem, _X_Y_Z_W, 1); } else { - mVUallocVIa(gprT1, _It_); + mVUallocVIa(mVU, gprT1, _It_); MOV32RtoR(gprT2, gprT1); - mVUaddrFix(gprT1); + mVUaddrFix(mVU, gprT1); getReg7(xmmFs, _Fs_); - mVUsaveReg2(xmmFs, gprT1, (uptr)mVU->regs->Mem, _X_Y_Z_W); + mVUsaveReg2(xmmFs, gprT1, (uptr)mVU->regs->Mem, _X_Y_Z_W); ADD16ItoR(gprT2, 1); - mVUallocVIb(gprT2, _It_); + mVUallocVIb(mVU, gprT2, _It_); } } pass3 { mVUlog("SQI.%s vf%02d, vi%02d++", _XYZW_String, _Fs_, _Ft_); } @@ -984,9 +933,8 @@ microVUf(void) mVU_SQI(mF) { // RINIT/RGET/RNEXT/RXOR //------------------------------------------------------------------ -microVUf(void) mVU_RINIT(mF) { - microVU* mVU = mVUx; - pass1 { mVUanalyzeR1(_Fs_, _Fsf_); } +mVUop(mVU_RINIT) { + pass1 { mVUanalyzeR1(mVU, _Fs_, _Fsf_); } pass2 { if (_Fs_ || (_Fsf_ == 3)) { getReg8(gprT1, _Fs_, _Fsf_); @@ -999,8 +947,7 @@ microVUf(void) mVU_RINIT(mF) { pass3 { mVUlog("RINIT R, vf%02d%s", _Fs_, _Fsf_String); } } -microVUt(void) mVU_RGET_(int Rreg) { - microVU* mVU = mVUx; +microVUt(void) mVU_RGET_(mV, int Rreg) { if (!noWriteVF) { if (_X) MOV32RtoM((uptr)&mVU->regs->VF[_Ft_].UL[0], Rreg); if (_Y) MOV32RtoM((uptr)&mVU->regs->VF[_Ft_].UL[1], Rreg); @@ -1009,16 +956,14 @@ microVUt(void) mVU_RGET_(int Rreg) { } } -microVUf(void) mVU_RGET(mF) { - microVU* mVU = mVUx; - pass1 { mVUanalyzeR2(_Ft_, 1); } - pass2 { MOV32MtoR(gprT1, Rmem); mVU_RGET_(gprT1); } +mVUop(mVU_RGET) { + pass1 { mVUanalyzeR2(mVU, _Ft_, 1); } + pass2 { MOV32MtoR(gprT1, Rmem); mVU_RGET_(mVU, gprT1); } pass3 { mVUlog("RGET.%s vf%02d, R", _XYZW_String, _Ft_); } } -microVUf(void) mVU_RNEXT(mF) { - microVU* mVU = mVUx; - pass1 { mVUanalyzeR2(_Ft_, 0); } +mVUop(mVU_RNEXT) { + pass1 { mVUanalyzeR2(mVU, _Ft_, 0); } pass2 { // algorithm from www.project-fao.org MOV32MtoR(gprR, Rmem); @@ -1035,15 +980,14 @@ microVUf(void) mVU_RNEXT(mF) { XOR32RtoR(gprR, gprT1); AND32ItoR(gprR, 0x007fffff); OR32ItoR (gprR, 0x3f800000); - mVU_RGET_(gprR); + mVU_RGET_(mVU, gprR); MOV32ItoR(gprR, Roffset); // Restore gprR } pass3 { mVUlog("RNEXT.%s vf%02d, R", _XYZW_String, _Ft_); } } -microVUf(void) mVU_RXOR(mF) { - microVU* mVU = mVUx; - pass1 { mVUanalyzeR1(_Fs_, _Fsf_); } +mVUop(mVU_RXOR) { + pass1 { mVUanalyzeR1(mVU, _Fs_, _Fsf_); } pass2 { if (_Fs_ || (_Fsf_ == 3)) { getReg8(gprT1, _Fs_, _Fsf_); @@ -1058,14 +1002,12 @@ microVUf(void) mVU_RXOR(mF) { // WaitP/WaitQ //------------------------------------------------------------------ -microVUf(void) mVU_WAITP(mF) { - microVU* mVU = mVUx; +mVUop(mVU_WAITP) { pass1 { mVUstall = aMax(mVUstall, ((mVUregs.p) ? (mVUregs.p - 1) : 0)); } pass3 { mVUlog("WAITP"); } } -microVUf(void) mVU_WAITQ(mF) { - microVU* mVU = mVUx; +mVUop(mVU_WAITQ) { pass1 { mVUstall = aMax(mVUstall, mVUregs.q); } pass3 { mVUlog("WAITQ"); } } @@ -1074,22 +1016,20 @@ microVUf(void) mVU_WAITQ(mF) { // XTOP/XITOP //------------------------------------------------------------------ -microVUf(void) mVU_XTOP(mF) { - microVU* mVU = mVUx; +mVUop(mVU_XTOP) { pass1 { if (!_It_) { mVUinfo |= _isNOP; } analyzeVIreg2(_It_, 1); } pass2 { MOVZX32M16toR(gprT1, (uptr)&mVU->regs->vifRegs->top); - mVUallocVIb(gprT1, _It_); + mVUallocVIb(mVU, gprT1, _It_); } pass3 { mVUlog("XTOP vi%02d", _Ft_); } } -microVUf(void) mVU_XITOP(mF) { - microVU* mVU = mVUx; +mVUop(mVU_XITOP) { pass1 { if (!_It_) { mVUinfo |= _isNOP; } analyzeVIreg2(_It_, 1); } pass2 { MOVZX32M16toR(gprT1, (uptr)&mVU->regs->vifRegs->itop); - mVUallocVIb(gprT1, _It_); + mVUallocVIb(mVU, gprT1, _It_); } pass3 { mVUlog("XITOP vi%02d", _Ft_); } } @@ -1103,9 +1043,7 @@ void __fastcall mVU_XGKICK_(u32 addr) { u32 *data = (u32*)(microVU1.regs->Mem + addr); u32 size = mtgsThread->PrepDataPacket(GIF_PATH_1, data, (0x4000-addr) >> 4); u8 *pDest = mtgsThread->GetDataPacketPtr(); -/* - if((size << 4) > (0x4000-(addr&0x3fff))) - { +/* if((size << 4) > (0x4000-(addr&0x3fff))) { //DevCon::Notice("addr + Size = 0x%x, transferring %x then doing %x", params (addr&0x3fff) + (size << 4), (0x4000-(addr&0x3fff)) >> 4, size - ((0x4000-(addr&0x3fff)) >> 4)); memcpy_aligned(pDest, microVU1.regs->Mem + addr, 0x4000-(addr&0x3fff)); size -= (0x4000-(addr&0x3fff)) >> 4; @@ -1113,12 +1051,9 @@ void __fastcall mVU_XGKICK_(u32 addr) { pDest += 0x4000-(addr&0x3fff); memcpy_aligned(pDest, microVU1.regs->Mem, size<<4); } - else - { -*/ + else { */ memcpy_aligned(pDest, microVU1.regs->Mem + addr, size<<4); // } - mtgsThread->SendDataPacket(); } @@ -1126,24 +1061,22 @@ void __fastcall mVU_XGKICK__(u32 addr) { GSGIFTRANSFER1((u32*)microVU1.regs->Mem, ((addr<<4)&0x3fff)); } -microVUf(void) mVU_XGKICK(mF) { - microVU* mVU = mVUx; - pass1 { mVUanalyzeXGkick(_Is_, mVU_XGKICK_CYCLES); } +mVUop(mVU_XGKICK) { + pass1 { mVUanalyzeXGkick(mVU, _Is_, mVU_XGKICK_CYCLES); } pass2 { mVUprint("XGkick"); - mVUallocVIa(gprT1, _Is_); + mVUallocVIa(mVU, gprT1, _Is_); MOV32RtoM((uptr)&mVU->VIxgkick, gprT1); } pass3 { mVUlog("XGKICK vi%02d", _Fs_); } } -microVUt(void) mVU_XGKICK_DELAY() { - microVU* mVU = mVUx; +microVUt(void) mVU_XGKICK_DELAY(mV) { MOV32MtoR(gprT2, (uptr)&mVU->VIxgkick); // gprT2 = ECX for __fastcall - mVUbackupRegs(); + mVUbackupRegs(mVU); if (mtgsThread != NULL) CALLFunc((uptr)mVU_XGKICK_); else CALLFunc((uptr)mVU_XGKICK__); - mVUrestoreRegs(); + mVUrestoreRegs(mVU); } //------------------------------------------------------------------ @@ -1157,123 +1090,113 @@ microVUt(void) mVU_XGKICK_DELAY() { pass4 { if (_Imm11_ == 1 && !_x_) { return; } mVUbranch = x; } \ } -microVUf(void) mVU_B(mF) { - microVU* mVU = mVUx; +mVUop(mVU_B) { setBranchA(1, 0); pass3 { mVUlog("B [%04x]", branchAddr, branchAddr); } } -microVUf(void) mVU_BAL(mF) { - microVU* mVU = mVUx; +mVUop(mVU_BAL) { setBranchA(2, _It_); pass1 { analyzeVIreg2(_It_, 1); } pass2 { MOV32ItoR(gprT1, bSaveAddr); - mVUallocVIb(gprT1, _It_); + mVUallocVIb(mVU, gprT1, _It_); } pass3 { mVUlog("BAL vi%02d [%04x]", _Ft_, branchAddr, branchAddr); } } -microVUf(void) mVU_IBEQ(mF) { - microVU* mVU = mVUx; +mVUop(mVU_IBEQ) { setBranchA(3, 0); - pass1 { mVUanalyzeBranch2(_Is_, _It_); } + pass1 { mVUanalyzeBranch2(mVU, _Is_, _It_); } pass2 { if (memReadIs) MOV32MtoR(gprT1, (uptr)&mVU->VIbackup[0]); - else mVUallocVIa(gprT1, _Is_); + else mVUallocVIa(mVU, gprT1, _Is_); if (memReadIt) XOR32MtoR(gprT1, (uptr)&mVU->VIbackup[0]); - else { mVUallocVIa(gprT2, _It_); XOR32RtoR(gprT1, gprT2); } + else { mVUallocVIa(mVU, gprT2, _It_); XOR32RtoR(gprT1, gprT2); } MOV32RtoM((uptr)&mVU->branch, gprT1); } pass3 { mVUlog("IBEQ vi%02d, vi%02d [%04x]", _Ft_, _Fs_, branchAddr, branchAddr); } } -microVUf(void) mVU_IBGEZ(mF) { - microVU* mVU = mVUx; +mVUop(mVU_IBGEZ) { setBranchA(4, 0); - pass1 { mVUanalyzeBranch1(_Is_); } + pass1 { mVUanalyzeBranch1(mVU, _Is_); } pass2 { if (memReadIs) MOV32MtoR(gprT1, (uptr)&mVU->VIbackup[0]); - else mVUallocVIa(gprT1, _Is_); + else mVUallocVIa(mVU, gprT1, _Is_); MOV32RtoM((uptr)&mVU->branch, gprT1); } pass3 { mVUlog("IBGEZ vi%02d [%04x]", _Fs_, branchAddr, branchAddr); } } -microVUf(void) mVU_IBGTZ(mF) { - microVU* mVU = mVUx; +mVUop(mVU_IBGTZ) { setBranchA(5, 0); - pass1 { mVUanalyzeBranch1(_Is_); } + pass1 { mVUanalyzeBranch1(mVU, _Is_); } pass2 { if (memReadIs) MOV32MtoR(gprT1, (uptr)&mVU->VIbackup[0]); - else mVUallocVIa(gprT1, _Is_); + else mVUallocVIa(mVU, gprT1, _Is_); MOV32RtoM((uptr)&mVU->branch, gprT1); } pass3 { mVUlog("IBGTZ vi%02d [%04x]", _Fs_, branchAddr, branchAddr); } } -microVUf(void) mVU_IBLEZ(mF) { - microVU* mVU = mVUx; +mVUop(mVU_IBLEZ) { setBranchA(6, 0); - pass1 { mVUanalyzeBranch1(_Is_); } + pass1 { mVUanalyzeBranch1(mVU, _Is_); } pass2 { if (memReadIs) MOV32MtoR(gprT1, (uptr)&mVU->VIbackup[0]); - else mVUallocVIa(gprT1, _Is_); + else mVUallocVIa(mVU, gprT1, _Is_); MOV32RtoM((uptr)&mVU->branch, gprT1); } pass3 { mVUlog("IBLEZ vi%02d [%04x]", _Fs_, branchAddr, branchAddr); } } -microVUf(void) mVU_IBLTZ(mF) { - microVU* mVU = mVUx; +mVUop(mVU_IBLTZ) { setBranchA(7, 0); - pass1 { mVUanalyzeBranch1(_Is_); } + pass1 { mVUanalyzeBranch1(mVU, _Is_); } pass2 { if (memReadIs) MOV32MtoR(gprT1, (uptr)&mVU->VIbackup[0]); - else mVUallocVIa(gprT1, _Is_); + else mVUallocVIa(mVU, gprT1, _Is_); MOV32RtoM((uptr)&mVU->branch, gprT1); } pass3 { mVUlog("IBLTZ vi%02d [%04x]", _Fs_, branchAddr, branchAddr); } } -microVUf(void) mVU_IBNE(mF) { - microVU* mVU = mVUx; +mVUop(mVU_IBNE) { setBranchA(8, 0); - pass1 { mVUanalyzeBranch2(_Is_, _It_); } + pass1 { mVUanalyzeBranch2(mVU, _Is_, _It_); } pass2 { if (memReadIs) MOV32MtoR(gprT1, (uptr)&mVU->VIbackup[0]); - else mVUallocVIa(gprT1, _Is_); + else mVUallocVIa(mVU, gprT1, _Is_); if (memReadIt) XOR32MtoR(gprT1, (uptr)&mVU->VIbackup[0]); - else { mVUallocVIa(gprT2, _It_); XOR32RtoR(gprT1, gprT2); } + else { mVUallocVIa(mVU, gprT2, _It_); XOR32RtoR(gprT1, gprT2); } MOV32RtoM((uptr)&mVU->branch, gprT1); } pass3 { mVUlog("IBNE vi%02d, vi%02d [%04x]", _Ft_, _Fs_, branchAddr, branchAddr); } } -microVUf(void) mVU_JR(mF) { - microVU* mVU = mVUx; +mVUop(mVU_JR) { mVUbranch = 9; pass1 { analyzeVIreg1(_Is_); } pass2 { - mVUallocVIa(gprT1, _Is_); + mVUallocVIa(mVU, gprT1, _Is_); SHL32ItoR(gprT1, 3); - AND32ItoR(gprT1, vuIndex ? 0x3ff8 : 0xff8); + AND32ItoR(gprT1, isVU1 ? 0x3ff8 : 0xff8); MOV32RtoM((uptr)&mVU->branch, gprT1); } pass3 { mVUlog("JR [vi%02d]", _Fs_); } } -microVUf(void) mVU_JALR(mF) { - microVU* mVU = mVUx; +mVUop(mVU_JALR) { mVUbranch = 10; pass1 { analyzeVIreg1(_Is_); analyzeVIreg2(_It_, 1); } pass2 { - mVUallocVIa(gprT1, _Is_); + mVUallocVIa(mVU, gprT1, _Is_); SHL32ItoR(gprT1, 3); - AND32ItoR(gprT1, vuIndex ? 0x3ff8 : 0xff8); + AND32ItoR(gprT1, isVU1 ? 0x3ff8 : 0xff8); MOV32RtoM((uptr)&mVU->branch, gprT1); MOV32ItoR(gprT1, bSaveAddr); - mVUallocVIb(gprT1, _It_); + mVUallocVIb(mVU, gprT1, _It_); } pass3 { mVUlog("JALR vi%02d, [vi%02d]", _Ft_, _Fs_); } } diff --git a/pcsx2/x86/microVU_Misc.h b/pcsx2/x86/microVU_Misc.h index 695c9ac694..00b0530c6c 100644 --- a/pcsx2/x86/microVU_Misc.h +++ b/pcsx2/x86/microVU_Misc.h @@ -105,7 +105,9 @@ declareAllVariables #define _Tbit_ (1<<27) #define _MDTbit_ 0 //( _Mbit_ | _Dbit_ | _Tbit_ ) // ToDo: Implement this stuff... -#define getVUmem(x) (((vuIndex == 1) ? (x & 0x3ff) : ((x >= 0x400) ? (x & 0x43f) : (x & 0xff))) * 16) +#define isVU1 (mVU == µVU1) +#define getIndex (isVU1 ? 1 : 0) +#define getVUmem(x) (((isVU1) ? (x & 0x3ff) : ((x >= 0x400) ? (x & 0x43f) : (x & 0xff))) * 16) #define offsetSS ((_X) ? (0) : ((_Y) ? (4) : ((_Z) ? 8: 12))) #define offsetReg ((_X) ? (0) : ((_Y) ? (1) : ((_Z) ? 2: 3))) @@ -136,15 +138,19 @@ declareAllVariables #define gprF2 6 // Status Flag 2 #define gprF3 7 // Status Flag 3 -// Template Stuff -#define mVUx (vuIndex ? µVU1 : µVU0) -#define microVUt(aType) template __forceinline aType -#define microVUx(aType) template aType -#define microVUf(aType) template aType -#define microVUq(aType) template __forceinline aType - // Function Params +#define mP microVU* mVU, int recPass +#define mV microVU* mVU #define mF int recPass +#define mX mVU, recPass + +// Function/Template Stuff +#define mVUx (vuIndex ? µVU1 : µVU0) +#define mVUop(opName) void opName (mP) +#define microVUt(aType) __forceinline aType +#define microVUx(aType) template aType +#define microVUf(aType) template __forceinline aType + // Define Passes #define pass1 if (recPass == 0) @@ -176,9 +182,9 @@ declareAllVariables #define setCode() { mVU->code = curI; } #define incPC(x) { iPC = ((iPC + x) & (mVU->progSize-1)); setCode(); } #define incPC2(x) { iPC = ((iPC + x) & (mVU->progSize-1)); } -#define incCycles(x) { mVUincCycles(x); } -#define bSaveAddr (((xPC + (2 * 8)) & ((vuIndex) ? 0x3ff8:0xff8)) / 8) -#define branchAddr ((xPC + 8 + (_Imm11_ * 8)) & ((vuIndex) ? 0x3ff8:0xff8)) +#define incCycles(x) { mVUincCycles(mVU, x); } +#define bSaveAddr (((xPC + (2 * 8)) & ((isVU1) ? 0x3ff8:0xff8)) / 8) +#define branchAddr ((xPC + 8 + (_Imm11_ * 8)) & ((isVU1) ? 0x3ff8 : 0xff8)) #define shufflePQ (((mVU->p) ? 0xb0 : 0xe0) | ((mVU->q) ? 0x01 : 0x04)) #define Rmem (uptr)&mVU->regs->VI[REG_R].UL #define Roffset (uptr)&mVU->regs->VI[9].UL @@ -288,7 +294,7 @@ declareAllVariables // Program Logging... #ifdef mVUlogProg -#define mVUlog __mVULog +#define mVUlog ((isVU1) ? __mVULog<1> : __mVULog<0>) #define mVUdumpProg __mVUdumpProgram #else #define mVUlog 0&& @@ -309,7 +315,8 @@ declareAllVariables uptr diff = ptr - start; \ if (diff >= limit) { \ Console::Error("microVU Error: Program went over its cache limit. Size = 0x%x", params diff); \ - mVUreset(); \ + if (!isVU1) mVUreset<0>(); \ + else mVUreset<1>(); \ } \ } diff --git a/pcsx2/x86/microVU_Misc.inl b/pcsx2/x86/microVU_Misc.inl index 8584169a41..4d3ddc8fba 100644 --- a/pcsx2/x86/microVU_Misc.inl +++ b/pcsx2/x86/microVU_Misc.inl @@ -23,7 +23,7 @@ //------------------------------------------------------------------ // Used for Result Clamping -microVUx(void) mVUclamp1(int reg, int regT1, int xyzw) { +void mVUclamp1(int reg, int regT1, int xyzw) { switch (xyzw) { case 1: case 2: case 4: case 8: SSE_MINSS_XMM_to_XMM(reg, xmmMax); @@ -37,7 +37,7 @@ microVUx(void) mVUclamp1(int reg, int regT1, int xyzw) { } // Used for Operand Clamping -microVUx(void) mVUclamp2(int reg, int regT1, int xyzw) { +void mVUclamp2(int reg, int regT1, int xyzw) { if (CHECK_VU_SIGN_OVERFLOW) { switch (xyzw) { case 1: case 2: case 4: case 8: @@ -56,14 +56,14 @@ microVUx(void) mVUclamp2(int reg, int regT1, int xyzw) { break; } } - else mVUclamp1(reg, regT1, xyzw); + else mVUclamp1(reg, regT1, xyzw); } //------------------------------------------------------------------ // Micro VU - Misc Functions //------------------------------------------------------------------ -microVUx(void) mVUunpack_xyzw(int dstreg, int srcreg, int xyzw) { +void mVUunpack_xyzw(int dstreg, int srcreg, int xyzw) { switch ( xyzw ) { case 0: SSE2_PSHUFD_XMM_to_XMM(dstreg, srcreg, 0x00); break; case 1: SSE2_PSHUFD_XMM_to_XMM(dstreg, srcreg, 0x55); break; @@ -72,7 +72,7 @@ microVUx(void) mVUunpack_xyzw(int dstreg, int srcreg, int xyzw) { } } -microVUx(void) mVUloadReg(int reg, uptr offset, int xyzw) { +void mVUloadReg(int reg, uptr offset, int xyzw) { switch( xyzw ) { case 8: SSE_MOVSS_M32_to_XMM(reg, offset); break; // X case 4: SSE_MOVSS_M32_to_XMM(reg, offset+4); break; // Y @@ -82,7 +82,7 @@ microVUx(void) mVUloadReg(int reg, uptr offset, int xyzw) { } } -microVUx(void) mVUloadReg2(int reg, int gprReg, uptr offset, int xyzw) { +void mVUloadReg2(int reg, int gprReg, uptr offset, int xyzw) { switch( xyzw ) { case 8: SSE_MOVSS_Rm_to_XMM(reg, gprReg, offset); break; // X case 4: SSE_MOVSS_Rm_to_XMM(reg, gprReg, offset+4); break; // Y @@ -93,7 +93,7 @@ microVUx(void) mVUloadReg2(int reg, int gprReg, uptr offset, int xyzw) { } // Modifies the Source Reg! -microVUx(void) mVUsaveReg(int reg, uptr offset, int xyzw, bool modXYZW) { +void mVUsaveReg(int reg, uptr offset, int xyzw, bool modXYZW) { /*SSE_MOVAPS_M128_to_XMM(xmmT2, offset); if (modXYZW && (xyzw == 8 || xyzw == 4 || xyzw == 2 || xyzw == 1)) { mVUunpack_xyzw(reg, reg, 0); @@ -135,13 +135,13 @@ microVUx(void) mVUsaveReg(int reg, uptr offset, int xyzw, bool modXYZW) { SSE_MOVHLPS_XMM_to_XMM(reg, reg); SSE_MOVSS_XMM_to_M32(offset+8, reg); break; // XYZ - case 4: if (!modXYZW) mVUunpack_xyzw(reg, reg, 1); + case 4: if (!modXYZW) mVUunpack_xyzw(reg, reg, 1); SSE_MOVSS_XMM_to_M32(offset+4, reg); break; // Y - case 2: if (!modXYZW) mVUunpack_xyzw(reg, reg, 2); + case 2: if (!modXYZW) mVUunpack_xyzw(reg, reg, 2); SSE_MOVSS_XMM_to_M32(offset+8, reg); break; // Z - case 1: if (!modXYZW) mVUunpack_xyzw(reg, reg, 3); + case 1: if (!modXYZW) mVUunpack_xyzw(reg, reg, 3); SSE_MOVSS_XMM_to_M32(offset+12, reg); break; // W case 8: SSE_MOVSS_XMM_to_M32(offset, reg); break; // X @@ -152,7 +152,7 @@ microVUx(void) mVUsaveReg(int reg, uptr offset, int xyzw, bool modXYZW) { } // Modifies the Source Reg! -microVUx(void) mVUsaveReg2(int reg, int gprReg, u32 offset, int xyzw) { +void mVUsaveReg2(int reg, int gprReg, u32 offset, int xyzw) { /*SSE_MOVAPSRmtoR(xmmT2, gprReg, offset); if (xyzw == 8 || xyzw == 4 || xyzw == 2 || xyzw == 1) { mVUunpack_xyzw(reg, reg, 0); @@ -262,8 +262,8 @@ void mVUmergeRegs(int dest, int src, int xyzw) { } // Transforms the Address in gprReg to valid VU0/VU1 Address -microVUt(void) mVUaddrFix(int gprReg) { - if (vuIndex) { +microVUt(void) mVUaddrFix(mV, int gprReg) { + if (mVU == µVU1) { AND32ItoR(gprReg, 0x3ff); // wrap around SHL32ItoR(gprReg, 4); } @@ -281,15 +281,13 @@ microVUt(void) mVUaddrFix(int gprReg) { } // Backup Volatile Regs (EAX, ECX, EDX, MM0~7, XMM0~7, are all volatile according to 32bit Win/Linux ABI) -microVUt(void) mVUbackupRegs() { - microVU* mVU = mVUx; +microVUt(void) mVUbackupRegs(mV) { SSE_MOVAPS_XMM_to_M128((uptr)&mVU->regs->ACC.UL[0], xmmACC); SSE_MOVAPS_XMM_to_M128((uptr)&mVU->xmmPQb[0], xmmPQ); } // Restore Volatile Regs -microVUt(void) mVUrestoreRegs() { - microVU* mVU = mVUx; +microVUt(void) mVUrestoreRegs(mV) { SSE_MOVAPS_M128_to_XMM(xmmACC, (uptr)&mVU->regs->ACC.UL[0]); SSE_MOVAPS_M128_to_XMM(xmmPQ, (uptr)&mVU->xmmPQb[0]); SSE_MOVAPS_M128_to_XMM(xmmMax, (uptr)mVU_maxvals); @@ -298,15 +296,14 @@ microVUt(void) mVUrestoreRegs() { } // Reads entire microProgram and finds out if Status Flag is Used -microVUt(void) mVUcheckSflag(int progIndex) { +microVUt(void) mVUcheckSflag(mV, int progIndex) { if (CHECK_VU_FLAGHACK1) { - microVU* mVU = mVUx; int bFlagInfo = mVUflagInfo; int bCode = mVU->code; mVUsFlagHack = 1; for (u32 i = 0; i < mVU->progSize; i+=2) { mVU->code = mVU->prog.prog[progIndex].data[i]; - mVUopL(3); + mVUopL(mVU, 3); } mVUflagInfo = bFlagInfo; mVU->code = bCode; diff --git a/pcsx2/x86/microVU_Tables.inl b/pcsx2/x86/microVU_Tables.inl index 64d3ac682d..2316c116f9 100644 --- a/pcsx2/x86/microVU_Tables.inl +++ b/pcsx2/x86/microVU_Tables.inl @@ -21,182 +21,182 @@ //------------------------------------------------------------------ // Declarations //------------------------------------------------------------------ -#define mVUgetCode (vuIndex ? microVU1.code : microVU0.code) +#define mVUgetCode (mVU->code) -microVUf(void) mVU_UPPER_FD_00(mF); -microVUf(void) mVU_UPPER_FD_01(mF); -microVUf(void) mVU_UPPER_FD_10(mF); -microVUf(void) mVU_UPPER_FD_11(mF); -microVUf(void) mVULowerOP(mF); -microVUf(void) mVULowerOP_T3_00(mF); -microVUf(void) mVULowerOP_T3_01(mF); -microVUf(void) mVULowerOP_T3_10(mF); -microVUf(void) mVULowerOP_T3_11(mF); -microVUf(void) mVUunknown(mF); +mVUop(mVU_UPPER_FD_00); +mVUop(mVU_UPPER_FD_01); +mVUop(mVU_UPPER_FD_10); +mVUop(mVU_UPPER_FD_11); +mVUop(mVULowerOP); +mVUop(mVULowerOP_T3_00); +mVUop(mVULowerOP_T3_01); +mVUop(mVULowerOP_T3_10); +mVUop(mVULowerOP_T3_11); +mVUop(mVUunknown); //------------------------------------------------------------------ //------------------------------------------------------------------ // Opcode Tables //------------------------------------------------------------------ -#define microVU_LOWER_OPCODE(x) void (*mVULOWER_OPCODE##x [128])(mF) = { \ - mVU_LQ , mVU_SQ , mVUunknown , mVUunknown, \ - mVU_ILW , mVU_ISW , mVUunknown , mVUunknown, \ - mVU_IADDIU , mVU_ISUBIU , mVUunknown , mVUunknown, \ - mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ - mVU_FCEQ , mVU_FCSET , mVU_FCAND , mVU_FCOR, /* 0x10 */ \ - mVU_FSEQ , mVU_FSSET , mVU_FSAND , mVU_FSOR, \ - mVU_FMEQ , mVUunknown , mVU_FMAND , mVU_FMOR, \ - mVU_FCGET , mVUunknown , mVUunknown , mVUunknown, \ - mVU_B , mVU_BAL , mVUunknown , mVUunknown, /* 0x20 */ \ - mVU_JR , mVU_JALR , mVUunknown , mVUunknown, \ - mVU_IBEQ , mVU_IBNE , mVUunknown , mVUunknown, \ - mVU_IBLTZ , mVU_IBGTZ , mVU_IBLEZ , mVU_IBGEZ, \ - mVUunknown , mVUunknown , mVUunknown , mVUunknown, /* 0x30 */ \ - mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ - mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ - mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ - mVULowerOP , mVUunknown , mVUunknown , mVUunknown, /* 0x40*/ \ - mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ - mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ - mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ - mVUunknown , mVUunknown , mVUunknown , mVUunknown, /* 0x50 */ \ - mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ - mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ - mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ - mVUunknown , mVUunknown , mVUunknown , mVUunknown, /* 0x60 */ \ - mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ - mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ - mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ - mVUunknown , mVUunknown , mVUunknown , mVUunknown, /* 0x70 */ \ - mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ - mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ - mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ +#define microVU_LOWER_OPCODE(x) void (*mVULOWER_OPCODE##x [128])(mP) = { \ + mVU_LQ , mVU_SQ , mVUunknown , mVUunknown, \ + mVU_ILW , mVU_ISW , mVUunknown , mVUunknown, \ + mVU_IADDIU , mVU_ISUBIU , mVUunknown , mVUunknown, \ + mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ + mVU_FCEQ , mVU_FCSET , mVU_FCAND , mVU_FCOR, /* 0x10 */ \ + mVU_FSEQ , mVU_FSSET , mVU_FSAND , mVU_FSOR, \ + mVU_FMEQ , mVUunknown , mVU_FMAND , mVU_FMOR, \ + mVU_FCGET , mVUunknown , mVUunknown , mVUunknown, \ + mVU_B , mVU_BAL , mVUunknown , mVUunknown, /* 0x20 */ \ + mVU_JR , mVU_JALR , mVUunknown , mVUunknown, \ + mVU_IBEQ , mVU_IBNE , mVUunknown , mVUunknown, \ + mVU_IBLTZ , mVU_IBGTZ , mVU_IBLEZ , mVU_IBGEZ, \ + mVUunknown , mVUunknown , mVUunknown , mVUunknown, /* 0x30 */ \ + mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ + mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ + mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ + mVULowerOP , mVUunknown , mVUunknown , mVUunknown, /* 0x40*/ \ + mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ + mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ + mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ + mVUunknown , mVUunknown , mVUunknown , mVUunknown, /* 0x50 */ \ + mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ + mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ + mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ + mVUunknown , mVUunknown , mVUunknown , mVUunknown, /* 0x60 */ \ + mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ + mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ + mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ + mVUunknown , mVUunknown , mVUunknown , mVUunknown, /* 0x70 */ \ + mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ + mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ + mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ }; -#define microVU_LowerOP_T3_00_OPCODE(x) void (*mVULowerOP_T3_00_OPCODE##x [32])(mF) = { \ - mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ - mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ - mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ - mVU_MOVE , mVU_LQI , mVU_DIV , mVU_MTIR, \ - mVU_RNEXT , mVUunknown , mVUunknown , mVUunknown, /* 0x10 */ \ - mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ - mVUunknown , mVU_MFP , mVU_XTOP , mVU_XGKICK, \ - mVU_ESADD , mVU_EATANxy, mVU_ESQRT , mVU_ESIN, \ +#define microVU_LowerOP_T3_00_OPCODE(x) void (*mVULowerOP_T3_00_OPCODE##x [32])(mP) = { \ + mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ + mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ + mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ + mVU_MOVE , mVU_LQI , mVU_DIV , mVU_MTIR, \ + mVU_RNEXT , mVUunknown , mVUunknown , mVUunknown, /* 0x10 */ \ + mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ + mVUunknown , mVU_MFP , mVU_XTOP , mVU_XGKICK, \ + mVU_ESADD , mVU_EATANxy , mVU_ESQRT , mVU_ESIN, \ }; -#define microVU_LowerOP_T3_01_OPCODE(x) void (*mVULowerOP_T3_01_OPCODE##x [32])(mF) = { \ - mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ - mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ - mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ - mVU_MR32 , mVU_SQI , mVU_SQRT , mVU_MFIR, \ - mVU_RGET , mVUunknown , mVUunknown , mVUunknown, /* 0x10 */ \ - mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ - mVUunknown , mVUunknown , mVU_XITOP , mVUunknown, \ - mVU_ERSADD , mVU_EATANxz, mVU_ERSQRT , mVU_EATAN, \ +#define microVU_LowerOP_T3_01_OPCODE(x) void (*mVULowerOP_T3_01_OPCODE##x [32])(mP) = { \ + mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ + mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ + mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ + mVU_MR32 , mVU_SQI , mVU_SQRT , mVU_MFIR, \ + mVU_RGET , mVUunknown , mVUunknown , mVUunknown, /* 0x10 */ \ + mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ + mVUunknown , mVUunknown , mVU_XITOP , mVUunknown, \ + mVU_ERSADD , mVU_EATANxz , mVU_ERSQRT , mVU_EATAN, \ }; -#define microVU_LowerOP_T3_10_OPCODE(x) void (*mVULowerOP_T3_10_OPCODE##x [32])(mF) = { \ - mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ - mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ - mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ - mVUunknown , mVU_LQD , mVU_RSQRT , mVU_ILWR, \ - mVU_RINIT , mVUunknown , mVUunknown , mVUunknown, /* 0x10 */ \ - mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ - mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ - mVU_ELENG , mVU_ESUM , mVU_ERCPR , mVU_EEXP, \ +#define microVU_LowerOP_T3_10_OPCODE(x) void (*mVULowerOP_T3_10_OPCODE##x [32])(mP) = { \ + mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ + mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ + mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ + mVUunknown , mVU_LQD , mVU_RSQRT , mVU_ILWR, \ + mVU_RINIT , mVUunknown , mVUunknown , mVUunknown, /* 0x10 */ \ + mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ + mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ + mVU_ELENG , mVU_ESUM , mVU_ERCPR , mVU_EEXP, \ }; -#define microVU_LowerOP_T3_11_OPCODE(x) void (*mVULowerOP_T3_11_OPCODE##x [32])(mF) = { \ - mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ - mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ - mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ - mVUunknown , mVU_SQD , mVU_WAITQ , mVU_ISWR, \ - mVU_RXOR , mVUunknown , mVUunknown , mVUunknown, /* 0x10 */ \ - mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ - mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ - mVU_ERLENG , mVUunknown , mVU_WAITP , mVUunknown, \ +#define microVU_LowerOP_T3_11_OPCODE(x) void (*mVULowerOP_T3_11_OPCODE##x [32])(mP) = { \ + mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ + mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ + mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ + mVUunknown , mVU_SQD , mVU_WAITQ , mVU_ISWR, \ + mVU_RXOR , mVUunknown , mVUunknown , mVUunknown, /* 0x10 */ \ + mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ + mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ + mVU_ERLENG , mVUunknown , mVU_WAITP , mVUunknown, \ }; -#define microVU_LowerOP_OPCODE(x) void (*mVULowerOP_OPCODE##x [64])(mF) = { \ - mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ - mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ - mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ - mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ - mVUunknown , mVUunknown , mVUunknown , mVUunknown, /* 0x10 */ \ - mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ - mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ - mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ - mVUunknown , mVUunknown , mVUunknown , mVUunknown, /* 0x20 */ \ - mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ - mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ - mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ - mVU_IADD , mVU_ISUB , mVU_IADDI , mVUunknown, /* 0x30 */ \ - mVU_IAND , mVU_IOR , mVUunknown , mVUunknown, \ - mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ - mVULowerOP_T3_00, mVULowerOP_T3_01, mVULowerOP_T3_10, mVULowerOP_T3_11, \ +#define microVU_LowerOP_OPCODE(x) void (*mVULowerOP_OPCODE##x [64])(mP) = { \ + mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ + mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ + mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ + mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ + mVUunknown , mVUunknown , mVUunknown , mVUunknown, /* 0x10 */ \ + mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ + mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ + mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ + mVUunknown , mVUunknown , mVUunknown , mVUunknown, /* 0x20 */ \ + mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ + mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ + mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ + mVU_IADD , mVU_ISUB , mVU_IADDI , mVUunknown, /* 0x30 */ \ + mVU_IAND , mVU_IOR , mVUunknown , mVUunknown, \ + mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ + mVULowerOP_T3_00, mVULowerOP_T3_01, mVULowerOP_T3_10, mVULowerOP_T3_11, \ }; -#define microVU_UPPER_OPCODE(x) void (*mVU_UPPER_OPCODE##x [64])(mF) = { \ - mVU_ADDx , mVU_ADDy , mVU_ADDz , mVU_ADDw, \ - mVU_SUBx , mVU_SUBy , mVU_SUBz , mVU_SUBw, \ - mVU_MADDx , mVU_MADDy , mVU_MADDz , mVU_MADDw, \ - mVU_MSUBx , mVU_MSUBy , mVU_MSUBz , mVU_MSUBw, \ - mVU_MAXx , mVU_MAXy , mVU_MAXz , mVU_MAXw, /* 0x10 */ \ - mVU_MINIx , mVU_MINIy , mVU_MINIz , mVU_MINIw, \ - mVU_MULx , mVU_MULy , mVU_MULz , mVU_MULw, \ - mVU_MULq , mVU_MAXi , mVU_MULi , mVU_MINIi, \ - mVU_ADDq , mVU_MADDq , mVU_ADDi , mVU_MADDi, /* 0x20 */ \ - mVU_SUBq , mVU_MSUBq , mVU_SUBi , mVU_MSUBi, \ - mVU_ADD , mVU_MADD , mVU_MUL , mVU_MAX, \ - mVU_SUB , mVU_MSUB , mVU_OPMSUB , mVU_MINI, \ - mVUunknown , mVUunknown , mVUunknown , mVUunknown, /* 0x30 */ \ - mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ - mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ - mVU_UPPER_FD_00, mVU_UPPER_FD_01, mVU_UPPER_FD_10, mVU_UPPER_FD_11, \ +#define microVU_UPPER_OPCODE(x) void (*mVU_UPPER_OPCODE##x [64])(mP) = { \ + mVU_ADDx , mVU_ADDy , mVU_ADDz , mVU_ADDw, \ + mVU_SUBx , mVU_SUBy , mVU_SUBz , mVU_SUBw, \ + mVU_MADDx , mVU_MADDy , mVU_MADDz , mVU_MADDw, \ + mVU_MSUBx , mVU_MSUBy , mVU_MSUBz , mVU_MSUBw, \ + mVU_MAXx , mVU_MAXy , mVU_MAXz , mVU_MAXw, /* 0x10 */ \ + mVU_MINIx , mVU_MINIy , mVU_MINIz , mVU_MINIw, \ + mVU_MULx , mVU_MULy , mVU_MULz , mVU_MULw, \ + mVU_MULq , mVU_MAXi , mVU_MULi , mVU_MINIi, \ + mVU_ADDq , mVU_MADDq , mVU_ADDi , mVU_MADDi, /* 0x20 */ \ + mVU_SUBq , mVU_MSUBq , mVU_SUBi , mVU_MSUBi, \ + mVU_ADD , mVU_MADD , mVU_MUL , mVU_MAX, \ + mVU_SUB , mVU_MSUB , mVU_OPMSUB , mVU_MINI, \ + mVUunknown , mVUunknown , mVUunknown , mVUunknown, /* 0x30 */ \ + mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ + mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ + mVU_UPPER_FD_00, mVU_UPPER_FD_01, mVU_UPPER_FD_10, mVU_UPPER_FD_11, \ }; -#define microVU_UPPER_FD_00_TABLE(x) void (*mVU_UPPER_FD_00_TABLE##x [32])(mF) = { \ - mVU_ADDAx , mVU_SUBAx , mVU_MADDAx , mVU_MSUBAx, \ - mVU_ITOF0 , mVU_FTOI0 , mVU_MULAx , mVU_MULAq, \ - mVU_ADDAq , mVU_SUBAq , mVU_ADDA , mVU_SUBA, \ - mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ - mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ - mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ - mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ - mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ +#define microVU_UPPER_FD_00_TABLE(x) void (*mVU_UPPER_FD_00_TABLE##x [32])(mP) = { \ + mVU_ADDAx , mVU_SUBAx , mVU_MADDAx , mVU_MSUBAx, \ + mVU_ITOF0 , mVU_FTOI0 , mVU_MULAx , mVU_MULAq, \ + mVU_ADDAq , mVU_SUBAq , mVU_ADDA , mVU_SUBA, \ + mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ + mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ + mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ + mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ + mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ }; -#define microVU_UPPER_FD_01_TABLE(x) void (* mVU_UPPER_FD_01_TABLE##x [32])(mF) = { \ - mVU_ADDAy , mVU_SUBAy , mVU_MADDAy , mVU_MSUBAy, \ - mVU_ITOF4 , mVU_FTOI4 , mVU_MULAy , mVU_ABS, \ - mVU_MADDAq , mVU_MSUBAq , mVU_MADDA , mVU_MSUBA, \ - mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ - mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ - mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ - mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ - mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ +#define microVU_UPPER_FD_01_TABLE(x) void (* mVU_UPPER_FD_01_TABLE##x [32])(mP) = { \ + mVU_ADDAy , mVU_SUBAy , mVU_MADDAy , mVU_MSUBAy, \ + mVU_ITOF4 , mVU_FTOI4 , mVU_MULAy , mVU_ABS, \ + mVU_MADDAq , mVU_MSUBAq , mVU_MADDA , mVU_MSUBA, \ + mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ + mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ + mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ + mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ + mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ }; -#define microVU_UPPER_FD_10_TABLE(x) void (* mVU_UPPER_FD_10_TABLE##x [32])(mF) = { \ - mVU_ADDAz , mVU_SUBAz , mVU_MADDAz , mVU_MSUBAz, \ - mVU_ITOF12 , mVU_FTOI12 , mVU_MULAz , mVU_MULAi, \ - mVU_ADDAi , mVU_SUBAi , mVU_MULA , mVU_OPMULA, \ - mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ - mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ - mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ - mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ - mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ +#define microVU_UPPER_FD_10_TABLE(x) void (* mVU_UPPER_FD_10_TABLE##x [32])(mP) = { \ + mVU_ADDAz , mVU_SUBAz , mVU_MADDAz , mVU_MSUBAz, \ + mVU_ITOF12 , mVU_FTOI12 , mVU_MULAz , mVU_MULAi, \ + mVU_ADDAi , mVU_SUBAi , mVU_MULA , mVU_OPMULA, \ + mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ + mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ + mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ + mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ + mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ }; -#define microVU_UPPER_FD_11_TABLE(x) void (* mVU_UPPER_FD_11_TABLE##x [32])(mF) = { \ - mVU_ADDAw , mVU_SUBAw , mVU_MADDAw , mVU_MSUBAw, \ - mVU_ITOF15 , mVU_FTOI15 , mVU_MULAw , mVU_CLIP, \ - mVU_MADDAi , mVU_MSUBAi , mVUunknown , mVU_NOP, \ - mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ - mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ - mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ - mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ - mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ +#define microVU_UPPER_FD_11_TABLE(x) void (* mVU_UPPER_FD_11_TABLE##x [32])(mP) = { \ + mVU_ADDAw , mVU_SUBAw , mVU_MADDAw , mVU_MSUBAw, \ + mVU_ITOF15 , mVU_FTOI15 , mVU_MULAw , mVU_CLIP, \ + mVU_MADDAi , mVU_MSUBAi , mVUunknown , mVU_NOP, \ + mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ + mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ + mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ + mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ + mVUunknown , mVUunknown , mVUunknown , mVUunknown, \ }; //------------------------------------------------------------------ @@ -218,29 +218,27 @@ microVU_UPPER_FD_10_TABLE(x) \ microVU_UPPER_FD_11_TABLE(x) mVUcreateTable(0) -mVUcreateTable(1) //------------------------------------------------------------------ // Table Functions //------------------------------------------------------------------ -#define doTableStuff(tableName, args) { \ - if (vuIndex) tableName##1[ args ](recPass); \ - else tableName##0[ args ](recPass); \ +#define doTableStuff(tableName, args) { \ + tableName##0[ args ](mX); \ } -microVUf(void) mVU_UPPER_FD_00(mF) { doTableStuff(mVU_UPPER_FD_00_TABLE, ((mVUgetCode >> 6) & 0x1f)); } -microVUf(void) mVU_UPPER_FD_01(mF) { doTableStuff(mVU_UPPER_FD_01_TABLE, ((mVUgetCode >> 6) & 0x1f)); } -microVUf(void) mVU_UPPER_FD_10(mF) { doTableStuff(mVU_UPPER_FD_10_TABLE, ((mVUgetCode >> 6) & 0x1f)); } -microVUf(void) mVU_UPPER_FD_11(mF) { doTableStuff(mVU_UPPER_FD_11_TABLE, ((mVUgetCode >> 6) & 0x1f)); } -microVUf(void) mVULowerOP(mF) { doTableStuff(mVULowerOP_OPCODE, (mVUgetCode & 0x3f)); } -microVUf(void) mVULowerOP_T3_00(mF) { doTableStuff(mVULowerOP_T3_00_OPCODE, ((mVUgetCode >> 6) & 0x1f)); } -microVUf(void) mVULowerOP_T3_01(mF) { doTableStuff(mVULowerOP_T3_01_OPCODE, ((mVUgetCode >> 6) & 0x1f)); } -microVUf(void) mVULowerOP_T3_10(mF) { doTableStuff(mVULowerOP_T3_10_OPCODE, ((mVUgetCode >> 6) & 0x1f)); } -microVUf(void) mVULowerOP_T3_11(mF) { doTableStuff(mVULowerOP_T3_11_OPCODE, ((mVUgetCode >> 6) & 0x1f)); } -microVUf(void) mVUopU(mF) { doTableStuff(mVU_UPPER_OPCODE, (mVUgetCode & 0x3f)); } // Gets Upper Opcode -microVUf(void) mVUopL(mF) { doTableStuff(mVULOWER_OPCODE, (mVUgetCode >> 25)); } // Gets Lower Opcode -microVUf(void) mVUunknown(mF) { - pass2 { SysPrintf("microVU%d: Unknown Micro VU opcode called (%x)\n", vuIndex, mVUgetCode); } +mVUop(mVU_UPPER_FD_00) { doTableStuff(mVU_UPPER_FD_00_TABLE, ((mVUgetCode >> 6) & 0x1f)); } +mVUop(mVU_UPPER_FD_01) { doTableStuff(mVU_UPPER_FD_01_TABLE, ((mVUgetCode >> 6) & 0x1f)); } +mVUop(mVU_UPPER_FD_10) { doTableStuff(mVU_UPPER_FD_10_TABLE, ((mVUgetCode >> 6) & 0x1f)); } +mVUop(mVU_UPPER_FD_11) { doTableStuff(mVU_UPPER_FD_11_TABLE, ((mVUgetCode >> 6) & 0x1f)); } +mVUop(mVULowerOP) { doTableStuff(mVULowerOP_OPCODE, (mVUgetCode & 0x3f)); } +mVUop(mVULowerOP_T3_00) { doTableStuff(mVULowerOP_T3_00_OPCODE, ((mVUgetCode >> 6) & 0x1f)); } +mVUop(mVULowerOP_T3_01) { doTableStuff(mVULowerOP_T3_01_OPCODE, ((mVUgetCode >> 6) & 0x1f)); } +mVUop(mVULowerOP_T3_10) { doTableStuff(mVULowerOP_T3_10_OPCODE, ((mVUgetCode >> 6) & 0x1f)); } +mVUop(mVULowerOP_T3_11) { doTableStuff(mVULowerOP_T3_11_OPCODE, ((mVUgetCode >> 6) & 0x1f)); } +mVUop(mVUopU) { doTableStuff(mVU_UPPER_OPCODE, (mVUgetCode & 0x3f)); } // Gets Upper Opcode +mVUop(mVUopL) { doTableStuff(mVULOWER_OPCODE, (mVUgetCode >> 25)); } // Gets Lower Opcode +mVUop(mVUunknown) { + pass2 { SysPrintf("microVU%d: Unknown Micro VU opcode called (%x)\n", getIndex, mVUgetCode); } pass3 { mVUlog("Unknown", mVUgetCode); } } diff --git a/pcsx2/x86/microVU_Upper.inl b/pcsx2/x86/microVU_Upper.inl index ca1b31b4ba..30591004f4 100644 --- a/pcsx2/x86/microVU_Upper.inl +++ b/pcsx2/x86/microVU_Upper.inl @@ -27,8 +27,7 @@ #define SHIFT_XYZW(gprReg) { if (_XYZW_SS && modXYZW && !_W) { SHL32ItoR(gprReg, ADD_XYZW); } } // Note: If modXYZW is true, then it adjusts XYZW for Single Scalar operations -microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modXYZW) { - microVU* mVU = mVUx; +microVUt(void) mVUupdateFlags(mV, int reg, int regT1, int regT2, int xyzw, bool modXYZW) { int sReg, mReg = gprT1; static u8 *pjmp, *pjmp2; static const u16 flipMask[16] = {0, 8, 4, 12, 2, 10, 6, 14, 1, 9, 5, 13, 3, 11, 7, 15}; @@ -40,7 +39,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX else { SSE2_PSHUFD_XMM_to_XMM(regT1, reg, 0x1B); } // Flip wzyx to xyzw if (doStatus) { getFlagReg(sReg, fsInstance); // Set sReg to valid GPR by Cur Flag Instance - mVUallocSFLAGa(sReg, fpsInstance); // Get Prev Status Flag + mVUallocSFLAGa(sReg, fpsInstance); // Get Prev Status Flag AND32ItoR(sReg, 0xff0); // Keep Sticky and D/I flags } @@ -73,7 +72,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX if (_XYZW_SS && doStatus) x86SetJ8(pjmp2); // If we skipped the Zero Flag Checking, return here - if (doMac) mVUallocMFLAGb(mReg, fmInstance); // Set Mac Flag + if (doMac) mVUallocMFLAGb(mVU, mReg, fmInstance); // Set Mac Flag } //------------------------------------------------------------------ @@ -82,95 +81,88 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX // FMAC1 - Normal FMAC Opcodes #define mVU_FMAC1(operation, OPname) { \ - microVU* mVU = mVUx; \ - pass1 { mVUanalyzeFMAC1(_Fd_, _Fs_, _Ft_); } \ + pass1 { mVUanalyzeFMAC1(mVU, _Fd_, _Fs_, _Ft_); } \ pass2 { \ int Fd, Fs, Ft; \ - mVUallocFMAC1a(Fd, Fs, Ft); \ + mVUallocFMAC1a(mVU, Fd, Fs, Ft); \ if (_XYZW_SS) SSE_##operation##SS_XMM_to_XMM(Fs, Ft); \ else SSE_##operation##PS_XMM_to_XMM(Fs, Ft); \ - mVUupdateFlags(Fd, xmmT1, xmmT2, _X_Y_Z_W, 1); \ - mVUallocFMAC1b(Fd); \ + mVUupdateFlags(mVU, Fd, xmmT1, xmmT2, _X_Y_Z_W, 1); \ + mVUallocFMAC1b(mVU, Fd); \ } \ pass3 { mVUlog(OPname); mVUlogFd(); mVUlogFt(); } \ } // FMAC3 - BC(xyzw) FMAC Opcodes #define mVU_FMAC3(operation, OPname) { \ - microVU* mVU = mVUx; \ - pass1 { mVUanalyzeFMAC3(_Fd_, _Fs_, _Ft_); } \ + pass1 { mVUanalyzeFMAC3(mVU, _Fd_, _Fs_, _Ft_); } \ pass2 { \ int Fd, Fs, Ft; \ - mVUallocFMAC3a(Fd, Fs, Ft); \ + mVUallocFMAC3a(mVU, Fd, Fs, Ft); \ if (_XYZW_SS) SSE_##operation##SS_XMM_to_XMM(Fs, Ft); \ else SSE_##operation##PS_XMM_to_XMM(Fs, Ft); \ - mVUupdateFlags(Fd, xmmT1, xmmT2, _X_Y_Z_W, 1); \ - mVUallocFMAC3b(Fd); \ + mVUupdateFlags(mVU, Fd, xmmT1, xmmT2, _X_Y_Z_W, 1); \ + mVUallocFMAC3b(mVU, Fd); \ } \ pass3 { mVUlog(OPname); mVUlogFd(); mVUlogBC(); } \ } // FMAC4 - FMAC Opcodes Storing Result to ACC #define mVU_FMAC4(operation, OPname) { \ - microVU* mVU = mVUx; \ - pass1 { mVUanalyzeFMAC1(0, _Fs_, _Ft_); } \ + pass1 { mVUanalyzeFMAC1(mVU, 0, _Fs_, _Ft_); } \ pass2 { \ int ACC, Fs, Ft; \ - mVUallocFMAC4a(ACC, Fs, Ft); \ + mVUallocFMAC4a(mVU, ACC, Fs, Ft); \ if (_X_Y_Z_W == 8) SSE_##operation##SS_XMM_to_XMM(Fs, Ft); \ else SSE_##operation##PS_XMM_to_XMM(Fs, Ft); \ - mVUupdateFlags(Fs, xmmT1, xmmT2, _X_Y_Z_W, 0); \ - mVUallocFMAC4b(ACC, Fs); \ + mVUupdateFlags(mVU, Fs, xmmT1, xmmT2, _X_Y_Z_W, 0); \ + mVUallocFMAC4b(mVU, ACC, Fs); \ } \ pass3 { mVUlog(OPname); mVUlogACC(); mVUlogFt(); } \ } // FMAC5 - FMAC BC(xyzw) Opcodes Storing Result to ACC #define mVU_FMAC5(operation, OPname) { \ - microVU* mVU = mVUx; \ - pass1 { mVUanalyzeFMAC3(0, _Fs_, _Ft_); } \ + pass1 { mVUanalyzeFMAC3(mVU, 0, _Fs_, _Ft_); } \ pass2 { \ int ACC, Fs, Ft; \ - mVUallocFMAC5a(ACC, Fs, Ft); \ + mVUallocFMAC5a(mVU, ACC, Fs, Ft); \ if (_X_Y_Z_W == 8) SSE_##operation##SS_XMM_to_XMM(Fs, Ft); \ else SSE_##operation##PS_XMM_to_XMM(Fs, Ft); \ - mVUupdateFlags(Fs, xmmT1, xmmT2, _X_Y_Z_W, 0); \ - mVUallocFMAC5b(ACC, Fs); \ + mVUupdateFlags(mVU, Fs, xmmT1, xmmT2, _X_Y_Z_W, 0); \ + mVUallocFMAC5b(mVU, ACC, Fs); \ } \ pass3 { mVUlog(OPname); mVUlogACC(); mVUlogBC(); } \ } // FMAC6 - Normal FMAC Opcodes (I Reg) #define mVU_FMAC6(operation, OPname) { \ - microVU* mVU = mVUx; \ - pass1 { mVUanalyzeFMAC1(_Fd_, _Fs_, 0); } \ + pass1 { mVUanalyzeFMAC1(mVU, _Fd_, _Fs_, 0); } \ pass2 { \ int Fd, Fs, Ft; \ - mVUallocFMAC6a(Fd, Fs, Ft); \ + mVUallocFMAC6a(mVU, Fd, Fs, Ft); \ if (_XYZW_SS) SSE_##operation##SS_XMM_to_XMM(Fs, Ft); \ else SSE_##operation##PS_XMM_to_XMM(Fs, Ft); \ - mVUupdateFlags(Fd, xmmT1, xmmT2, _X_Y_Z_W, 1); \ - mVUallocFMAC6b(Fd); \ + mVUupdateFlags(mVU, Fd, xmmT1, xmmT2, _X_Y_Z_W, 1); \ + mVUallocFMAC6b(mVU, Fd); \ } \ pass3 { mVUlog(OPname); mVUlogFd(); mVUlogI(); } \ } // FMAC7 - FMAC Opcodes Storing Result to ACC (I Reg) #define mVU_FMAC7(operation, OPname) { \ - microVU* mVU = mVUx; \ - pass1 { mVUanalyzeFMAC1(0, _Fs_, 0); } \ + pass1 { mVUanalyzeFMAC1(mVU, 0, _Fs_, 0); } \ pass2 { \ int ACC, Fs, Ft; \ - mVUallocFMAC7a(ACC, Fs, Ft); \ + mVUallocFMAC7a(mVU, ACC, Fs, Ft); \ if (_X_Y_Z_W == 8) SSE_##operation##SS_XMM_to_XMM(Fs, Ft); \ else SSE_##operation##PS_XMM_to_XMM(Fs, Ft); \ - mVUupdateFlags(Fs, xmmT1, xmmT2, _X_Y_Z_W, 0); \ - mVUallocFMAC7b(ACC, Fs); \ + mVUupdateFlags(mVU, Fs, xmmT1, xmmT2, _X_Y_Z_W, 0); \ + mVUallocFMAC7b(mVU, ACC, Fs); \ } \ pass3 { mVUlog(OPname); mVUlogACC(); mVUlogI(); } \ } // FMAC8 - MADD FMAC Opcode Storing Result to Fd #define mVU_FMAC8(operation, OPname) { \ - microVU* mVU = mVUx; \ - pass1 { mVUanalyzeFMAC1(_Fd_, _Fs_, _Ft_); } \ + pass1 { mVUanalyzeFMAC1(mVU, _Fd_, _Fs_, _Ft_); } \ pass2 { \ int Fd, ACC, Fs, Ft; \ - mVUallocFMAC8a(Fd, ACC, Fs, Ft); \ + mVUallocFMAC8a(mVU, Fd, ACC, Fs, Ft); \ if (_X_Y_Z_W == 8) { \ SSE_MULSS_XMM_to_XMM(Fs, Ft); \ SSE_##operation##SS_XMM_to_XMM(Fs, ACC); \ @@ -179,18 +171,17 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX SSE_MULPS_XMM_to_XMM(Fs, Ft); \ SSE_##operation##PS_XMM_to_XMM(Fs, ACC); \ } \ - mVUupdateFlags(Fd, xmmT1, xmmT2, _X_Y_Z_W, 0); \ - mVUallocFMAC8b(Fd); \ + mVUupdateFlags(mVU, Fd, xmmT1, xmmT2, _X_Y_Z_W, 0); \ + mVUallocFMAC8b(mVU, Fd); \ } \ pass3 { mVUlog(OPname); mVUlogFd(); mVUlogFt(); } \ } // FMAC9 - MSUB FMAC Opcode Storing Result to Fd #define mVU_FMAC9(operation, OPname) { \ - microVU* mVU = mVUx; \ - pass1 { mVUanalyzeFMAC1(_Fd_, _Fs_, _Ft_); } \ + pass1 { mVUanalyzeFMAC1(mVU, _Fd_, _Fs_, _Ft_); } \ pass2 { \ int Fd, ACC, Fs, Ft; \ - mVUallocFMAC9a(Fd, ACC, Fs, Ft); \ + mVUallocFMAC9a(mVU, Fd, ACC, Fs, Ft); \ if (_X_Y_Z_W == 8) { \ SSE_MULSS_XMM_to_XMM(Fs, Ft); \ SSE_##operation##SS_XMM_to_XMM(ACC, Fs); \ @@ -199,18 +190,17 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX SSE_MULPS_XMM_to_XMM(Fs, Ft); \ SSE_##operation##PS_XMM_to_XMM(ACC, Fs); \ } \ - mVUupdateFlags(Fd, Fs, xmmT2, _X_Y_Z_W, 0); \ - mVUallocFMAC9b(Fd); \ + mVUupdateFlags(mVU, Fd, Fs, xmmT2, _X_Y_Z_W, 0); \ + mVUallocFMAC9b(mVU, Fd); \ } \ pass3 { mVUlog(OPname); mVUlogFd(); mVUlogFt(); } \ } // FMAC10 - MADD FMAC BC(xyzw) Opcode Storing Result to Fd #define mVU_FMAC10(operation, OPname) { \ - microVU* mVU = mVUx; \ - pass1 { mVUanalyzeFMAC3(_Fd_, _Fs_, _Ft_); } \ + pass1 { mVUanalyzeFMAC3(mVU, _Fd_, _Fs_, _Ft_); } \ pass2 { \ int Fd, ACC, Fs, Ft; \ - mVUallocFMAC10a(Fd, ACC, Fs, Ft); \ + mVUallocFMAC10a(mVU, Fd, ACC, Fs, Ft); \ if (_X_Y_Z_W == 8) { \ SSE_MULSS_XMM_to_XMM(Fs, Ft); \ SSE_##operation##SS_XMM_to_XMM(Fs, ACC); \ @@ -219,18 +209,17 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX SSE_MULPS_XMM_to_XMM(Fs, Ft); \ SSE_##operation##PS_XMM_to_XMM(Fs, ACC); \ } \ - mVUupdateFlags(Fd, xmmT1, xmmT2, _X_Y_Z_W, 0); \ - mVUallocFMAC10b(Fd); \ + mVUupdateFlags(mVU, Fd, xmmT1, xmmT2, _X_Y_Z_W, 0); \ + mVUallocFMAC10b(mVU, Fd); \ } \ pass3 { mVUlog(OPname); mVUlogFd(); mVUlogBC(); } \ } // FMAC11 - MSUB FMAC BC(xyzw) Opcode Storing Result to Fd #define mVU_FMAC11(operation, OPname) { \ - microVU* mVU = mVUx; \ - pass1 { mVUanalyzeFMAC3(_Fd_, _Fs_, _Ft_); } \ + pass1 { mVUanalyzeFMAC3(mVU, _Fd_, _Fs_, _Ft_); } \ pass2 { \ int Fd, ACC, Fs, Ft; \ - mVUallocFMAC11a(Fd, ACC, Fs, Ft); \ + mVUallocFMAC11a(mVU, Fd, ACC, Fs, Ft); \ if (_X_Y_Z_W == 8) { \ SSE_MULSS_XMM_to_XMM(Fs, Ft); \ SSE_##operation##SS_XMM_to_XMM(ACC, Fs); \ @@ -239,18 +228,17 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX SSE_MULPS_XMM_to_XMM(Fs, Ft); \ SSE_##operation##PS_XMM_to_XMM(ACC, Fs); \ } \ - mVUupdateFlags(Fd, Fs, xmmT2, _X_Y_Z_W, 0); \ - mVUallocFMAC11b(Fd); \ + mVUupdateFlags(mVU, Fd, Fs, xmmT2, _X_Y_Z_W, 0); \ + mVUallocFMAC11b(mVU, Fd); \ } \ pass3 { mVUlog(OPname); mVUlogFd(); mVUlogBC(); } \ } // FMAC12 - MADD FMAC Opcode Storing Result to Fd (I Reg) #define mVU_FMAC12(operation, OPname) { \ - microVU* mVU = mVUx; \ - pass1 { mVUanalyzeFMAC1(_Fd_, _Fs_, 0); } \ + pass1 { mVUanalyzeFMAC1(mVU, _Fd_, _Fs_, 0); } \ pass2 { \ int Fd, ACC, Fs, Ft; \ - mVUallocFMAC12a(Fd, ACC, Fs, Ft); \ + mVUallocFMAC12a(mVU, Fd, ACC, Fs, Ft); \ if (_X_Y_Z_W == 8) { \ SSE_MULSS_XMM_to_XMM(Fs, Ft); \ SSE_##operation##SS_XMM_to_XMM(Fs, ACC); \ @@ -259,18 +247,17 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX SSE_MULPS_XMM_to_XMM(Fs, Ft); \ SSE_##operation##PS_XMM_to_XMM(Fs, ACC); \ } \ - mVUupdateFlags(Fd, xmmT1, xmmT2, _X_Y_Z_W, 0); \ - mVUallocFMAC12b(Fd); \ + mVUupdateFlags(mVU, Fd, xmmT1, xmmT2, _X_Y_Z_W, 0); \ + mVUallocFMAC12b(mVU, Fd); \ } \ pass3 { mVUlog(OPname); mVUlogFd(); mVUlogI(); } \ } // FMAC13 - MSUB FMAC Opcode Storing Result to Fd (I Reg) #define mVU_FMAC13(operation, OPname) { \ - microVU* mVU = mVUx; \ - pass1 { mVUanalyzeFMAC1(_Fd_, _Fs_, 0); } \ + pass1 { mVUanalyzeFMAC1(mVU, _Fd_, _Fs_, 0); } \ pass2 { \ int Fd, ACC, Fs, Ft; \ - mVUallocFMAC13a(Fd, ACC, Fs, Ft); \ + mVUallocFMAC13a(mVU, Fd, ACC, Fs, Ft); \ if (_X_Y_Z_W == 8) { \ SSE_MULSS_XMM_to_XMM(Fs, Ft); \ SSE_##operation##SS_XMM_to_XMM(ACC, Fs); \ @@ -279,18 +266,17 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX SSE_MULPS_XMM_to_XMM(Fs, Ft); \ SSE_##operation##PS_XMM_to_XMM(ACC, Fs); \ } \ - mVUupdateFlags(Fd, Fs, xmmT2, _X_Y_Z_W, 0); \ - mVUallocFMAC13b(Fd); \ + mVUupdateFlags(mVU, Fd, Fs, xmmT2, _X_Y_Z_W, 0); \ + mVUallocFMAC13b(mVU, Fd); \ } \ pass3 { mVUlog(OPname); mVUlogFd(); mVUlogI(); } \ } // FMAC14 - MADDA/MSUBA FMAC Opcode #define mVU_FMAC14(operation, OPname) { \ - microVU* mVU = mVUx; \ - pass1 { mVUanalyzeFMAC1(0, _Fs_, _Ft_); } \ + pass1 { mVUanalyzeFMAC1(mVU, 0, _Fs_, _Ft_); } \ pass2 { \ int ACCw, ACCr, Fs, Ft; \ - mVUallocFMAC14a(ACCw, ACCr, Fs, Ft); \ + mVUallocFMAC14a(mVU, ACCw, ACCr, Fs, Ft); \ if (_X_Y_Z_W == 8) { \ SSE_MULSS_XMM_to_XMM(Fs, Ft); \ SSE_##operation##SS_XMM_to_XMM(ACCr, Fs); \ @@ -299,18 +285,17 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX SSE_MULPS_XMM_to_XMM(Fs, Ft); \ SSE_##operation##PS_XMM_to_XMM(ACCr, Fs); \ } \ - mVUupdateFlags(ACCr, Fs, xmmT2, _X_Y_Z_W, 0); \ - mVUallocFMAC14b(ACCw, ACCr); \ + mVUupdateFlags(mVU, ACCr, Fs, xmmT2, _X_Y_Z_W, 0); \ + mVUallocFMAC14b(mVU, ACCw, ACCr); \ } \ pass3 { mVUlog(OPname); mVUlogACC(); mVUlogFt(); } \ } // FMAC15 - MADDA/MSUBA BC(xyzw) FMAC Opcode #define mVU_FMAC15(operation, OPname) { \ - microVU* mVU = mVUx; \ - pass1 { mVUanalyzeFMAC3(0, _Fs_, _Ft_); } \ + pass1 { mVUanalyzeFMAC3(mVU, 0, _Fs_, _Ft_); } \ pass2 { \ int ACCw, ACCr, Fs, Ft; \ - mVUallocFMAC15a(ACCw, ACCr, Fs, Ft); \ + mVUallocFMAC15a(mVU, ACCw, ACCr, Fs, Ft); \ if (_X_Y_Z_W == 8) { \ SSE_MULSS_XMM_to_XMM(Fs, Ft); \ SSE_##operation##SS_XMM_to_XMM(ACCr, Fs); \ @@ -319,18 +304,17 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX SSE_MULPS_XMM_to_XMM(Fs, Ft); \ SSE_##operation##PS_XMM_to_XMM(ACCr, Fs); \ } \ - mVUupdateFlags(ACCr, Fs, xmmT2, _X_Y_Z_W, 0); \ - mVUallocFMAC15b(ACCw, ACCr); \ + mVUupdateFlags(mVU, ACCr, Fs, xmmT2, _X_Y_Z_W, 0); \ + mVUallocFMAC15b(mVU, ACCw, ACCr); \ } \ pass3 { mVUlog(OPname); mVUlogACC(); mVUlogBC(); } \ } // FMAC16 - MADDA/MSUBA FMAC Opcode (I Reg) #define mVU_FMAC16(operation, OPname) { \ - microVU* mVU = mVUx; \ - pass1 { mVUanalyzeFMAC1(0, _Fs_, 0); } \ + pass1 { mVUanalyzeFMAC1(mVU, 0, _Fs_, 0); } \ pass2 { \ int ACCw, ACCr, Fs, Ft; \ - mVUallocFMAC16a(ACCw, ACCr, Fs, Ft); \ + mVUallocFMAC16a(mVU, ACCw, ACCr, Fs, Ft); \ if (_X_Y_Z_W == 8) { \ SSE_MULSS_XMM_to_XMM(Fs, Ft); \ SSE_##operation##SS_XMM_to_XMM(ACCr, Fs); \ @@ -339,73 +323,68 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX SSE_MULPS_XMM_to_XMM(Fs, Ft); \ SSE_##operation##PS_XMM_to_XMM(ACCr, Fs); \ } \ - mVUupdateFlags(ACCr, Fs, xmmT2, _X_Y_Z_W, 0); \ - mVUallocFMAC16b(ACCw, ACCr); \ + mVUupdateFlags(mVU, ACCr, Fs, xmmT2, _X_Y_Z_W, 0); \ + mVUallocFMAC16b(mVU, ACCw, ACCr); \ } \ pass3 { mVUlog(OPname); mVUlogACC(); mVUlogI(); } \ } // FMAC18 - OPMULA FMAC Opcode #define mVU_FMAC18(operation, OPname) { \ - microVU* mVU = mVUx; \ - pass1 { mVUanalyzeFMAC1(0, _Fs_, _Ft_); } \ + pass1 { mVUanalyzeFMAC1(mVU, 0, _Fs_, _Ft_); } \ pass2 { \ int ACC, Fs, Ft; \ - mVUallocFMAC18a(ACC, Fs, Ft); \ + mVUallocFMAC18a(mVU, ACC, Fs, Ft); \ SSE_##operation##PS_XMM_to_XMM(Fs, Ft); \ - mVUupdateFlags(Fs, xmmT1, xmmT2, _X_Y_Z_W, 0); \ - mVUallocFMAC18b(ACC, Fs); \ + mVUupdateFlags(mVU, Fs, xmmT1, xmmT2, _X_Y_Z_W, 0); \ + mVUallocFMAC18b(mVU, ACC, Fs); \ } \ pass3 { mVUlog(OPname); mVUlogACC(); mVUlogFt(); } \ } // FMAC19 - OPMSUB FMAC Opcode #define mVU_FMAC19(operation, OPname) { \ - microVU* mVU = mVUx; \ - pass1 { mVUanalyzeFMAC1(_Fd_, _Fs_, _Ft_); } \ + pass1 { mVUanalyzeFMAC1(mVU, _Fd_, _Fs_, _Ft_); } \ pass2 { \ int Fd, ACC, Fs, Ft; \ - mVUallocFMAC19a(Fd, ACC, Fs, Ft); \ + mVUallocFMAC19a(mVU, Fd, ACC, Fs, Ft); \ SSE_MULPS_XMM_to_XMM(Fs, Ft); \ SSE_##operation##PS_XMM_to_XMM(ACC, Fs); \ - mVUupdateFlags(Fd, Fs, xmmT2, _X_Y_Z_W, 0); \ - mVUallocFMAC19b(Fd); \ + mVUupdateFlags(mVU, Fd, Fs, xmmT2, _X_Y_Z_W, 0); \ + mVUallocFMAC19b(mVU, Fd); \ } \ pass3 { mVUlog(OPname); mVUlogFd(); mVUlogFt(); } \ } // FMAC22 - Normal FMAC Opcodes (Q Reg) #define mVU_FMAC22(operation, OPname) { \ - microVU* mVU = mVUx; \ - pass1 { mVUanalyzeFMAC1(_Fd_, _Fs_, 0); } \ + pass1 { mVUanalyzeFMAC1(mVU, _Fd_, _Fs_, 0); } \ pass2 { \ int Fd, Fs, Ft; \ - mVUallocFMAC22a(Fd, Fs, Ft); \ + mVUallocFMAC22a(mVU, Fd, Fs, Ft); \ if (_XYZW_SS) SSE_##operation##SS_XMM_to_XMM(Fs, Ft); \ else SSE_##operation##PS_XMM_to_XMM(Fs, Ft); \ - mVUupdateFlags(Fd, xmmT1, xmmT2, _X_Y_Z_W, 1); \ - mVUallocFMAC22b(Fd); \ + mVUupdateFlags(mVU, Fd, xmmT1, xmmT2, _X_Y_Z_W, 1); \ + mVUallocFMAC22b(mVU, Fd); \ } \ pass3 { mVUlog(OPname); mVUlogFd(); mVUlogQ(); } \ } // FMAC23 - FMAC Opcodes Storing Result to ACC (Q Reg) #define mVU_FMAC23(operation, OPname) { \ - microVU* mVU = mVUx; \ - pass1 { mVUanalyzeFMAC1(0, _Fs_, 0); } \ + pass1 { mVUanalyzeFMAC1(mVU, 0, _Fs_, 0); } \ pass2 { \ int ACC, Fs, Ft; \ - mVUallocFMAC23a(ACC, Fs, Ft); \ + mVUallocFMAC23a(mVU, ACC, Fs, Ft); \ if (_X_Y_Z_W == 8) SSE_##operation##SS_XMM_to_XMM(Fs, Ft); \ else SSE_##operation##PS_XMM_to_XMM(Fs, Ft); \ - mVUupdateFlags(Fs, xmmT1, xmmT2, _X_Y_Z_W, 0); \ - mVUallocFMAC23b(ACC, Fs); \ + mVUupdateFlags(mVU, Fs, xmmT1, xmmT2, _X_Y_Z_W, 0); \ + mVUallocFMAC23b(mVU, ACC, Fs); \ } \ pass3 { mVUlog(OPname); mVUlogACC(); mVUlogQ();} \ } // FMAC24 - MADD FMAC Opcode Storing Result to Fd (Q Reg) #define mVU_FMAC24(operation, OPname) { \ - microVU* mVU = mVUx; \ - pass1 { mVUanalyzeFMAC1(_Fd_, _Fs_, 0); } \ + pass1 { mVUanalyzeFMAC1(mVU, _Fd_, _Fs_, 0); } \ pass2 { \ int Fd, ACC, Fs, Ft; \ - mVUallocFMAC24a(Fd, ACC, Fs, Ft); \ + mVUallocFMAC24a(mVU, Fd, ACC, Fs, Ft); \ if (_X_Y_Z_W == 8) { \ SSE_MULSS_XMM_to_XMM(Fs, Ft); \ SSE_##operation##SS_XMM_to_XMM(Fs, ACC); \ @@ -414,18 +393,17 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX SSE_MULPS_XMM_to_XMM(Fs, Ft); \ SSE_##operation##PS_XMM_to_XMM(Fs, ACC); \ } \ - mVUupdateFlags(Fd, xmmT1, xmmT2, _X_Y_Z_W, 0); \ - mVUallocFMAC24b(Fd); \ + mVUupdateFlags(mVU, Fd, xmmT1, xmmT2, _X_Y_Z_W, 0); \ + mVUallocFMAC24b(mVU, Fd); \ } \ pass3 { mVUlog(OPname); mVUlogFd(); mVUlogQ(); } \ } // FMAC25 - MSUB FMAC Opcode Storing Result to Fd (Q Reg) #define mVU_FMAC25(operation, OPname) { \ - microVU* mVU = mVUx; \ - pass1 { mVUanalyzeFMAC1(_Fd_, _Fs_, 0); } \ + pass1 { mVUanalyzeFMAC1(mVU, _Fd_, _Fs_, 0); } \ pass2 { \ int Fd, ACC, Fs, Ft; \ - mVUallocFMAC25a(Fd, ACC, Fs, Ft); \ + mVUallocFMAC25a(mVU, Fd, ACC, Fs, Ft); \ if (_X_Y_Z_W == 8) { \ SSE_MULSS_XMM_to_XMM(Fs, Ft); \ SSE_##operation##SS_XMM_to_XMM(ACC, Fs); \ @@ -434,18 +412,17 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX SSE_MULPS_XMM_to_XMM(Fs, Ft); \ SSE_##operation##PS_XMM_to_XMM(ACC, Fs); \ } \ - mVUupdateFlags(Fd, Fs, xmmT2, _X_Y_Z_W, 0); \ - mVUallocFMAC25b(Fd); \ + mVUupdateFlags(mVU, Fd, Fs, xmmT2, _X_Y_Z_W, 0); \ + mVUallocFMAC25b(mVU, Fd); \ } \ pass3 { mVUlog(OPname); mVUlogFd(); mVUlogQ(); } \ } // FMAC26 - MADDA/MSUBA FMAC Opcode (Q Reg) #define mVU_FMAC26(operation, OPname) { \ - microVU* mVU = mVUx; \ - pass1 { mVUanalyzeFMAC1(0, _Fs_, 0); } \ + pass1 { mVUanalyzeFMAC1(mVU, 0, _Fs_, 0); } \ pass2 { \ int ACCw, ACCr, Fs, Ft; \ - mVUallocFMAC26a(ACCw, ACCr, Fs, Ft); \ + mVUallocFMAC26a(mVU, ACCw, ACCr, Fs, Ft); \ if (_X_Y_Z_W == 8) { \ SSE_MULSS_XMM_to_XMM(Fs, Ft); \ SSE_##operation##SS_XMM_to_XMM(ACCr, Fs); \ @@ -454,123 +431,121 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX SSE_MULPS_XMM_to_XMM(Fs, Ft); \ SSE_##operation##PS_XMM_to_XMM(ACCr, Fs); \ } \ - mVUupdateFlags(ACCr, Fs, xmmT2, _X_Y_Z_W, 0); \ - mVUallocFMAC26b(ACCw, ACCr); \ + mVUupdateFlags(mVU, ACCr, Fs, xmmT2, _X_Y_Z_W, 0); \ + mVUallocFMAC26b(mVU, ACCw, ACCr); \ } \ pass3 { mVUlog(OPname); mVUlogACC(); mVUlogQ(); } \ } // FMAC27~29 - MAX/MINI FMAC Opcodes -#define mVU_FMAC27(operation, OPname) { mVU_FMAC1 (operation, OPname); pass1 { microVU* mVU = mVUx; mVUinfo &= ~_doStatus; } } -#define mVU_FMAC28(operation, OPname) { mVU_FMAC6 (operation, OPname); pass1 { microVU* mVU = mVUx; mVUinfo &= ~_doStatus; } } -#define mVU_FMAC29(operation, OPname) { mVU_FMAC3 (operation, OPname); pass1 { microVU* mVU = mVUx; mVUinfo &= ~_doStatus; } } +#define mVU_FMAC27(operation, OPname) { mVU_FMAC1 (operation, OPname); pass1 { mVUinfo &= ~_doStatus; } } +#define mVU_FMAC28(operation, OPname) { mVU_FMAC6 (operation, OPname); pass1 { mVUinfo &= ~_doStatus; } } +#define mVU_FMAC29(operation, OPname) { mVU_FMAC3 (operation, OPname); pass1 { mVUinfo &= ~_doStatus; } } //------------------------------------------------------------------ // Micro VU Micromode Upper instructions //------------------------------------------------------------------ -microVUf(void) mVU_ABS(mF) { - microVU* mVU = mVUx; - pass1 { mVUanalyzeFMAC2(_Fs_, _Ft_); } +mVUop(mVU_ABS) { + pass1 { mVUanalyzeFMAC2(mVU, _Fs_, _Ft_); } pass2 { int Fs, Ft; - mVUallocFMAC2a(Fs, Ft); + mVUallocFMAC2a(mVU, Fs, Ft); SSE_ANDPS_M128_to_XMM(Fs, (uptr)mVU_absclip); - mVUallocFMAC2b(Ft); + mVUallocFMAC2b(mVU, Ft); } pass3 { mVUlog("ABS"); mVUlogFtFs(); } } -microVUf(void) mVU_ADD(mF) { mVU_FMAC1 (ADD, "ADD"); } -microVUf(void) mVU_ADDi(mF) { mVU_FMAC6 (ADD2, "ADDi"); } -microVUf(void) mVU_ADDq(mF) { mVU_FMAC22(ADD, "ADDq"); } -microVUf(void) mVU_ADDx(mF) { mVU_FMAC3 (ADD, "ADDx"); } -microVUf(void) mVU_ADDy(mF) { mVU_FMAC3 (ADD, "ADDy"); } -microVUf(void) mVU_ADDz(mF) { mVU_FMAC3 (ADD, "ADDz"); } -microVUf(void) mVU_ADDw(mF) { mVU_FMAC3 (ADD, "ADDw"); } -microVUf(void) mVU_ADDA(mF) { mVU_FMAC4 (ADD, "ADDA"); } -microVUf(void) mVU_ADDAi(mF) { mVU_FMAC7 (ADD, "ADDAi"); } -microVUf(void) mVU_ADDAq(mF) { mVU_FMAC23(ADD, "ADDAq"); } -microVUf(void) mVU_ADDAx(mF) { mVU_FMAC5 (ADD, "ADDAx"); } -microVUf(void) mVU_ADDAy(mF) { mVU_FMAC5 (ADD, "ADDAy"); } -microVUf(void) mVU_ADDAz(mF) { mVU_FMAC5 (ADD, "ADDAz"); } -microVUf(void) mVU_ADDAw(mF) { mVU_FMAC5 (ADD, "ADDAw"); } -microVUf(void) mVU_SUB(mF) { mVU_FMAC1 (SUB, "SUB"); } -microVUf(void) mVU_SUBi(mF) { mVU_FMAC6 (SUB, "SUBi"); } -microVUf(void) mVU_SUBq(mF) { mVU_FMAC22(SUB, "SUBq"); } -microVUf(void) mVU_SUBx(mF) { mVU_FMAC3 (SUB, "SUBx"); } -microVUf(void) mVU_SUBy(mF) { mVU_FMAC3 (SUB, "SUBy"); } -microVUf(void) mVU_SUBz(mF) { mVU_FMAC3 (SUB, "SUBz"); } -microVUf(void) mVU_SUBw(mF) { mVU_FMAC3 (SUB, "SUBw"); } -microVUf(void) mVU_SUBA(mF) { mVU_FMAC4 (SUB, "SUBA"); } -microVUf(void) mVU_SUBAi(mF) { mVU_FMAC7 (SUB, "SUBAi"); } -microVUf(void) mVU_SUBAq(mF) { mVU_FMAC23(SUB, "SUBAq"); } -microVUf(void) mVU_SUBAx(mF) { mVU_FMAC5 (SUB, "SUBAx"); } -microVUf(void) mVU_SUBAy(mF) { mVU_FMAC5 (SUB, "SUBAy"); } -microVUf(void) mVU_SUBAz(mF) { mVU_FMAC5 (SUB, "SUBAz"); } -microVUf(void) mVU_SUBAw(mF) { mVU_FMAC5 (SUB, "SUBAw"); } -microVUf(void) mVU_MUL(mF) { mVU_FMAC1 (MUL, "MUL"); } -microVUf(void) mVU_MULi(mF) { mVU_FMAC6 (MUL, "MULi"); } -microVUf(void) mVU_MULq(mF) { mVU_FMAC22(MUL, "MULq"); } -microVUf(void) mVU_MULx(mF) { mVU_FMAC3 (MUL, "MULx"); } -microVUf(void) mVU_MULy(mF) { mVU_FMAC3 (MUL, "MULy"); } -microVUf(void) mVU_MULz(mF) { mVU_FMAC3 (MUL, "MULz"); } -microVUf(void) mVU_MULw(mF) { mVU_FMAC3 (MUL, "MULw"); } -microVUf(void) mVU_MULA(mF) { mVU_FMAC4 (MUL, "MULA"); } -microVUf(void) mVU_MULAi(mF) { mVU_FMAC7 (MUL, "MULAi"); } -microVUf(void) mVU_MULAq(mF) { mVU_FMAC23(MUL, "MULAq"); } -microVUf(void) mVU_MULAx(mF) { mVU_FMAC5 (MUL, "MULAx"); } -microVUf(void) mVU_MULAy(mF) { mVU_FMAC5 (MUL, "MULAy"); } -microVUf(void) mVU_MULAz(mF) { mVU_FMAC5 (MUL, "MULAz"); } -microVUf(void) mVU_MULAw(mF) { mVU_FMAC5 (MUL, "MULAw"); } -microVUf(void) mVU_MADD(mF) { mVU_FMAC8 (ADD, "MADD"); } -microVUf(void) mVU_MADDi(mF) { mVU_FMAC12(ADD, "MADDi"); } -microVUf(void) mVU_MADDq(mF) { mVU_FMAC24(ADD, "MADDq"); } -microVUf(void) mVU_MADDx(mF) { mVU_FMAC10(ADD, "MADDx"); } -microVUf(void) mVU_MADDy(mF) { mVU_FMAC10(ADD, "MADDy"); } -microVUf(void) mVU_MADDz(mF) { mVU_FMAC10(ADD, "MADDz"); } -microVUf(void) mVU_MADDw(mF) { mVU_FMAC10(ADD, "MADDw"); } -microVUf(void) mVU_MADDA(mF) { mVU_FMAC14(ADD, "MADDA"); } -microVUf(void) mVU_MADDAi(mF) { mVU_FMAC16(ADD, "MADDAi"); } -microVUf(void) mVU_MADDAq(mF) { mVU_FMAC26(ADD, "MADDAq"); } -microVUf(void) mVU_MADDAx(mF) { mVU_FMAC15(ADD, "MADDAx"); } -microVUf(void) mVU_MADDAy(mF) { mVU_FMAC15(ADD, "MADDAy"); } -microVUf(void) mVU_MADDAz(mF) { mVU_FMAC15(ADD, "MADDAz"); } -microVUf(void) mVU_MADDAw(mF) { mVU_FMAC15(ADD, "MADDAw"); } -microVUf(void) mVU_MSUB(mF) { mVU_FMAC9 (SUB, "MSUB"); } -microVUf(void) mVU_MSUBi(mF) { mVU_FMAC13(SUB, "MSUBi"); } -microVUf(void) mVU_MSUBq(mF) { mVU_FMAC25(SUB, "MSUBq"); } -microVUf(void) mVU_MSUBx(mF) { mVU_FMAC11(SUB, "MSUBx"); } -microVUf(void) mVU_MSUBy(mF) { mVU_FMAC11(SUB, "MSUBy"); } -microVUf(void) mVU_MSUBz(mF) { mVU_FMAC11(SUB, "MSUBz"); } -microVUf(void) mVU_MSUBw(mF) { mVU_FMAC11(SUB, "MSUBw"); } -microVUf(void) mVU_MSUBA(mF) { mVU_FMAC14(SUB, "MSUBA"); } -microVUf(void) mVU_MSUBAi(mF) { mVU_FMAC16(SUB, "MSUBAi"); } -microVUf(void) mVU_MSUBAq(mF) { mVU_FMAC26(SUB, "MSUBAq"); } -microVUf(void) mVU_MSUBAx(mF) { mVU_FMAC15(SUB, "MSUBAx"); } -microVUf(void) mVU_MSUBAy(mF) { mVU_FMAC15(SUB, "MSUBAy"); } -microVUf(void) mVU_MSUBAz(mF) { mVU_FMAC15(SUB, "MSUBAz"); } -microVUf(void) mVU_MSUBAw(mF) { mVU_FMAC15(SUB, "MSUBAw"); } -microVUf(void) mVU_MAX(mF) { mVU_FMAC27(MAX2, "MAX"); } -microVUf(void) mVU_MAXi(mF) { mVU_FMAC28(MAX2, "MAXi"); } -microVUf(void) mVU_MAXx(mF) { mVU_FMAC29(MAX2, "MAXx"); } -microVUf(void) mVU_MAXy(mF) { mVU_FMAC29(MAX2, "MAXy"); } -microVUf(void) mVU_MAXz(mF) { mVU_FMAC29(MAX2, "MAXz"); } -microVUf(void) mVU_MAXw(mF) { mVU_FMAC29(MAX2, "MAXw"); } -microVUf(void) mVU_MINI(mF) { mVU_FMAC27(MIN2, "MINI"); } -microVUf(void) mVU_MINIi(mF) { mVU_FMAC28(MIN2, "MINIi"); } -microVUf(void) mVU_MINIx(mF) { mVU_FMAC29(MIN2, "MINIx"); } -microVUf(void) mVU_MINIy(mF) { mVU_FMAC29(MIN2, "MINIy"); } -microVUf(void) mVU_MINIz(mF) { mVU_FMAC29(MIN2, "MINIz"); } -microVUf(void) mVU_MINIw(mF) { mVU_FMAC29(MIN2, "MINIw"); } -microVUf(void) mVU_OPMULA(mF) { mVU_FMAC18(MUL, "OPMULA"); } -microVUf(void) mVU_OPMSUB(mF) { mVU_FMAC19(SUB, "OPMSUB"); } -microVUf(void) mVU_NOP(mF) { pass3 { mVUlog("NOP"); } } -microVUq(void) mVU_FTOIx(uptr addr, int recPass) { - microVU* mVU = mVUx; - pass1 { mVUanalyzeFMAC2(_Fs_, _Ft_); } +mVUop(mVU_ADD) { mVU_FMAC1 (ADD, "ADD"); } +mVUop(mVU_ADDi) { mVU_FMAC6 (ADD2, "ADDi"); } +mVUop(mVU_ADDq) { mVU_FMAC22(ADD, "ADDq"); } +mVUop(mVU_ADDx) { mVU_FMAC3 (ADD, "ADDx"); } +mVUop(mVU_ADDy) { mVU_FMAC3 (ADD, "ADDy"); } +mVUop(mVU_ADDz) { mVU_FMAC3 (ADD, "ADDz"); } +mVUop(mVU_ADDw) { mVU_FMAC3 (ADD, "ADDw"); } +mVUop(mVU_ADDA) { mVU_FMAC4 (ADD, "ADDA"); } +mVUop(mVU_ADDAi) { mVU_FMAC7 (ADD, "ADDAi"); } +mVUop(mVU_ADDAq) { mVU_FMAC23(ADD, "ADDAq"); } +mVUop(mVU_ADDAx) { mVU_FMAC5 (ADD, "ADDAx"); } +mVUop(mVU_ADDAy) { mVU_FMAC5 (ADD, "ADDAy"); } +mVUop(mVU_ADDAz) { mVU_FMAC5 (ADD, "ADDAz"); } +mVUop(mVU_ADDAw) { mVU_FMAC5 (ADD, "ADDAw"); } +mVUop(mVU_SUB) { mVU_FMAC1 (SUB, "SUB"); } +mVUop(mVU_SUBi) { mVU_FMAC6 (SUB, "SUBi"); } +mVUop(mVU_SUBq) { mVU_FMAC22(SUB, "SUBq"); } +mVUop(mVU_SUBx) { mVU_FMAC3 (SUB, "SUBx"); } +mVUop(mVU_SUBy) { mVU_FMAC3 (SUB, "SUBy"); } +mVUop(mVU_SUBz) { mVU_FMAC3 (SUB, "SUBz"); } +mVUop(mVU_SUBw) { mVU_FMAC3 (SUB, "SUBw"); } +mVUop(mVU_SUBA) { mVU_FMAC4 (SUB, "SUBA"); } +mVUop(mVU_SUBAi) { mVU_FMAC7 (SUB, "SUBAi"); } +mVUop(mVU_SUBAq) { mVU_FMAC23(SUB, "SUBAq"); } +mVUop(mVU_SUBAx) { mVU_FMAC5 (SUB, "SUBAx"); } +mVUop(mVU_SUBAy) { mVU_FMAC5 (SUB, "SUBAy"); } +mVUop(mVU_SUBAz) { mVU_FMAC5 (SUB, "SUBAz"); } +mVUop(mVU_SUBAw) { mVU_FMAC5 (SUB, "SUBAw"); } +mVUop(mVU_MUL) { mVU_FMAC1 (MUL, "MUL"); } +mVUop(mVU_MULi) { mVU_FMAC6 (MUL, "MULi"); } +mVUop(mVU_MULq) { mVU_FMAC22(MUL, "MULq"); } +mVUop(mVU_MULx) { mVU_FMAC3 (MUL, "MULx"); } +mVUop(mVU_MULy) { mVU_FMAC3 (MUL, "MULy"); } +mVUop(mVU_MULz) { mVU_FMAC3 (MUL, "MULz"); } +mVUop(mVU_MULw) { mVU_FMAC3 (MUL, "MULw"); } +mVUop(mVU_MULA) { mVU_FMAC4 (MUL, "MULA"); } +mVUop(mVU_MULAi) { mVU_FMAC7 (MUL, "MULAi"); } +mVUop(mVU_MULAq) { mVU_FMAC23(MUL, "MULAq"); } +mVUop(mVU_MULAx) { mVU_FMAC5 (MUL, "MULAx"); } +mVUop(mVU_MULAy) { mVU_FMAC5 (MUL, "MULAy"); } +mVUop(mVU_MULAz) { mVU_FMAC5 (MUL, "MULAz"); } +mVUop(mVU_MULAw) { mVU_FMAC5 (MUL, "MULAw"); } +mVUop(mVU_MADD) { mVU_FMAC8 (ADD, "MADD"); } +mVUop(mVU_MADDi) { mVU_FMAC12(ADD, "MADDi"); } +mVUop(mVU_MADDq) { mVU_FMAC24(ADD, "MADDq"); } +mVUop(mVU_MADDx) { mVU_FMAC10(ADD, "MADDx"); } +mVUop(mVU_MADDy) { mVU_FMAC10(ADD, "MADDy"); } +mVUop(mVU_MADDz) { mVU_FMAC10(ADD, "MADDz"); } +mVUop(mVU_MADDw) { mVU_FMAC10(ADD, "MADDw"); } +mVUop(mVU_MADDA) { mVU_FMAC14(ADD, "MADDA"); } +mVUop(mVU_MADDAi) { mVU_FMAC16(ADD, "MADDAi"); } +mVUop(mVU_MADDAq) { mVU_FMAC26(ADD, "MADDAq"); } +mVUop(mVU_MADDAx) { mVU_FMAC15(ADD, "MADDAx"); } +mVUop(mVU_MADDAy) { mVU_FMAC15(ADD, "MADDAy"); } +mVUop(mVU_MADDAz) { mVU_FMAC15(ADD, "MADDAz"); } +mVUop(mVU_MADDAw) { mVU_FMAC15(ADD, "MADDAw"); } +mVUop(mVU_MSUB) { mVU_FMAC9 (SUB, "MSUB"); } +mVUop(mVU_MSUBi) { mVU_FMAC13(SUB, "MSUBi"); } +mVUop(mVU_MSUBq) { mVU_FMAC25(SUB, "MSUBq"); } +mVUop(mVU_MSUBx) { mVU_FMAC11(SUB, "MSUBx"); } +mVUop(mVU_MSUBy) { mVU_FMAC11(SUB, "MSUBy"); } +mVUop(mVU_MSUBz) { mVU_FMAC11(SUB, "MSUBz"); } +mVUop(mVU_MSUBw) { mVU_FMAC11(SUB, "MSUBw"); } +mVUop(mVU_MSUBA) { mVU_FMAC14(SUB, "MSUBA"); } +mVUop(mVU_MSUBAi) { mVU_FMAC16(SUB, "MSUBAi"); } +mVUop(mVU_MSUBAq) { mVU_FMAC26(SUB, "MSUBAq"); } +mVUop(mVU_MSUBAx) { mVU_FMAC15(SUB, "MSUBAx"); } +mVUop(mVU_MSUBAy) { mVU_FMAC15(SUB, "MSUBAy"); } +mVUop(mVU_MSUBAz) { mVU_FMAC15(SUB, "MSUBAz"); } +mVUop(mVU_MSUBAw) { mVU_FMAC15(SUB, "MSUBAw"); } +mVUop(mVU_MAX) { mVU_FMAC27(MAX2, "MAX"); } +mVUop(mVU_MAXi) { mVU_FMAC28(MAX2, "MAXi"); } +mVUop(mVU_MAXx) { mVU_FMAC29(MAX2, "MAXx"); } +mVUop(mVU_MAXy) { mVU_FMAC29(MAX2, "MAXy"); } +mVUop(mVU_MAXz) { mVU_FMAC29(MAX2, "MAXz"); } +mVUop(mVU_MAXw) { mVU_FMAC29(MAX2, "MAXw"); } +mVUop(mVU_MINI) { mVU_FMAC27(MIN2, "MINI"); } +mVUop(mVU_MINIi) { mVU_FMAC28(MIN2, "MINIi"); } +mVUop(mVU_MINIx) { mVU_FMAC29(MIN2, "MINIx"); } +mVUop(mVU_MINIy) { mVU_FMAC29(MIN2, "MINIy"); } +mVUop(mVU_MINIz) { mVU_FMAC29(MIN2, "MINIz"); } +mVUop(mVU_MINIw) { mVU_FMAC29(MIN2, "MINIw"); } +mVUop(mVU_OPMULA) { mVU_FMAC18(MUL, "OPMULA"); } +mVUop(mVU_OPMSUB) { mVU_FMAC19(SUB, "OPMSUB"); } +mVUop(mVU_NOP) { pass3 { mVUlog("NOP"); } } +void mVU_FTOIx(mP, uptr addr) { + pass1 { mVUanalyzeFMAC2(mVU, _Fs_, _Ft_); } pass2 { int Fs, Ft; - mVUallocFMAC2a(Fs, Ft); + mVUallocFMAC2a(mVU, Fs, Ft); // Note: For help understanding this algorithm see recVUMI_FTOI_Saturate() SSE_MOVAPS_XMM_to_XMM(xmmT1, Fs); @@ -583,38 +558,36 @@ microVUq(void) mVU_FTOIx(uptr addr, int recPass) { SSE_ANDPS_XMM_to_XMM(xmmT1, xmmFt); SSE2_PADDD_XMM_to_XMM(Fs, xmmT1); - mVUallocFMAC2b(Ft); + mVUallocFMAC2b(mVU, Ft); } } -microVUf(void) mVU_FTOI0(mF) { mVU_FTOIx((uptr)0, recPass); pass3 { microVU* mVU = mVUx; mVUlog("FTOI0"); mVUlogFtFs(); } } -microVUf(void) mVU_FTOI4(mF) { mVU_FTOIx((uptr)mVU_FTOI_4, recPass); pass3 { microVU* mVU = mVUx; mVUlog("FTOI4"); mVUlogFtFs(); } } -microVUf(void) mVU_FTOI12(mF) { mVU_FTOIx((uptr)mVU_FTOI_12, recPass); pass3 { microVU* mVU = mVUx; mVUlog("FTOI12"); mVUlogFtFs(); } } -microVUf(void) mVU_FTOI15(mF) { mVU_FTOIx((uptr)mVU_FTOI_15, recPass); pass3 { microVU* mVU = mVUx; mVUlog("FTOI15"); mVUlogFtFs(); } } -microVUq(void) mVU_ITOFx(uptr addr, int recPass) { - microVU* mVU = mVUx; - pass1 { mVUanalyzeFMAC2(_Fs_, _Ft_); } +mVUop(mVU_FTOI0) { mVU_FTOIx(mX, (uptr)0); pass3 { mVUlog("FTOI0"); mVUlogFtFs(); } } +mVUop(mVU_FTOI4) { mVU_FTOIx(mX, (uptr)mVU_FTOI_4); pass3 { mVUlog("FTOI4"); mVUlogFtFs(); } } +mVUop(mVU_FTOI12) { mVU_FTOIx(mX, (uptr)mVU_FTOI_12); pass3 { mVUlog("FTOI12"); mVUlogFtFs(); } } +mVUop(mVU_FTOI15) { mVU_FTOIx(mX, (uptr)mVU_FTOI_15); pass3 { mVUlog("FTOI15"); mVUlogFtFs(); } } +void mVU_ITOFx(mP, uptr addr) { + pass1 { mVUanalyzeFMAC2(mVU, _Fs_, _Ft_); } pass2 { int Fs, Ft; - mVUallocFMAC2a(Fs, Ft); + mVUallocFMAC2a(mVU, Fs, Ft); SSE2_CVTDQ2PS_XMM_to_XMM(Ft, Fs); if (addr) { SSE_MULPS_M128_to_XMM(Ft, addr); } //mVUclamp2(Ft, xmmT1, 15); // Clamp (not sure if this is needed) - mVUallocFMAC2b(Ft); + mVUallocFMAC2b(mVU, Ft); } } -microVUf(void) mVU_ITOF0(mF) { mVU_ITOFx((uptr)0, recPass); pass3 { microVU* mVU = mVUx; mVUlog("ITOF0"); mVUlogFtFs(); } } -microVUf(void) mVU_ITOF4(mF) { mVU_ITOFx((uptr)mVU_ITOF_4, recPass); pass3 { microVU* mVU = mVUx; mVUlog("ITOF4"); mVUlogFtFs(); } } -microVUf(void) mVU_ITOF12(mF) { mVU_ITOFx((uptr)mVU_ITOF_12, recPass); pass3 { microVU* mVU = mVUx; mVUlog("ITOF12"); mVUlogFtFs(); } } -microVUf(void) mVU_ITOF15(mF) { mVU_ITOFx((uptr)mVU_ITOF_15, recPass); pass3 { microVU* mVU = mVUx; mVUlog("ITOF15"); mVUlogFtFs(); } } -microVUf(void) mVU_CLIP(mF) { - microVU* mVU = mVUx; - pass1 { mVUanalyzeFMAC4(_Fs_, _Ft_); } +mVUop(mVU_ITOF0) { mVU_ITOFx(mX, (uptr)0); pass3 { mVUlog("ITOF0"); mVUlogFtFs(); } } +mVUop(mVU_ITOF4) { mVU_ITOFx(mX, (uptr)mVU_ITOF_4); pass3 { mVUlog("ITOF4"); mVUlogFtFs(); } } +mVUop(mVU_ITOF12) { mVU_ITOFx(mX, (uptr)mVU_ITOF_12); pass3 { mVUlog("ITOF12"); mVUlogFtFs(); } } +mVUop(mVU_ITOF15) { mVU_ITOFx(mX, (uptr)mVU_ITOF_15); pass3 { mVUlog("ITOF15"); mVUlogFtFs(); } } +mVUop(mVU_CLIP) { + pass1 { mVUanalyzeFMAC4(mVU, _Fs_, _Ft_); } pass2 { int Fs, Ft; - mVUallocFMAC17a(Fs, Ft); - mVUallocCFLAGa(gprT1, fpcInstance); + mVUallocFMAC17a(mVU, Fs, Ft); + mVUallocCFLAGa(mVU, gprT1, fpcInstance); SHL32ItoR(gprT1, 6); SSE_ANDPS_M128_to_XMM(Ft, (uptr)mVU_absclip); @@ -638,7 +611,7 @@ microVUf(void) mVU_CLIP(mF) { OR32RtoR (gprT1, gprT2); AND32ItoR(gprT1, 0xffffff); - mVUallocCFLAGb(gprT1, fcInstance); + mVUallocCFLAGb(mVU, gprT1, fcInstance); } pass3 { mVUlog("CLIP"); mVUlogCLIP(); } }