From 51107ee9ddde66c9efddc816b5ed268a142d3cc6 Mon Sep 17 00:00:00 2001
From: refractionpcsx2 <refraction@gmail.com>
Date: Thu, 29 Dec 2022 17:05:05 +0000
Subject: [PATCH] mVU: Align x86ptr based on AVX2 caps

---
 pcsx2/PCSX2Base.h             | 8 --------
 pcsx2/x86/microVU_Compile.inl | 5 ++++-
 2 files changed, 4 insertions(+), 9 deletions(-)

diff --git a/pcsx2/PCSX2Base.h b/pcsx2/PCSX2Base.h
index 41d2036a1e..a7d6d4ae46 100644
--- a/pcsx2/PCSX2Base.h
+++ b/pcsx2/PCSX2Base.h
@@ -31,14 +31,6 @@
 	#error PCSX2 requires compiling for at least SSE 4.1
 #endif
 
-// Require 32 bit alignment for vectors for AVX2.
-#if _M_SSE >= 0x501
-	#define SSE_ALIGN_N 32
-#else
-	#define SSE_ALIGN_N 16
-#endif
-#define SSE_ALIGN alignas(SSE_ALIGN_N)
-
 // Starting with AVX, processors have fast unaligned loads
 // Reduce code duplication by not compiling multiple versions
 #if _M_SSE >= 0x500
diff --git a/pcsx2/x86/microVU_Compile.inl b/pcsx2/x86/microVU_Compile.inl
index 17f368d213..a18ea68bb6 100644
--- a/pcsx2/x86/microVU_Compile.inl
+++ b/pcsx2/x86/microVU_Compile.inl
@@ -482,7 +482,10 @@ void mVUtestCycles(microVU& mVU, microFlagCycles& mFC)
 	mVUendProgram(mVU, &mFC, 0);
 
 	{
-		xAlignPtr(SSE_ALIGN_N);
+		if(x86caps.hasAVX2)
+			xAlignPtr(32);
+		else
+			xAlignPtr(16);
 
 		u8* curx86Ptr = x86Ptr;
 		x86SetPtr(writeback);