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microVU: minor optimizations/changes... 

git-svn-id: http://pcsx2.googlecode.com/svn/trunk@1278 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
cottonvibes 2009-05-28 02:27:08 +00:00
parent a1cd98bc59
commit 50332c1cd1
5 changed files with 9 additions and 13 deletions
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1
pcsx2/x86/iVU0micro.cpp
View File

@ -47,7 +47,6 @@ namespace VU0micro
if ((VU0.VI[REG_VPU_STAT].UL & 1) == 0) return;
FreezeXMMRegs(1);
//Currently breaking mVU execution is disabled. Check mVUtestCycles<vuIndex>() in microVU_Compile.inl
if (useMVU0) runVUrec(VU0.VI[REG_TPC].UL, 50000, 0);
else SuperVUExecuteProgram(VU0.VI[REG_TPC].UL & 0xfff, 0);
FreezeXMMRegs(0);

1
pcsx2/x86/iVU1micro.cpp
View File

@ -275,7 +275,6 @@ namespace VU1micro
#endif
FreezeXMMRegs(1);
//Currently breaking mVU execution is disabled. Check mVUtestCycles<vuIndex>() in microVU_Compile.inl
if (useMVU1) runVUrec(VU1.VI[REG_TPC].UL, 3000000, 1);
else {
if (VU1.VI[REG_TPC].UL >= VU1.maxmicro) {

6
pcsx2/x86/microVU_Compile.inl
View File

@ -192,7 +192,7 @@ microVUt(void) mVUtestCycles() {
microVU* mVU = mVUx;
iPC = mVUstartPC;
mVUdebugNOW(0);
CMP32ItoM((uptr)&mVU->cycles, 0);
SUB32ItoM((uptr)&mVU->cycles, mVUcycles);
u8* jmp8 = JG8(0);
MOV32ItoR(gprT2, xPC);
if (!vuIndex) CALLFunc((uptr)mVUwarning0);
@ -200,7 +200,6 @@ microVUt(void) mVUtestCycles() {
MOV32ItoR(gprR, Roffset); // Restore gprR
mVUendProgram<vuIndex>(0, 0, sI, 0, cI);
x86SetJ8(jmp8);
SUB32ItoM((uptr)&mVU->cycles, mVUcycles);
}
//------------------------------------------------------------------
@ -266,8 +265,7 @@ microVUt(void*) __fastcall mVUcompile(u32 startPC, uptr pState) {
// Sets Up Flag instances
int xStatus[4], xMac[4], xClip[4];
int xCycles = mVUsetFlags<vuIndex>(xStatus, xMac, xClip);
//mVUtestCycles<vuIndex>(); //uncomment to re-enable breaking on bad programms, costs a few fps
mVUtestCycles<vuIndex>();
// Second Pass
iPC = mVUstartPC;

2
pcsx2/x86/microVU_Flags.inl
View File

@ -52,7 +52,7 @@ microVUt(void) mVUstatusFlagOp() {
}
}
iPC = curPC;
DevCon::Notice("microVU%d: FSSET Optimization", params vuIndex);
DevCon::Status("microVU%d: FSSET Optimization", params vuIndex);
}
int findFlagInst(int* fFlag, int cycles) {

12
pcsx2/x86/microVU_Upper.inl
View File

@ -55,23 +55,23 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
SSE_MOVMSKPS_XMM_to_R32(mReg, regT2); // Move the sign bits of the t1reg
AND32ItoR(mReg, AND_XYZW); // Grab "Is Signed" bits from the previous calculation
pjmp = JZ8(0); // Skip if none are
if (doStatus) pjmp = JZ8(0); // Skip if none are
if (doMac) SHL32ItoR(mReg, 4 + ADD_XYZW);
if (doStatus) OR32ItoR(sReg, 0x82); // SS, S flags
if (_XYZW_SS) pjmp2 = JMP8(0); // If negative and not Zero, we can skip the Zero Flag checking
x86SetJ8(pjmp);
if (_XYZW_SS && doStatus) pjmp2 = JMP8(0); // If negative and not Zero, we can skip the Zero Flag checking
if (doStatus) x86SetJ8(pjmp);
//-------------------------Check for Zero flags------------------------------
AND32ItoR(gprT2, AND_XYZW); // Grab "Is Zero" bits from the previous calculation
pjmp = JZ8(0); // Skip if none are
if (doStatus) pjmp = JZ8(0); // Skip if none are
if (doMac) { SHIFT_XYZW(gprT2); OR32RtoR(mReg, gprT2); }
if (doStatus) { OR32ItoR(sReg, 0x41); } // ZS, Z flags
x86SetJ8(pjmp);
if (doStatus) x86SetJ8(pjmp);
//-------------------------Write back flags------------------------------
if (_XYZW_SS) x86SetJ8(pjmp2); // If we skipped the Zero Flag Checking, return here
if (_XYZW_SS && doStatus) x86SetJ8(pjmp2); // If we skipped the Zero Flag Checking, return here
if (doMac) mVUallocMFLAGb<vuIndex>(mReg, fmInstance); // Set Mac Flag
}