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Remove all MMX and XMM register freeze code. 

DevNote: I could have left the code for the freezes in, except I *really* don't want us to ever have to resort to using such a system ever again in the future.  For anything. (its just not safe on modern optimizing compilers)

git-svn-id: http://pcsx2.googlecode.com/svn/trunk@3392 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
Jake.Stine 2010-07-05 01:12:38 +00:00
parent 1394b9e03c
commit 4f9a5c6876
24 changed files with 7 additions and 397 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
common/build/x86emitter/x86emitter.cbp
View File

@ -171,7 +171,6 @@
<Unit filename="../../src/x86emitter/legacy_sse.cpp" />
<Unit filename="../../src/x86emitter/movs.cpp" />
<Unit filename="../../src/x86emitter/simd.cpp" />
<Unit filename="../../src/x86emitter/tools.cpp" />
<Unit filename="../../src/x86emitter/x86emitter.cpp" />
<Extensions>
<envvars />

4
common/build/x86emitter/x86emitter.vcproj
View File

@ -266,10 +266,6 @@
RelativePath="..\..\src\x86emitter\simd.cpp"
>
</File>
<File
RelativePath="..\..\src\x86emitter\tools.cpp"
>
</File>
<File
RelativePath="..\..\src\x86emitter\x86emitter.cpp"
>

29
common/include/x86emitter/tools.h
View File

@ -198,35 +198,6 @@ union SSE_MXCSR
extern SSE_MXCSR MXCSR_Mask;
//////////////////////////////////////////////////////////////////////////////////////////
extern __aligned16 x86capabilities x86caps;
extern bool g_EEFreezeRegs;
// when using mmx/xmm regs, use these functions.
namespace MMXRegisters
{
extern void Freeze();
extern void Thaw();
extern bool Saved();
extern __aligned16 u64 data[8];
};
namespace XMMRegisters
{
extern void Freeze();
extern void Thaw();
extern bool Saved();
extern __aligned16 u64 data[2*iREGCNT_XMM];
};
namespace Registers
{
extern void Freeze();
extern void Thaw();
extern bool Saved();
};

1
common/src/x86emitter/CMakeLists.txt
View File

@ -117,7 +117,6 @@ set(x86emitterSources
movs.cpp
PrecompiledHeader.cpp
simd.cpp
tools.cpp
x86emitter.cpp)
# variable with all headers of this library

265
common/src/x86emitter/tools.cpp
View File

@ -1,265 +0,0 @@
/* PCSX2 - PS2 Emulator for PCs
* Copyright (C) 2002-2010 PCSX2 Dev Team
*
* PCSX2 is free software: you can redistribute it and/or modify it under the terms
* of the GNU Lesser General Public License as published by the Free Software Found-
* ation, either version 3 of the License, or (at your option) any later version.
*
* PCSX2 is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
* PURPOSE. See the GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along with PCSX2.
* If not, see <http://www.gnu.org/licenses/>.
*/
#include "PrecompiledHeader.h"
#include "tools.h"
// To make sure regs don't get changed while in the recompiler,
// use Freeze/Thaw in MMXRegisters, XMMRegisters, & Registers.
// used to disable register freezing during cpuBranchTests (registers
// are safe then since they've been completely flushed)
bool g_EEFreezeRegs = false;
/////////////////////////////////////////////////////////////////////
// MMX Register Freezing
//
namespace MMXRegisters
{
u8 stack_depth = 0;
__aligned16 u64 data[8];
__forceinline bool Saved()
{
return false;
//return (stack_depth > 0);
}
__forceinline void Freeze()
{
return;
if (!g_EEFreezeRegs) return;
//DevCon.Warning("MMXRegisters::Freeze: depth[%d]\n", stack_depth);
stack_depth++;
if (stack_depth > 1)
{
//DevCon.Warning("MMX Already Saved!\n");
return;
}
#ifdef _MSC_VER
__asm {
mov ecx, offset data
movntq mmword ptr [ecx+0], mm0
movntq mmword ptr [ecx+8], mm1
movntq mmword ptr [ecx+16], mm2
movntq mmword ptr [ecx+24], mm3
movntq mmword ptr [ecx+32], mm4
movntq mmword ptr [ecx+40], mm5
movntq mmword ptr [ecx+48], mm6
movntq mmword ptr [ecx+56], mm7
emms
}
#else
__asm__ volatile(
".intel_syntax noprefix\n"
"movq [%[data]+0x00], mm0\n"
"movq [%[data]+0x08], mm1\n"
"movq [%[data]+0x10], mm2\n"
"movq [%[data]+0x18], mm3\n"
"movq [%[data]+0x20], mm4\n"
"movq [%[data]+0x28], mm5\n"
"movq [%[data]+0x30], mm6\n"
"movq [%[data]+0x38], mm7\n"
"emms\n"
".att_syntax\n" : : [data]"r"(data) : "memory"
);
#endif
}
__forceinline void Thaw()
{
return;
if (!g_EEFreezeRegs) return;
//DevCon.Warning("MMXRegisters::Thaw: depth[%d]\n", stack_depth);
if (!Saved())
{
//DevCon.Warning("MMX Not Saved!\n");
return;
}
stack_depth--;
if (Saved()) return;
#ifdef _MSC_VER
__asm {
mov ecx, offset data
movq mm0, mmword ptr [ecx+0]
movq mm1, mmword ptr [ecx+8]
movq mm2, mmword ptr [ecx+16]
movq mm3, mmword ptr [ecx+24]
movq mm4, mmword ptr [ecx+32]
movq mm5, mmword ptr [ecx+40]
movq mm6, mmword ptr [ecx+48]
movq mm7, mmword ptr [ecx+56]
emms
}
#else
__asm__ volatile(
".intel_syntax noprefix\n"
"movq mm0, [%[data]+0x00]\n"
"movq mm1, [%[data]+0x08]\n"
"movq mm2, [%[data]+0x10]\n"
"movq mm3, [%[data]+0x18]\n"
"movq mm4, [%[data]+0x20]\n"
"movq mm5, [%[data]+0x28]\n"
"movq mm6, [%[data]+0x30]\n"
"movq mm7, [%[data]+0x38]\n"
"emms\n"
".att_syntax\n" : : [data]"r"(data) : "memory"
);
#endif
}
}
//////////////////////////////////////////////////////////////////////
// XMM Register Freezing
//
namespace XMMRegisters
{
u8 stack_depth = 0;
__aligned16 u64 data[2*iREGCNT_XMM];
__forceinline bool Saved()
{
return false;
//return ( stack_depth > 0);
}
__forceinline void Freeze()
{
return;
if (!g_EEFreezeRegs) return;
//DevCon.Warning("XMMRegisters::Freeze: depth[%d]\n", Depth());
stack_depth++;
if (stack_depth > 1)
{
//DevCon.Warning("XMM Already saved\n");
return;
}
#ifdef _MSC_VER
__asm {
mov ecx, offset data
movaps xmmword ptr [ecx+0x00], xmm0
movaps xmmword ptr [ecx+0x10], xmm1
movaps xmmword ptr [ecx+0x20], xmm2
movaps xmmword ptr [ecx+0x30], xmm3
movaps xmmword ptr [ecx+0x40], xmm4
movaps xmmword ptr [ecx+0x50], xmm5
movaps xmmword ptr [ecx+0x60], xmm6
movaps xmmword ptr [ecx+0x70], xmm7
}
#else
__asm__ volatile(
".intel_syntax noprefix\n"
"movaps [%[data]+0x00], xmm0\n"
"movaps [%[data]+0x10], xmm1\n"
"movaps [%[data]+0x20], xmm2\n"
"movaps [%[data]+0x30], xmm3\n"
"movaps [%[data]+0x40], xmm4\n"
"movaps [%[data]+0x50], xmm5\n"
"movaps [%[data]+0x60], xmm6\n"
"movaps [%[data]+0x70], xmm7\n"
".att_syntax\n" : : [data]"r"(data) : "memory"
);
#endif // _MSC_VER
}
__forceinline void Thaw()
{
return;
if (!g_EEFreezeRegs) return;
//DevCon.Warning("XMMRegisters::Thaw: depth[%d]\n", Depth());
if (!Saved())
{
//DevCon.Warning("XMM Regs not saved!\n");
return;
}
// TODO: really need to backup all regs?
stack_depth--;
if (Saved()) return;
#ifdef _MSC_VER
__asm
{
mov ecx, offset data
movaps xmm0, xmmword ptr [ecx+0x00]
movaps xmm1, xmmword ptr [ecx+0x10]
movaps xmm2, xmmword ptr [ecx+0x20]
movaps xmm3, xmmword ptr [ecx+0x30]
movaps xmm4, xmmword ptr [ecx+0x40]
movaps xmm5, xmmword ptr [ecx+0x50]
movaps xmm6, xmmword ptr [ecx+0x60]
movaps xmm7, xmmword ptr [ecx+0x70]
}
#else
__asm__ volatile(
".intel_syntax noprefix\n"
"movaps xmm0, [%[data]+0x00]\n"
"movaps xmm1, [%[data]+0x10]\n"
"movaps xmm2, [%[data]+0x20]\n"
"movaps xmm3, [%[data]+0x30]\n"
"movaps xmm4, [%[data]+0x40]\n"
"movaps xmm5, [%[data]+0x50]\n"
"movaps xmm6, [%[data]+0x60]\n"
"movaps xmm7, [%[data]+0x70]\n"
".att_syntax\n" : : [data]"r"(data) : "memory"
);
#endif // _MSC_VER
}
};
//////////////////////////////////////////////////////////////////////
// Register Freezing
//
namespace Registers
{
// MMX registers should not be needing freezes anymore (speedup!)
__forceinline bool Saved()
{
return false; //(XMMRegisters::Saved() /*|| MMXRegisters::Saved()*/ );
}
__forceinline void Freeze()
{
//XMMRegisters::Freeze();
//MMXRegisters::Freeze();
}
__forceinline void Thaw()
{
//XMMRegisters::Thaw();
//MMXRegisters::Thaw();
}
}

9
common/src/x86emitter/x86emitter.cpp
View File

@ -30,9 +30,6 @@
#include "PrecompiledHeader.h"
#include "internal.h"
// defined in tools.cpp
//extern __aligned16 u64 g_globalXMMData[2*iREGCNT_XMM];
#include "tools.h"
// ------------------------------------------------------------------------
@ -919,14 +916,16 @@ __emitinline void xBSWAP( const xRegister32& to )
xWrite8( 0xC8 | to.Id );
}
static __aligned16 u64 xmm_data[iREGCNT_XMM*2];
__emitinline void xStoreReg( const xRegisterSSE& src )
{
xMOVDQA( ptr[&XMMRegisters::data[src.Id*2]], src );
xMOVDQA( ptr[&xmm_data[src.Id*2]], src );
}
__emitinline void xRestoreReg( const xRegisterSSE& dest )
{
xMOVDQA( dest, ptr[&XMMRegisters::data[dest.Id*2]] );
xMOVDQA( dest, ptr[&xmm_data[dest.Id*2]] );
}
}

4
pcsx2/Counters.cpp
View File

@ -222,8 +222,6 @@ static void vSyncInfoCalc( vSyncTimingInfo* info, Fixed100 framesPerSecond, u32
u32 UpdateVSyncRate()
{
Registers::Freeze();
// Notice: (and I probably repeat this elsewhere, but it's worth repeating)
// The PS2's vsync timer is an *independent* crystal that is fixed to either 59.94 (NTSC)
// or 50.0 (PAL) Hz. It has *nothing* to do with real TV timings or the real vsync of
@ -277,8 +275,6 @@ u32 UpdateVSyncRate()
m_iStart = GetCPUTicks();
Registers::Thaw();
return (u32)m_iTicks;
}

2
pcsx2/FiFo.cpp
View File

@ -195,7 +195,6 @@ void __fastcall WriteFIFO_page_6(u32 mem, const mem128_t *value)
nloop0_packet[1] = psHu32(GIF_FIFO + 4);
nloop0_packet[2] = psHu32(GIF_FIFO + 8);
nloop0_packet[3] = psHu32(GIF_FIFO + 12);
Registers::Freeze();
GetMTGS().PrepDataPacket(GIF_PATH_3, (u8*)nloop0_packet, 1);
u64* data = (u64*)GetMTGS().GetDataPacketPtr();
data[0] = value[0];
@ -207,7 +206,6 @@ void __fastcall WriteFIFO_page_6(u32 mem, const mem128_t *value)
gifRegs->stat.APATH = GIF_APATH_IDLE;
if(gifRegs->stat.P1Q) gsPath1Interrupt();
}
Registers::Thaw();
}
void __fastcall WriteFIFO_page_7(u32 mem, const mem128_t *value)

6
pcsx2/Gif.cpp
View File

@ -56,7 +56,6 @@ void gsPath1Interrupt()
if((gifRegs->stat.APATH <= GIF_APATH1 || (gifRegs->stat.IP3 == true && gifRegs->stat.APATH == GIF_APATH3)) && Path1WritePos > 0 && !gifRegs->stat.PSE)
{
Registers::Freeze();
while(Path1WritePos > 0)
{
u32 size = GetMTGS().PrepDataPacket(GIF_PATH_1, Path1Buffer + (Path1ReadPos * 16), (Path1WritePos - Path1ReadPos));
@ -81,7 +80,6 @@ void gsPath1Interrupt()
gifRegs->stat.P1Q = false;
}
}
Registers::Thaw();
}
else
{
@ -183,12 +181,10 @@ int _GIFchain()
static __forceinline void GIFchain()
{
Registers::Freeze();
// qwc check now done outside this function
// Voodoocycles
// >> 2 so Drakan and Tekken 5 don't mess up in some PATH3 transfer. Cycles to interrupt were getting huge..
/*if (gif->qwc)*/ gscycles+= ( _GIFchain() * BIAS); /* guessing */
Registers::Thaw();
}
static __forceinline bool checkTieBit(tDMA_TAG* &ptag)
@ -605,13 +601,11 @@ void mfifoGIFtransfer(int qwc)
}
}
Registers::Freeze();
if (!mfifoGIFchain())
{
Console.WriteLn("GIF dmaChain error size=%d, madr=%lx, tadr=%lx", gif->qwc, gif->madr, gif->tadr);
gifstate = GIF_STATE_STALL;
}
Registers::Thaw();
if ((gif->qwc == 0) && (gifstate & GIF_STATE_DONE)) gifstate = GIF_STATE_STALL;
CPU_INT(11,mfifocycles);

8
pcsx2/HwWrite.cpp
View File

@ -31,9 +31,7 @@ static bool QuickDmaExec( void (*func)(), u32 mem)
if (reg->chcr.STR && dmacRegs->ctrl.DMAE && !psHu8(DMAC_ENABLER+2))
{
Registers::Freeze();
func();
Registers::Thaw();
ret = true;
}
@ -129,9 +127,7 @@ static __forceinline void DmaExec8( void (*func)(), u32 mem, u8 value )
if (reg->chcr.STR && dmacRegs->ctrl.DMAE && !psHu8(DMAC_ENABLER+2))
{
Registers::Freeze();
func();
Registers::Thaw();
}
else if(reg->chcr.STR)
{
@ -209,9 +205,7 @@ static __forceinline void DmaExec16( void (*func)(), u32 mem, u16 value )
if (reg->chcr.STR && dmacRegs->ctrl.DMAE && !psHu8(DMAC_ENABLER+2))
{
Registers::Freeze();
func();
Registers::Thaw();
}
else if(reg->chcr.STR)
{
@ -295,9 +289,7 @@ static void DmaExec( void (*func)(), u32 mem, u32 value )
if (reg->chcr.STR && dmacRegs->ctrl.DMAE && !psHu8(DMAC_ENABLER+2))
{
Registers::Freeze();
func();
Registers::Thaw();
}
else if(reg->chcr.STR)
{

4
pcsx2/IPU/yuv2rgb.cpp
View File

@ -78,8 +78,6 @@ static __aligned16 u16 yuv2rgb_temp[3][8];
// This could potentially be improved for SSE4
__releaseinline void yuv2rgb_sse2(void)
{
XMMRegisters::Freeze();
#if defined(_MSC_VER) || defined(__INTEL_COMPILER)
__asm {
mov eax, 1
@ -368,8 +366,6 @@ ihatemsvc:
#else
# error Unsupported compiler
#endif
XMMRegisters::Thaw();
}
void yuv2rgb_init(void)

3
pcsx2/Interpreter.cpp
View File

@ -380,8 +380,6 @@ static void intEventTest()
static void intExecute()
{
g_EEFreezeRegs = false;
try {
if (g_SkipBiosHack) {
do
@ -409,7 +407,6 @@ static void intCheckExecutionState()
static void intStep()
{
g_EEFreezeRegs = false;
execI();
}

4
pcsx2/IopDma.cpp
View File

@ -199,11 +199,9 @@ void psxDma9(u32 madr, u32 bcr, u32 chcr)
/*if (sif0.ee.busy)
{*/
XMMRegisters::Freeze();
SIF0Dma();
psHu32(SBUS_F240) &= ~0x20;
psHu32(SBUS_F240) &= ~0x2000;
XMMRegisters::Thaw();
//}
}
@ -216,12 +214,10 @@ void psxDma10(u32 madr, u32 bcr, u32 chcr)
/*if (sif1.ee.busy)
{*/
XMMRegisters::Freeze();
SIF1Dma();
psHu32(SBUS_F240) &= ~0x40;
psHu32(SBUS_F240) &= ~0x100;
psHu32(SBUS_F240) &= ~0x4000;
XMMRegisters::Thaw();
//}
}

1
pcsx2/R5900.h
View File

@ -24,7 +24,6 @@ class BaseR5900Exception;
// them in iR5900.h would mean having to include that into more files than I care to
// right now, so we're sticking them here for now until a better solution comes along.
extern bool g_EEFreezeRegs;
extern bool g_SkipBiosHack;
extern bool g_GameStarted;

4
pcsx2/Sif0.cpp
View File

@ -344,11 +344,9 @@ __forceinline void dmaSIF0()
/*if (sif0.iop.busy)
{*/
XMMRegisters::Freeze();
hwIntcIrq(INTC_SBUS);
hwIntcIrq(INTC_SBUS);
SIF0Dma();
psHu32(SBUS_F240) &= ~0x20;
psHu32(SBUS_F240) &= ~0x2000;
XMMRegisters::Thaw();
//}
}

2
pcsx2/Sif1.cpp
View File

@ -343,11 +343,9 @@ __forceinline void dmaSIF1()
/*if (sif1.iop.busy)
{*/
XMMRegisters::Freeze();
SIF1Dma();
psHu32(SBUS_F240) &= ~0x40;
psHu32(SBUS_F240) &= ~0x100;
psHu32(SBUS_F240) &= ~0x4000;
XMMRegisters::Thaw();
//}
}

4
pcsx2/Vif1_Dma.cpp
View File

@ -77,8 +77,6 @@ void vif1TransferToMemory()
// stuff from the GS. The *only* way to handle this case safely is to flush the GS
// completely and execute the transfer there-after.
//Console.Warning("Real QWC %x", vif1ch->qwc);
XMMRegisters::Freeze();
size = min((u32)vif1ch->qwc, vif1.GSLastDownloadSize);
if (GSreadFIFO2 == NULL)
@ -129,8 +127,6 @@ void vif1TransferToMemory()
}
XMMRegisters::Thaw();
g_vifCycles += vif1ch->qwc * 2;
vif1ch->madr += vif1ch->qwc * 16; // mgs3 scene changes
if(vif1.GSLastDownloadSize >= vif1ch->qwc)

4
pcsx2/Vif_Codes.cpp
View File

@ -161,7 +161,6 @@ template<int idx> _f int _vifCode_Direct(int pass, u8* data, bool isDirectHL) {
gifRegs->stat.clear_flags(GIF_STAT_P2Q);
Registers::Freeze();
nVifStruct& v = nVif[1];
const int ret = aMin(vif1.vifpacketsize, vif1.tag.size);
u32 size = ret << 2;
@ -181,7 +180,6 @@ template<int idx> _f int _vifCode_Direct(int pass, u8* data, bool isDirectHL) {
v.bSize += vif1.vifpacketsize << 2;
v.bPtr += vif1.vifpacketsize << 2;
vif1.tag.size -= vif1.vifpacketsize;
Registers::Thaw();
if(vif1.tag.size == 0)
{
DevCon.Warning("Missaligned packet on DIRECT end!");
@ -214,7 +212,6 @@ template<int idx> _f int _vifCode_Direct(int pass, u8* data, bool isDirectHL) {
vif1.cmd = 0;
}
vif1.vifstalled = true;
Registers::Thaw();
return ret;
}
else
@ -228,7 +225,6 @@ template<int idx> _f int _vifCode_Direct(int pass, u8* data, bool isDirectHL) {
vif1.cmd = 0;
}
vif1.vifstalled = true;
Registers::Thaw();
return count << 2;
}
}

6
pcsx2/x86/iR3000A.cpp
View File

@ -122,9 +122,7 @@ static DynGenFunc* iopExitRecompiledCode = NULL;
static void recEventTest()
{
pxAssert(!Registers::Saved());
_cpuBranchTest_Shared();
pxAssert(!Registers::Saved());
}
// parameters:
@ -882,10 +880,6 @@ static __noinline s32 recExecuteBlock( s32 eeCycles )
psxBreak = 0;
psxCycleEE = eeCycles;
// Register freezing note:
// The IOP does not use mmx/xmm registers, so we don't modify the status
// of the g_EEFreezeRegs here.
// [TODO] recExecuteBlock could be replaced by a direct call to the iopEnterRecompiledCode()
// (by assigning its address to the psxRec structure). But for that to happen, we need
// to move psxBreak/psxCycleEE update code to emitted assembly code. >_< --air

5
pcsx2/x86/iVU1micro.cpp
View File

@ -127,8 +127,6 @@ namespace VU1micro
SysPrintf("(%08d) StartPC = 0x%04x\n", runAmount, VU1.VI[REG_TPC].UL);
#endif
XMMRegisters::Freeze();
runCount++;
memcpy_const((u8*)backVUregs, (u8*)&VU1, sizeof(VURegs));
memcpy_const((u8*)backVUmem, (u8*)VU1.Mem, 0x4000);
@ -243,7 +241,6 @@ namespace VU1micro
}
VUtestPause();
XMMRegisters::Thaw();
}
}
#else
@ -275,7 +272,6 @@ namespace VU1micro
SysPrintf("(%08d) StartPC = 0x%04x\n", runAmount, VU1.VI[REG_TPC].UL);
#endif
XMMRegisters::Freeze();
if (useMVU1) runVUrec(VU1.VI[REG_TPC].UL, 3000000, 1);
else {
if (VU1.VI[REG_TPC].UL >= VU1.maxmicro) {
@ -285,7 +281,6 @@ namespace VU1micro
SuperVUExecuteProgram(VU1.VI[REG_TPC].UL & 0x3fff, 1);
} while( VU0.VI[REG_VPU_STAT].UL & 0x100 );
}
XMMRegisters::Thaw();
VUtestPause();
}
}*/

6
pcsx2/x86/ix86-32/iR5900-32.cpp
View File

@ -352,9 +352,7 @@ static DynGenFunc* ExitRecompiledCode = NULL;
static void recEventTest()
{
pxAssert(!Registers::Saved());
_cpuBranchTest_Shared();
pxAssert(!Registers::Saved());
}
// parameters:
@ -750,7 +748,6 @@ static void recExecute()
#if PCSX2_SEH
eeRecIsReset = false;
m_vmException = NULL;
g_EEFreezeRegs = true;
ScopedBool executing(m_recExecutingCode);
try {
@ -765,7 +762,6 @@ static void recExecute()
if( !setjmp( m_SetJmp_StateCheck ) )
{
eeRecIsReset = false;
g_EEFreezeRegs = true;
// Important! Most of the console logging and such has cancel points in it. This is great
// in Windows, where SEH lets us safely kill a thread from anywhere we want. This is bad
@ -1258,8 +1254,6 @@ static void __fastcall PreBlockCheck( u32 blockpc )
static int curcount = 0;
const int skip = 0;
pxAssert(!Registers::Saved());
/*if( blockpc != 0x81fc0 ) {//&& lastrec != g_lastpc ) {
curcount++;

24
pcsx2/x86/microVU.cpp
View File

@ -350,36 +350,16 @@ void recMicroVU0::Execute(u32 cycles) {
if(!(VU0.VI[REG_VPU_STAT].UL & 1)) return;
XMMRegisters::Freeze();
// Sometimes games spin on vu0, so be careful with this value
// woody hangs if too high on sVU (untested on mVU)
// Edit: Need to test this again, if anyone ever has a "Woody" game :p
try {
((mVUrecCall)microVU0.startFunct)(VU0.VI[REG_TPC].UL, cycles);
} catch (BaseException& pxDevelCode(ex)) {
pxFailDev( wxsFormat(L"microVU0 recompiler exception: " + ex.FormatDiagnosticMessage()));
} catch (std::exception& pxDevelCode(ex)) {
pxFailDev( wxsFormat(L"microVU0 recompiler exception: " + Exception::RuntimeError(ex).FormatDiagnosticMessage()));
}
XMMRegisters::Thaw();
((mVUrecCall)microVU0.startFunct)(VU0.VI[REG_TPC].UL, cycles);
}
void recMicroVU1::Execute(u32 cycles) {
pxAssert(mvu1_allocated); // please allocate me first! :|
if(!(VU0.VI[REG_VPU_STAT].UL & 0x100)) return;
XMMRegisters::Freeze();
// Exception note: It's bad news if the recompiler throws any exceptions, so we have a clause to
// assert if an exception occurs. The rec should be pretty much exception safe, except for
// critical errors that would result in a crash regardless.
try {
((mVUrecCall)microVU1.startFunct)(VU1.VI[REG_TPC].UL, vu1RunCycles);
} catch (BaseException& pxDevelCode(ex)) {
pxFailDev( wxsFormat(L"microVU1 recompiler exception: " + ex.FormatDiagnosticMessage()));
} catch (std::exception& pxDevelCode(ex)) {
pxFailDev( wxsFormat(L"microVU1 recompiler exception: " + Exception::RuntimeError(ex).FormatDiagnosticMessage()));
}
XMMRegisters::Thaw();
((mVUrecCall)microVU1.startFunct)(VU1.VI[REG_TPC].UL, vu1RunCycles);
}
void recMicroVU0::Clear(u32 addr, u32 size) {

2
pcsx2/x86/newVif_Unpack.cpp
View File

@ -114,7 +114,6 @@ static _f void incVUptrBy16(int vuidx, u8* &ptr, const u8* vuMemBase) {
}
int nVifUnpack(int idx, u8* data) {
XMMRegisters::Freeze();
nVifStruct& v = nVif[idx];
vif = v.vif;
vifRegs = v.vifRegs;
@ -144,7 +143,6 @@ int nVifUnpack(int idx, u8* data) {
vif->tag.size -= ret;
}
XMMRegisters::Thaw();
return ret;
}

6
pcsx2/x86/sVU_zerorec.cpp
View File

@ -4636,10 +4636,8 @@ void recSuperVU0::Execute(u32 cycles)
{
if ((VU0.VI[REG_VPU_STAT].UL & 1) == 0) return;
XMMRegisters::Freeze();
runCycles = cycles;
SuperVUExecuteProgram(VU0.VI[REG_TPC].UL & 0xfff, 0);
XMMRegisters::Thaw();
}
void recSuperVU0::Clear(u32 Addr, u32 Size)
@ -4679,8 +4677,6 @@ void recSuperVU1::Execute(u32 cycles)
// [TODO] Debugging pre- and post- hooks?
XMMRegisters::Freeze();
if (VU1.VI[REG_TPC].UL >= VU1.maxmicro) {
Console.Error("VU1 memory overflow!!: %x", VU1.VI[REG_TPC].UL);
}
@ -4688,8 +4684,6 @@ void recSuperVU1::Execute(u32 cycles)
do { // while loop needed since not always will return finished
SuperVUExecuteProgram(VU1.VI[REG_TPC].UL & 0x3fff, 1);
} while( VU0.VI[REG_VPU_STAT].UL&0x100 );
XMMRegisters::Thaw();
}
void recSuperVU1::Clear(u32 Addr, u32 Size)