mirror of https://github.com/PCSX2/pcsx2.git
implemented alot of microVU shit...
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@708 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
cottonvibes
parent
56f802c80f
commit
4f63ac1101
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@ -33,12 +33,12 @@ PCSX2_ALIGNED16(const u32 mVU_absclip[4]) = {0x7fffffff, 0x7fffffff, 0x7fffffff,
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PCSX2_ALIGNED16(const u32 mVU_signbit[4]) = {0x80000000, 0x80000000, 0x80000000, 0x80000000};
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PCSX2_ALIGNED16(const u32 mVU_minvals[4]) = {0xff7fffff, 0xff7fffff, 0xff7fffff, 0xff7fffff};
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PCSX2_ALIGNED16(const u32 mVU_maxvals[4]) = {0x7f7fffff, 0x7f7fffff, 0x7f7fffff, 0x7f7fffff};
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PCSX2_ALIGNED16(const float mVU_FTOI_4[4]) = { 16.0, 16.0, 16.0, 16.0 };
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PCSX2_ALIGNED16(const float mVU_FTOI_12[4]) = { 4096.0, 4096.0, 4096.0, 4096.0 };
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PCSX2_ALIGNED16(const float mVU_FTOI_15[4]) = { 32768.0, 32768.0, 32768.0, 32768.0 };
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PCSX2_ALIGNED16(const float mVU_ITOF_4[4]) = { 0.0625f, 0.0625f, 0.0625f, 0.0625f };
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PCSX2_ALIGNED16(const float mVU_ITOF_12[4]) = { 0.000244140625, 0.000244140625, 0.000244140625, 0.000244140625 };
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PCSX2_ALIGNED16(const float mVU_ITOF_15[4]) = { 0.000030517578125, 0.000030517578125, 0.000030517578125, 0.000030517578125 };
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PCSX2_ALIGNED16(const float mVU_FTOI_4[4]) = {16.0, 16.0, 16.0, 16.0};
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PCSX2_ALIGNED16(const float mVU_FTOI_12[4]) = {4096.0, 4096.0, 4096.0, 4096.0};
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PCSX2_ALIGNED16(const float mVU_FTOI_15[4]) = {32768.0, 32768.0, 32768.0, 32768.0};
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PCSX2_ALIGNED16(const float mVU_ITOF_4[4]) = {0.0625f, 0.0625f, 0.0625f, 0.0625f};
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PCSX2_ALIGNED16(const float mVU_ITOF_12[4]) = {0.000244140625, 0.000244140625, 0.000244140625, 0.000244140625};
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PCSX2_ALIGNED16(const float mVU_ITOF_15[4]) = {0.000030517578125, 0.000030517578125, 0.000030517578125, 0.000030517578125};
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//------------------------------------------------------------------
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@ -270,6 +270,7 @@ __declspec(naked) void __fastcall endVU0(u32 startPC, u32 cycles) {
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pop ebx;
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ldmxcsr g_sseMXCSR
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emms
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ret
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}
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@ -38,19 +38,21 @@ struct microAllocInfo {
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u8 p;
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u8 r;
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u16 info[pSize];// bit 0 = NOP?
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// bit 1 = Read Fd from backup memory?
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// bit 2 = Read Fs from backup memory?
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// bit 3 = Read Ft from backup memory?
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// bit 4 = ACC1 or ACC2?
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// bit 1 = Used with bit 2 to make a 2-bit key for ACC write instance
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// bit 2 = (00 = instance #0, 01 = instance #1, 10 = instance #2, 11 = instance #3)
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// bit 3 = Used with bit 4 to make a 2-bit key for ACC read instance
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// bit 4 = (00 = instance #0, 01 = instance #1, 10 = instance #2, 11 = instance #3)
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// bit 5 = Read Q1/P1 or backup?
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// bit 6 = Write to Q2/P2?
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// bit 7 = Write Fd/Acc/Result to backup memory?
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// bit 7 = Write VI(Fd) Result to backup memory?
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// bit 8 = Update Mac Flags?
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// bit 9 = Update Status Flags?
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// bit 10 = Used with bit 11 to make a 2-bit key for mac flag instance
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// bit 11 = (00 = instance #0, 01 = instance #1, 10 = instance #2, 11 = instance #3)
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// bit 12 = Used with bit 13 to make a 2-bit key for status flag instance
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// bit 13 = (00 = instance #0, 01 = instance #1, 10 = instance #2, 11 = instance #3)
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// bit 14 = Read VI(Fs) from backup memory?
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// bit 15 = Read VI(Ft) from backup memory?
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u32 curPC;
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};
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@ -48,6 +48,7 @@
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//------------------------------------------------------------------
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// FMAC1 - Normal FMAC Opcodes
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//------------------------------------------------------------------
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microVUt(void) mVUallocFMAC1a(int& Fd, int& Fs, int& Ft) {
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microVU* mVU = mVUx;
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Fs = xmmFs;
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@ -85,6 +86,7 @@ microVUt(void) mVUallocFMAC1b(int& Fd) {
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//------------------------------------------------------------------
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// FMAC2 - ABS/FTOI/ITOF Opcodes
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//------------------------------------------------------------------
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microVUt(void) mVUallocFMAC2a(int& Fs, int& Ft) {
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microVU* mVU = mVUx;
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Fs = xmmFs;
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@ -164,4 +166,127 @@ microVUt(void) mVUallocFMAC3b(int& Fd) {
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mVUallocFMAC1b<vuIndex>(Fd);
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}
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//------------------------------------------------------------------
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// FMAC4 - FMAC Opcodes Storing Result to ACC
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//------------------------------------------------------------------
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#define getReg4(reg, _reg_) { \
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mVUloadReg<vuIndex>(reg, (uptr)&mVU->regs->VF[_reg_].UL[0], (_XYZW_SS) ? 15 : _X_Y_Z_W); \
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if (CHECK_VU_EXTRA_OVERFLOW) mVUclamp2<vuIndex>(reg, xmmT1, (_XYZW_SS) ? 15 : _X_Y_Z_W); \
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}
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#define getZero4(reg) { \
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if (_W) { mVUloadReg<vuIndex>(reg, (uptr)&mVU->regs->VF[0].UL[0], (_XYZW_SS) ? 15 : _X_Y_Z_W); } \
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else { SSE_XORPS_XMM_to_XMM(reg, reg); } \
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}
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#define getACC(reg) { \
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reg = xmmACC0 + writeACC; \
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if (_X_Y_Z_W != 15) { SSE_MOVAPS_XMM_to_XMM(reg, (xmmACC0 + prevACC)); } \
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}
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microVUt(void) mVUallocFMAC4a(int& ACC, int& Fs, int& Ft) {
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microVU* mVU = mVUx;
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Fs = xmmFs;
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Ft = xmmFt;
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getACC(ACC);
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if (_XYZW_SS && _X) {
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if (!_Fs_) { getZeroSS(Fs); }
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else { getReg(Fs, _Fs_); }
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if (_Ft_ == _Fs_) { Ft = Fs; }
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else {
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if (!_Ft_) { getZeroSS(Ft); }
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else { getReg(Ft, _Ft_); }
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}
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}
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else {
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if (!_Fs_) { getZero4(Fs); }
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else { getReg4(Fs, _Fs_); }
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if (_Ft_ == _Fs_) { Ft = Fs; }
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else {
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if (!_Ft_) { getZero4(Ft); }
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else { getReg4(Ft, _Ft_); }
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}
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}
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}
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microVUt(void) mVUallocFMAC4b(int& ACC, int& Fs) {
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microVU* mVU = mVUx;
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if (!_Fd_) return;
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if (CHECK_VU_OVERFLOW) mVUclamp1<vuIndex>(Fs, xmmT1, (_XYZW_SS && !_X) ? 15 : _X_Y_Z_W);
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mVUmergeRegs<vuIndex>(ACC, Fs, _X_Y_Z_W);
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}
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//------------------------------------------------------------------
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// FMAC5 - FMAC BC(xyzw) Opcodes Storing Result to ACC
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//------------------------------------------------------------------
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microVUt(void) mVUallocFMAC5a(int& ACC, int& Fs, int& Ft) {
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microVU* mVU = mVUx;
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Fs = xmmFs;
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Ft = xmmFt;
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getACC(ACC);
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if (_XYZW_SS && _X) {
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if (!_Fs_) { getZeroSS(Fs); }
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else { getReg(Fs, _Fs_); }
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if ( (_Ft_ == _Fs_) && _bc_x) {
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Ft = Fs;
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}
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else {
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if (!_Ft_) { getZero3SS(Ft); }
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else { getReg3SS(Ft, _Ft_); }
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}
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}
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else {
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if (!_Fs_) { getZero4(Fs); }
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else { getReg4(Fs, _Fs_); }
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if (!_Ft_) { getZero3(Ft); }
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else { getReg3(Ft, _Ft_); }
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}
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}
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microVUt(void) mVUallocFMAC5b(int& ACC, int& Fs) {
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mVUallocFMAC4b<vuIndex>(ACC, Fs);
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}
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//------------------------------------------------------------------
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// Flag Allocators
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//------------------------------------------------------------------
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#define getFlagReg(regX, fInst) { \
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switch (fInst) { \
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case 0: regX = gprF0; break; \
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case 1: regX = gprF1; break; \
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case 2: regX = gprF2; break; \
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case 3: regX = gprF3; break; \
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} \
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}
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microVUt(void) mVUallocSFLAGa(int reg, int fInstance) {
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getFlagReg(fInstance, fInstance);
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MOVZX32R16toR(reg, fInstance);
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}
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microVUt(void) mVUallocSFLAGb(int reg, int fInstance) {
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getFlagReg(fInstance, fInstance);
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MOV32RtoR(fInstance, reg);
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}
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microVUt(void) mVUallocMFLAGa(int reg, int fInstance) {
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getFlagReg(fInstance, fInstance);
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MOV32RtoR(reg, fInstance);
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SHR32ItoR(reg, 16);
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}
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microVUt(void) mVUallocMFLAGb(int reg, int fInstance) {
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getFlagReg(fInstance, fInstance);
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AND32ItoR(fInstance, 0xffff);
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SHL32ItoR(reg, 16);
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OR32RtoR(fInstance, reg);
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}
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#endif //PCSX2_MICROVU
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@ -63,20 +63,29 @@ PCSX2_ALIGNED16_EXTERN(const float mVU_ITOF_15[4]);
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#define xmmT1 0 // Temp Reg
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#define xmmFs 1 // Holds the Value of Fs (writes back result Fd)
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#define xmmFt 2 // Holds the Value of Ft
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#define xmmACC1 3 // Holds the Value of ACC
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#define xmmACC2 4 // Holds the Backup Value of ACC
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#define xmmPQ 5 // Holds the Value and Backup Values of P and Q regs
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#define xmmVI 6 // Holds VI regs 8, 9, 10, 11, 12, 13, 14, and 15
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#define xmmF 7 // Holds 4 instances of the status and mac flags (macflagX4::statusflagX4)
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#define xmmACC0 3 // Holds ACC Instance #0
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#define xmmACC1 4 // Holds ACC Instance #1
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#define xmmACC2 5 // Holds ACC Instance #2
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#define xmmACC3 6 // Holds ACC Instance #3
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#define xmmPQ 7 // Holds the Value and Backup Values of P and Q regs
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#define mmxT1 0 // Temp Reg
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#define mmxC 1 // Clip Flag?
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#define mmxVI0 2 // Holds VI 00 to 03?
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#define mmxVI1 3 // Holds VI 04 to 07?
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#define mmxVI2 4 // Holds VI 08 to 11?
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#define mmxVI3 5 // Holds VI 12 to 15?
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#define mmxM 6 // ?
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#define mmxS 7 // ?
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#define gprT1 0 // Temp Reg
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#define gprT2 1 // Temp Reg
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#define gprT3 2 // Temp Reg
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#define gprVI7 3 // VI 7
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#define gprT3 2 // Temp Reg?
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#define gprF0 3 // MAC Flag::Status Flag 0
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#define gprESP 4 // Don't use?
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#define gprVI5 5 // VI 6::5
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#define gprVI3 6 // VI 4::3
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#define gprVI1 7 // VI 2::1
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#define gprF1 5 // MAC Flag::Status Flag 1
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#define gprF2 6 // MAC Flag::Status Flag 2
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#define gprF3 7 // MAC Flag::Status Flag 3
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// Template Stuff
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#define mVUx (vuIndex ? µVU1 : µVU0)
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@ -88,16 +97,19 @@ PCSX2_ALIGNED16_EXTERN(const float mVU_ITOF_15[4]);
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#define mVUallocInfo mVU->prog.prog[mVU->prog.cur].allocInfo
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#define isNOP (mVUallocInfo.info[mVUallocInfo.curPC] & (1<<0))
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#define getFd (mVUallocInfo.info[mVUallocInfo.curPC] & (1<<1))
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#define getFs (mVUallocInfo.info[mVUallocInfo.curPC] & (1<<2))
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#define getFt (mVUallocInfo.info[mVUallocInfo.curPC] & (1<<3))
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#define setFd (mVUallocInfo.info[mVUallocInfo.curPC] & (1<<7))
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#define writeACC ((mVUallocInfo.info[mVUallocInfo.curPC] & (3<<1)) >> 1)
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#define prevACC (((u8)((mVUallocInfo.info[mVUallocInfo.curPC] & (3<<1)) >> 1) - 1) & 0x3)
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//#define setACCreg ((mVUallocInfo.info[mVUallocInfo.curPC] & (1<<1)) >> 1)
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//#define setACCmem (mVUallocInfo.info[mVUallocInfo.curPC] & (1<<2))
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//#define setFd (mVUallocInfo.info[mVUallocInfo.curPC] & (1<<7))
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#define doFlags (mVUallocInfo.info[mVUallocInfo.curPC] & (3<<8))
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#define doMac (mVUallocInfo.info[mVUallocInfo.curPC] & (1<<8))
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#define doStatus (mVUallocInfo.info[mVUallocInfo.curPC] & (1<<9))
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#define fmInstance ((mVUallocInfo.info[mVUallocInfo.curPC] & (3<<10)) + 4)
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#define fsInstance ((mVUallocInfo.info[mVUallocInfo.curPC] & (3<<12)) + 0)
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#define fpmInstance ((((u8)(mVUallocInfo.info[mVUallocInfo.curPC] & (3<<10)) - 1) & 0x3) + 4)
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#define fpsInstance ((((u8)(mVUallocInfo.info[mVUallocInfo.curPC] & (3<<10)) - 1) & 0x3) + 0)
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#define fmInstance ((mVUallocInfo.info[mVUallocInfo.curPC] & (3<<10)) >> 10)
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#define fsInstance ((mVUallocInfo.info[mVUallocInfo.curPC] & (3<<12)) >> 12)
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#define fpmInstance (((u8)((mVUallocInfo.info[mVUallocInfo.curPC] & (3<<10)) >> 10) - 1) & 0x3)
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#define fpsInstance (((u8)((mVUallocInfo.info[mVUallocInfo.curPC] & (3<<12)) >> 12) - 1) & 0x3)
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//#define getFs (mVUallocInfo.info[mVUallocInfo.curPC] & (1<<2))
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//#define getFt (mVUallocInfo.info[mVUallocInfo.curPC] & (1<<3))
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#include "microVU_Misc.inl"
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@ -152,4 +152,62 @@ microVUx(void) mVUsaveReg(int reg, u32 offset, int xyzw) {
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}
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}
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// Modifies the Source Reg!
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microVUx(void) mVUmergeRegs(int dest, int src, int xyzw) {
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xyzw &= 0xf;
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if ( (dest != src) && (xyzw != 0) ) {
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if ( cpucaps.hasStreamingSIMD4Extensions && (xyzw != 0x8) && (xyzw != 0xf) ) {
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xyzw = ((xyzw & 1) << 3) | ((xyzw & 2) << 1) | ((xyzw & 4) >> 1) | ((xyzw & 8) >> 3);
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SSE4_BLENDPS_XMM_to_XMM(dest, src, xyzw);
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}
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else {
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switch (xyzw) {
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case 1: SSE_MOVHLPS_XMM_to_XMM(src, dest);
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SSE_SHUFPS_XMM_to_XMM(dest, src, 0xc4);
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break;
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case 2: SSE_MOVHLPS_XMM_to_XMM(src, dest);
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SSE_SHUFPS_XMM_to_XMM(dest, src, 0x64);
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break;
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case 3: SSE_SHUFPS_XMM_to_XMM(dest, src, 0xe4);
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break;
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case 4: SSE_MOVSS_XMM_to_XMM(src, dest);
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SSE2_MOVSD_XMM_to_XMM(dest, src);
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break;
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case 5: SSE_SHUFPS_XMM_to_XMM(dest, src, 0xd8);
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SSE_SHUFPS_XMM_to_XMM(dest, dest, 0xd8);
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break;
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case 6: SSE_SHUFPS_XMM_to_XMM(dest, src, 0x9c);
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SSE_SHUFPS_XMM_to_XMM(dest, dest, 0x78);
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break;
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case 7: SSE_MOVSS_XMM_to_XMM(src, dest);
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SSE_MOVAPS_XMM_to_XMM(dest, src);
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break;
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case 8: SSE_MOVSS_XMM_to_XMM(dest, src);
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break;
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case 9: SSE_SHUFPS_XMM_to_XMM(dest, src, 0xc9);
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SSE_SHUFPS_XMM_to_XMM(dest, dest, 0xd2);
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break;
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case 10: SSE_SHUFPS_XMM_to_XMM(dest, src, 0x8d);
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SSE_SHUFPS_XMM_to_XMM(dest, dest, 0x72);
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break;
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case 11: SSE_MOVSS_XMM_to_XMM(dest, src);
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SSE_SHUFPS_XMM_to_XMM(dest, src, 0xe4);
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break;
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case 12: SSE2_MOVSD_XMM_to_XMM(dest, src);
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break;
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case 13: SSE_MOVHLPS_XMM_to_XMM(dest, src);
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SSE_SHUFPS_XMM_to_XMM(src, dest, 0x64);
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SSE_MOVAPS_XMM_to_XMM(dest, src);
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break;
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case 14: SSE_MOVHLPS_XMM_to_XMM(dest, src);
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SSE_SHUFPS_XMM_to_XMM(src, dest, 0xc4);
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SSE_MOVAPS_XMM_to_XMM(dest, src);
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break;
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default: SSE_MOVAPS_XMM_to_XMM(dest, src);
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break;
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}
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}
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}
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}
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#endif //PCSX2_MICROVU
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@ -24,7 +24,7 @@
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//------------------------------------------------------------------
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// Declarations
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//------------------------------------------------------------------
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#define mVUgetCode (vuIndex ? microVU1.regs->code : microVU0.regs->code)
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#define mVUgetCode (vuIndex ? microVU1.code : microVU0.code)
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microVUf(void) mVU_UPPER_FD_00();
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microVUf(void) mVU_UPPER_FD_01();
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@ -26,6 +26,7 @@
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|
||||
microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw) {
|
||||
microVU* mVU = mVUx;
|
||||
int sReg, mReg = gprT1;
|
||||
static u8 *pjmp, *pjmp2;
|
||||
static const int flipMask[16] = {0, 8, 4, 12, 2, 10, 6, 14, 1, 9, 5, 13, 3, 11, 7, 15};
|
||||
|
||||
|
|
@ -35,8 +36,9 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw) {
|
|||
if (!doMac) { regT1 = reg; }
|
||||
else SSE2_PSHUFD_XMM_to_XMM(regT1, reg, 0x1B); // Flip wzyx to xyzw
|
||||
if (doStatus) {
|
||||
SSE_PEXTRW_XMM_to_R32(gprT1, xmmF, fpsInstance); // Get Prev Status Flag
|
||||
AND16ItoR(gprT1, 0xff0); // Keep Sticky and D/I flags
|
||||
getFlagReg(sReg, fsInstance); // Set sReg to valid GPR by Cur Flag Instance
|
||||
mVUallocSFLAGa<vuIndex>(sReg, fpsInstance); // Get Prev Status Flag
|
||||
AND16ItoR(sReg, 0xff0); // Keep Sticky and D/I flags
|
||||
}
|
||||
|
||||
//-------------------------Check for Signed flags------------------------------
|
||||
|
|
@ -44,32 +46,31 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw) {
|
|||
// The following code makes sure the Signed Bit isn't set with Negative Zero
|
||||
SSE_XORPS_XMM_to_XMM(regT2, regT2); // Clear regT2
|
||||
SSE_CMPEQPS_XMM_to_XMM(regT2, regT1); // Set all F's if each vector is zero
|
||||
SSE_MOVMSKPS_XMM_to_R32(gprT3, regT2); // Used for Zero Flag Calculation
|
||||
SSE_MOVMSKPS_XMM_to_R32(gprT2, regT2); // Used for Zero Flag Calculation
|
||||
SSE_ANDNPS_XMM_to_XMM(regT2, regT1);
|
||||
|
||||
SSE_MOVMSKPS_XMM_to_R32(gprT2, regT2); // Move the sign bits of the t1reg
|
||||
SSE_MOVMSKPS_XMM_to_R32(mReg, regT2); // Move the sign bits of the t1reg
|
||||
|
||||
AND16ItoR(gprT2, AND_XYZW ); // Grab "Is Signed" bits from the previous calculation
|
||||
AND16ItoR(mReg, AND_XYZW ); // Grab "Is Signed" bits from the previous calculation
|
||||
pjmp = JZ8(0); // Skip if none are
|
||||
if (doMac) SHL16ItoR(gprT2, 4);
|
||||
if (doStatus) OR16ItoR(gprT1, 0x82); // SS, S flags
|
||||
if (doMac) SHL16ItoR(mReg, 4);
|
||||
if (doStatus) OR16ItoR(sReg, 0x82); // SS, S flags
|
||||
if (_XYZW_SS) pjmp2 = JMP8(0); // If negative and not Zero, we can skip the Zero Flag checking
|
||||
x86SetJ8(pjmp);
|
||||
|
||||
//-------------------------Check for Zero flags------------------------------
|
||||
|
||||
AND16ItoR(gprT3, AND_XYZW ); // Grab "Is Zero" bits from the previous calculation
|
||||
AND16ItoR(gprT2, AND_XYZW ); // Grab "Is Zero" bits from the previous calculation
|
||||
pjmp = JZ8(0); // Skip if none are
|
||||
if (doMac) OR32RtoR(gprT2, gprT3);
|
||||
if (doStatus) OR16ItoR(gprT1, 0x41); // ZS, Z flags
|
||||
if (doMac) OR32RtoR(mReg, gprT2);
|
||||
if (doStatus) OR16ItoR(sReg, 0x41); // ZS, Z flags
|
||||
x86SetJ8(pjmp);
|
||||
|
||||
//-------------------------Finally: Send the Flags to the Mac Flag Address------------------------------
|
||||
|
||||
if (_XYZW_SS) x86SetJ8(pjmp2); // If we skipped the Zero Flag Checking, return here
|
||||
|
||||
if (doMac) SSE_PINSRW_R32_to_XMM(xmmF, gprT2, fmInstance); // Set Mac Flag
|
||||
if (doStatus) SSE_PINSRW_R32_to_XMM(xmmF, gprT1, fsInstance); // Set Status Flag
|
||||
if (doMac) mVUallocMFLAGb<vuIndex>(mReg, fmInstance); // Set Mac Flag
|
||||
}
|
||||
|
||||
//------------------------------------------------------------------
|
||||
|
|
@ -104,6 +105,34 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw) {
|
|||
} \
|
||||
}
|
||||
|
||||
#define mVU_FMAC4(operation) { \
|
||||
microVU* mVU = mVUx; \
|
||||
if (recPass == 0) {} \
|
||||
else { \
|
||||
int ACC, Fs, Ft; \
|
||||
if (isNOP) return; \
|
||||
mVUallocFMAC4a<vuIndex>(ACC, Fs, Ft); \
|
||||
if (_XYZW_SS && _X) SSE_##operation##SS_XMM_to_XMM(Fs, Ft); \
|
||||
else SSE_##operation##PS_XMM_to_XMM(Fs, Ft); \
|
||||
mVUupdateFlags<vuIndex>(Fs, xmmT1, Ft, _X_Y_Z_W); \
|
||||
mVUallocFMAC4b<vuIndex>(ACC, Fs); \
|
||||
} \
|
||||
}
|
||||
|
||||
#define mVU_FMAC5(operation) { \
|
||||
microVU* mVU = mVUx; \
|
||||
if (recPass == 0) {} \
|
||||
else { \
|
||||
int ACC, Fs, Ft; \
|
||||
if (isNOP) return; \
|
||||
mVUallocFMAC5a<vuIndex>(ACC, Fs, Ft); \
|
||||
if (_XYZW_SS && _X) SSE_##operation##SS_XMM_to_XMM(Fs, Ft); \
|
||||
else SSE_##operation##PS_XMM_to_XMM(Fs, Ft); \
|
||||
mVUupdateFlags<vuIndex>(Fs, xmmT1, Ft, _X_Y_Z_W); \
|
||||
mVUallocFMAC5b<vuIndex>(ACC, Fs); \
|
||||
} \
|
||||
}
|
||||
|
||||
//------------------------------------------------------------------
|
||||
// Micro VU Micromode Upper instructions
|
||||
//------------------------------------------------------------------
|
||||
|
|
@ -122,48 +151,45 @@ microVUf(void) mVU_ABS() {
|
|||
microVUf(void) mVU_ADD() { mVU_FMAC1(ADD); }
|
||||
microVUf(void) mVU_ADDi(){}
|
||||
microVUf(void) mVU_ADDq(){}
|
||||
microVUq(void) mVU_ADDxyzw() { mVU_FMAC3(ADD); }
|
||||
microVUf(void) mVU_ADDx() { mVU_ADDxyzw<vuIndex, recPass>(); }
|
||||
microVUf(void) mVU_ADDy() { mVU_ADDxyzw<vuIndex, recPass>(); }
|
||||
microVUf(void) mVU_ADDz() { mVU_ADDxyzw<vuIndex, recPass>(); }
|
||||
microVUf(void) mVU_ADDw() { mVU_ADDxyzw<vuIndex, recPass>(); }
|
||||
microVUf(void) mVU_ADDA(){}
|
||||
microVUf(void) mVU_ADDx() { mVU_FMAC3(ADD); }
|
||||
microVUf(void) mVU_ADDy() { mVU_FMAC3(ADD); }
|
||||
microVUf(void) mVU_ADDz() { mVU_FMAC3(ADD); }
|
||||
microVUf(void) mVU_ADDw() { mVU_FMAC3(ADD); }
|
||||
microVUf(void) mVU_ADDA() { mVU_FMAC4(ADD); }
|
||||
microVUf(void) mVU_ADDAi(){}
|
||||
microVUf(void) mVU_ADDAq(){}
|
||||
microVUf(void) mVU_ADDAx(){}
|
||||
microVUf(void) mVU_ADDAy(){}
|
||||
microVUf(void) mVU_ADDAz(){}
|
||||
microVUf(void) mVU_ADDAw(){}
|
||||
microVUf(void) mVU_ADDAx() { mVU_FMAC5(ADD); }
|
||||
microVUf(void) mVU_ADDAy() { mVU_FMAC5(ADD); }
|
||||
microVUf(void) mVU_ADDAz() { mVU_FMAC5(ADD); }
|
||||
microVUf(void) mVU_ADDAw() { mVU_FMAC5(ADD); }
|
||||
microVUf(void) mVU_SUB() { mVU_FMAC1(SUB); }
|
||||
microVUf(void) mVU_SUBi(){}
|
||||
microVUf(void) mVU_SUBq(){}
|
||||
microVUq(void) mVU_SUBxyzw() { mVU_FMAC3(SUB); }
|
||||
microVUf(void) mVU_SUBx() { mVU_SUBxyzw<vuIndex, recPass>(); }
|
||||
microVUf(void) mVU_SUBy() { mVU_SUBxyzw<vuIndex, recPass>(); }
|
||||
microVUf(void) mVU_SUBz() { mVU_SUBxyzw<vuIndex, recPass>(); }
|
||||
microVUf(void) mVU_SUBw() { mVU_SUBxyzw<vuIndex, recPass>(); }
|
||||
microVUf(void) mVU_SUBA(){}
|
||||
microVUf(void) mVU_SUBx() { mVU_FMAC3(SUB); }
|
||||
microVUf(void) mVU_SUBy() { mVU_FMAC3(SUB); }
|
||||
microVUf(void) mVU_SUBz() { mVU_FMAC3(SUB); }
|
||||
microVUf(void) mVU_SUBw() { mVU_FMAC3(SUB); }
|
||||
microVUf(void) mVU_SUBA() { mVU_FMAC4(SUB); }
|
||||
microVUf(void) mVU_SUBAi(){}
|
||||
microVUf(void) mVU_SUBAq(){}
|
||||
microVUf(void) mVU_SUBAx(){}
|
||||
microVUf(void) mVU_SUBAy(){}
|
||||
microVUf(void) mVU_SUBAz(){}
|
||||
microVUf(void) mVU_SUBAw(){}
|
||||
microVUf(void) mVU_SUBAx() { mVU_FMAC5(SUB); }
|
||||
microVUf(void) mVU_SUBAy() { mVU_FMAC5(SUB); }
|
||||
microVUf(void) mVU_SUBAz() { mVU_FMAC5(SUB); }
|
||||
microVUf(void) mVU_SUBAw() { mVU_FMAC5(SUB); }
|
||||
microVUf(void) mVU_MUL() { mVU_FMAC1(MUL); }
|
||||
microVUf(void) mVU_MULi(){}
|
||||
microVUf(void) mVU_MULq(){}
|
||||
microVUq(void) mVU_MULxyzw() { mVU_FMAC3(MUL); }
|
||||
microVUf(void) mVU_MULx() { mVU_MULxyzw<vuIndex, recPass>(); }
|
||||
microVUf(void) mVU_MULy() { mVU_MULxyzw<vuIndex, recPass>(); }
|
||||
microVUf(void) mVU_MULz() { mVU_MULxyzw<vuIndex, recPass>(); }
|
||||
microVUf(void) mVU_MULw() { mVU_MULxyzw<vuIndex, recPass>(); }
|
||||
microVUf(void) mVU_MULA(){}
|
||||
microVUf(void) mVU_MULx() { mVU_FMAC3(MUL); }
|
||||
microVUf(void) mVU_MULy() { mVU_FMAC3(MUL); }
|
||||
microVUf(void) mVU_MULz() { mVU_FMAC3(MUL); }
|
||||
microVUf(void) mVU_MULw() { mVU_FMAC3(MUL); }
|
||||
microVUf(void) mVU_MULA() { mVU_FMAC4(MUL); }
|
||||
microVUf(void) mVU_MULAi(){}
|
||||
microVUf(void) mVU_MULAq(){}
|
||||
microVUf(void) mVU_MULAx(){}
|
||||
microVUf(void) mVU_MULAy(){}
|
||||
microVUf(void) mVU_MULAz(){}
|
||||
microVUf(void) mVU_MULAw(){}
|
||||
microVUf(void) mVU_MULAx() { mVU_FMAC5(MUL); }
|
||||
microVUf(void) mVU_MULAy() { mVU_FMAC5(MUL); }
|
||||
microVUf(void) mVU_MULAz() { mVU_FMAC5(MUL); }
|
||||
microVUf(void) mVU_MULAw() { mVU_FMAC5(MUL); }
|
||||
microVUf(void) mVU_MADD(){}
|
||||
microVUf(void) mVU_MADDi(){}
|
||||
microVUf(void) mVU_MADDq(){}
|
||||
|
|
@ -194,18 +220,16 @@ microVUf(void) mVU_MSUBAz(){}
|
|||
microVUf(void) mVU_MSUBAw(){}
|
||||
microVUf(void) mVU_MAX() { mVU_FMAC1(MAX); }
|
||||
microVUf(void) mVU_MAXi(){}
|
||||
microVUq(void) mVU_MAXxyzw() { mVU_FMAC3(MAX); }
|
||||
microVUf(void) mVU_MAXx() { mVU_MAXxyzw<vuIndex, recPass>(); }
|
||||
microVUf(void) mVU_MAXy() { mVU_MAXxyzw<vuIndex, recPass>(); }
|
||||
microVUf(void) mVU_MAXz() { mVU_MAXxyzw<vuIndex, recPass>(); }
|
||||
microVUf(void) mVU_MAXw() { mVU_MAXxyzw<vuIndex, recPass>(); }
|
||||
microVUf(void) mVU_MAXx() { mVU_FMAC3(MAX); }
|
||||
microVUf(void) mVU_MAXy() { mVU_FMAC3(MAX); }
|
||||
microVUf(void) mVU_MAXz() { mVU_FMAC3(MAX); }
|
||||
microVUf(void) mVU_MAXw() { mVU_FMAC3(MAX); }
|
||||
microVUf(void) mVU_MINI() { mVU_FMAC1(MIN); }
|
||||
microVUf(void) mVU_MINIi(){}
|
||||
microVUq(void) mVU_MINIxyzw(){ mVU_FMAC3(MIN); }
|
||||
microVUf(void) mVU_MINIx() { mVU_MINIxyzw<vuIndex, recPass>(); }
|
||||
microVUf(void) mVU_MINIy() { mVU_MINIxyzw<vuIndex, recPass>(); }
|
||||
microVUf(void) mVU_MINIz() { mVU_MINIxyzw<vuIndex, recPass>(); }
|
||||
microVUf(void) mVU_MINIw() { mVU_MINIxyzw<vuIndex, recPass>(); }
|
||||
microVUf(void) mVU_MINIx() { mVU_FMAC3(MIN); }
|
||||
microVUf(void) mVU_MINIy() { mVU_FMAC3(MIN); }
|
||||
microVUf(void) mVU_MINIz() { mVU_FMAC3(MIN); }
|
||||
microVUf(void) mVU_MINIw() { mVU_FMAC3(MIN); }
|
||||
microVUf(void) mVU_OPMULA(){}
|
||||
microVUf(void) mVU_OPMSUB(){}
|
||||
microVUf(void) mVU_NOP(){}
|
||||
|
|
|
|||
Loading…
Reference in New Issue