From 4ea331ecf24c6b6b97db766253139e3af5a63acc Mon Sep 17 00:00:00 2001 From: Stenzek Date: Fri, 30 Dec 2022 18:19:40 +1000 Subject: [PATCH] x86/microVU: Fix VU1->VU0 register access in MTVU mode eax wasn't being backed up, and in most cases it contains the address we're loading from/storing to. --- pcsx2/x86/microVU_Execute.inl | 7 ++++--- pcsx2/x86/microVU_Misc.inl | 2 ++ 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/pcsx2/x86/microVU_Execute.inl b/pcsx2/x86/microVU_Execute.inl index 4fcd69eed6..3910dad5ab 100644 --- a/pcsx2/x86/microVU_Execute.inl +++ b/pcsx2/x86/microVU_Execute.inl @@ -135,8 +135,9 @@ void mvuGenerateWaitMTVU(mV) if (!xRegister32::IsCallerSaved(i) || i == rsp.GetId()) continue; - // no need to save temps - if (i == gprT1.GetId() || i == gprT2.GetId()) + // T1 often contains the address we're loading when waiting for VU1. + // T2 isn't used until afterwards, so don't bother saving it. + if (i == gprT2.GetId()) continue; xPUSH(xRegister64(i)); @@ -187,7 +188,7 @@ void mvuGenerateWaitMTVU(mV) if (!xRegister32::IsCallerSaved(i) || i == rsp.GetId()) continue; - if (i == gprT1.GetId() || i == gprT2.GetId()) + if (i == gprT2.GetId()) continue; xPOP(xRegister64(i)); diff --git a/pcsx2/x86/microVU_Misc.inl b/pcsx2/x86/microVU_Misc.inl index 9bb2a6e4ab..0ec8ac4bcc 100644 --- a/pcsx2/x86/microVU_Misc.inl +++ b/pcsx2/x86/microVU_Misc.inl @@ -326,7 +326,9 @@ __fi void mVUaddrFix(mV, const xAddressReg& gprReg) { xMOV(gprT1, mVU.prog.cur->idx); // Note: Kernel does it via COP2 to initialize VU1! xMOV(gprT2, xPC); // So we don't spam console, we'll only check micro-mode... + mVUbackupRegs(mVU, true, false); xFastCall((void*)mVUwarningRegAccess, arg1regd, arg2regd); + mVUrestoreRegs(mVU, true, false); } #endif xFastCall((void*)mVU.waitMTVU);