mirror of https://github.com/PCSX2/pcsx2.git
fixed some counters problems, should be more smooth and stable.
one of the problems i'm having is that rcntUpdate() should be called more-often, but i don't know where i should put it... git-svn-id: http://pcsx2-playground.googlecode.com/svn/trunk@238 a6443dda-0b58-4228-96e9-037be469359c
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@ -139,12 +139,12 @@ u64 GetCPUTicks()
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void UpdateVSyncRate() {
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counters[4].count = 0;
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counters[4].mode = MODE_HRENDER; // Counter 4 takes care of hBlanks
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counters[4].sCycle = cpuRegs.cycle; // Update Counter 4's Start Cycle
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counters[4].count = 0; // Set number of scanlines/hblanks to zero
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counters[4].mode = MODE_HRENDER; // Counter 4 takes care of scanlines, so set the mode to HRENDER (drawing part of scanline)
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counters[4].sCycle = cpuRegs.cycle; // Update Counter 4's Start Cycle to match CPU's cycle
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counters[5].mode = MODE_VRENDER; // Counter 5 takes care of vSync/vBlanks
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counters[5].rate = MODE_VBLANK1;
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counters[5].rate = MODE_VBLANK1; // Rate is just used to alternate between vBlank1 and vBlank2 modes (because of interlacing, one half-frame can have a different number of vBlank scanlines)
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if (Config.CustomFps > 0) {
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iTicks = GetTickFrequency() / Config.CustomFps;
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@ -381,16 +381,28 @@ __forceinline void VBlankEnd()
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SysUpdate(); // check for and handle keyevents
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}
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#define hScanlineOptimization(diff, compareValue, incrementCounters) { \
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if (diff >= compareValue) { \
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u32 increment = (diff / compareValue); \
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SysPrintf("Counters Optimization\n"); \
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counters[4].count += increment; \
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if (incrementCounters) { \
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/*Update counters using the hblank as the clock*/ \
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if ((counters[0].mode & 0x83) == 0x83) counters[0].count += (increment * HBLANK_COUNTER_SPEED); \
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if ((counters[1].mode & 0x83) == 0x83) counters[1].count += (increment * HBLANK_COUNTER_SPEED); \
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if ((counters[2].mode & 0x83) == 0x83) counters[2].count += (increment * HBLANK_COUNTER_SPEED); \
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if ((counters[3].mode & 0x83) == 0x83) counters[3].count += (increment * HBLANK_COUNTER_SPEED); \
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} \
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} \
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}
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int hScanline()
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{
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u32 difference = (cpuRegs.cycle - counters[4].sCycle);
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if (counters[4].mode & MODE_HBLANK) { //HBLANK Start
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if (difference >= HBLANK_TIME_ ) {
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if (difference >= (SCANLINE_ + HBLANK_TIME_)) {
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//SysPrintf("Counters Optimization 1\n");
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counters[4].count += (cpuRegs.cycle - counters[4].sCycle) / (SCANLINE_ + HBLANK_TIME_);
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}
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//hScanlineOptimization(difference, (SCANLINE_ + HBLANK_TIME_), 1);
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rcntStartGate(0);
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psxCheckStartGate(0);
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counters[4].sCycle = cpuRegs.cycle;
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@ -399,10 +411,7 @@ int hScanline()
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}
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else { //HBLANK END / HRENDER Begin
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if (difference >= (HRENDER_TIME_)) {
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if (difference >= (SCANLINE_ + HRENDER_TIME_)) {
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//SysPrintf("Counters Optimization 2\n");
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counters[4].count += (cpuRegs.cycle - counters[4].sCycle) / (SCANLINE_ + HRENDER_TIME_);
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}
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//hScanlineOptimization(difference, (SCANLINE_ + HRENDER_TIME_), 0);
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if (CSRw & 0x4) GSCSRr |= 4; // signal
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if (!(GSIMR&0x400)) gsIrq();
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if (gates) rcntEndGate(0);
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@ -411,10 +420,10 @@ int hScanline()
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counters[4].sCycle = cpuRegs.cycle;
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counters[4].mode ^= MODE_HBLANK;
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return 0;
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return 0; // Count Incremented
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}
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}
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return 1;
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return 1; // Count not Incremented
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}
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void vSync()
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@ -559,7 +568,7 @@ void rcntWmode(int index, u32 value)
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case 0: counters[index].rate = 2; break;
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case 1: counters[index].rate = 32; break;
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case 2: counters[index].rate = 512; break;
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case 3: counters[index].rate = PS2HBLANK; break;
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case 3: counters[index].rate = SCANLINE_; break;
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}
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if((counters[index].mode & 0xF) == 0x7) {
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@ -587,19 +596,14 @@ void rcntStartGate(unsigned int mode) {
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for (i=0; i <=3; i++) { //Gates for counters
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if ((mode == 0) && ((counters[i].mode & 0x83) == 0x83)) counters[i].count++; //Update counters using the hblank as the clock
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if ((mode == 0) && ((counters[i].mode & 0x83) == 0x83)) counters[i].count += HBLANK_COUNTER_SPEED; //Update counters using the hblank as the clock
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if (!(gates & (1<<i))) continue;
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if ((counters[i].mode & 0x8) != mode) continue;
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//SysPrintf("Gate %d mode %d Start\n", i, (counters[i].mode & 0x30) >> 4);
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switch (counters[i].mode & 0x30) {
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case 0x00: //Count When Signal is low (off)
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counters[i].count = rcntRcount(i);
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rcntUpd(i);
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counters[i].mode &= ~0x80;
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break;
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case 0x20: //Reset and start counting on Vsync end
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//Do Nothing
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counters[i].mode |= 0x80;
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break;
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case 0x10: //Reset and start counting on Vsync start
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case 0x30: //Reset and start counting on Vsync start and end
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@ -607,7 +611,6 @@ void rcntStartGate(unsigned int mode) {
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rcntReset(i);
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counters[i].target &= 0xffff;
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break;
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}
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}
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}
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@ -618,14 +621,12 @@ void rcntEndGate(unsigned int mode) {
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for(i=0; i <=3; i++) { //Gates for counters
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if (!(gates & (1<<i))) continue;
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if ((counters[i].mode & 0x8) != mode) continue;
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//SysPrintf("Gate %d mode %d End\n", i, (counters[i].mode & 0x30) >> 4);
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switch (counters[i].mode & 0x30) {
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case 0x00: //Count When Signal is low (off)
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counters[i].count = rcntRcount(i);
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rcntUpd(i);
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counters[i].mode |= 0x80;
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break;
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case 0x10: //Reset and start counting on Vsync start
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//Do Nothing
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counters[i].mode &= ~0x80;
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break;
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case 0x20: //Reset and start counting on Vsync end
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case 0x30: //Reset and start counting on Vsync start and end
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@ -61,7 +61,7 @@ typedef struct {
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#define SCANLINES_VBLANK2_PAL 20 // scanlines used for vblank2 (odd interlace)
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//------------------------------------------------------------------
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// PAL Timing Information!!!
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// Timing (PAL/NTSC) Information!!!
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//------------------------------------------------------------------
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#define SCANLINE_ (u32)((Config.PsxType&1) ? SCANLINE_PAL : SCANLINE_NTSC) * HBLANK_TIMER_SLOWDOWN
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#define HRENDER_TIME_ (u32)((Config.PsxType&1) ? HRENDER_TIME_PAL : HRENDER_TIME_NTSC) * HBLANK_TIMER_SLOWDOWN
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