mirror of https://github.com/PCSX2/pcsx2.git
added Nneeve's (q.w.e.r.t.y) fixed add/sub code. its on by default, theres a macro to turn it off. just set FPU_ADD_SUB_HACK to 0 to use the old way.
and i think i know a way to improve fpu clamping, i'm going to try and code it for my next update. git-svn-id: http://pcsx2-playground.googlecode.com/svn/trunk@429 a6443dda-0b58-4228-96e9-037be469359c
This commit is contained in:
cottonvibes
Gregory Hainaut
parent
d2aabc8c2e
commit
49cf52a0ab
162
pcsx2/x86/iFPU.c
162
pcsx2/x86/iFPU.c
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@ -49,6 +49,8 @@
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#define FPUflagSO 0X00000010
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#define FPUflagSU 0X00000008
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#define FPU_ADD_SUB_HACK 1 // Add/Sub opcodes produce more ps2-like results if set to 1
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extern PCSX2_ALIGNED16_DECL(u32 g_minvals[4]);
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extern PCSX2_ALIGNED16_DECL(u32 g_maxvals[4]);
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@ -518,13 +520,39 @@ REC_FPUFUNC(RSQRT_S);
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//------------------------------------------------------------------
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// Clamp Functions (Converts NaN's and Infinities to Normal Numbers)
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//------------------------------------------------------------------
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void fpuFloat(int regd) {
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void fpuFloat(int regd) { // +/-NaN -> +fMax, +Inf -> +fMax, -Inf -> -fMax
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if (CHECK_FPU_OVERFLOW && !CHECK_FPUCLAMPHACK) { // Tekken 5 doesn't like clamping infinities.
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SSE_MINSS_M32_to_XMM(regd, (uptr)&g_maxvals[0]); // MIN() must be before MAX()! So that NaN's become +Maximum
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SSE_MAXSS_M32_to_XMM(regd, (uptr)&g_minvals[0]);
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}
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}
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PCSX2_ALIGNED16(u64 FPU_FLOAT_TEMP[2]);
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void fpuFloat2(int regd) { // +NaN -> +fMax, -NaN -> -fMax, +Inf -> +fMax, -Inf -> -fMax
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if (CHECK_FPU_OVERFLOW && !CHECK_FPUCLAMPHACK) { // Tekken 5 doesn't like clamping infinities.
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int t1reg = _allocTempXMMreg(XMMT_FPS, -1);
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if (t1reg >= 0) {
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SSE_MOVSS_XMM_to_XMM(t1reg, regd);
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SSE_ANDPS_XMM_to_XMM(t1reg, (uptr)&s_neg[0]);
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SSE_MINSS_M32_to_XMM(regd, (uptr)&g_maxvals[0]);
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SSE_MAXSS_M32_to_XMM(regd, (uptr)&g_minvals[0]);
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SSE_ORPS_XMM_to_XMM(regd, t1reg);
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_freeXMMreg(t1reg);
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}
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else {
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SysPrintf("fpuFloat2() allocation error\n");
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t1reg = (regd == 0) ? 1 : 0; // get a temp reg thats not regd
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SSE_MOVAPS_XMM_to_M128( (uptr)&FPU_FLOAT_TEMP[0], t1reg ); // backup data in t1reg to a temp address
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SSE_MOVSS_XMM_to_XMM(t1reg, regd);
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SSE_ANDPS_XMM_to_XMM(t1reg, (uptr)&s_neg[0]);
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SSE_MINSS_M32_to_XMM(regd, (uptr)&g_maxvals[0]);
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SSE_MAXSS_M32_to_XMM(regd, (uptr)&g_minvals[0]);
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SSE_ORPS_XMM_to_XMM(regd, t1reg);
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SSE_MOVAPS_M128_to_XMM( t1reg, (uptr)&FPU_FLOAT_TEMP[0] ); // restore t1reg data
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}
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}
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}
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void ClampValues(int regd) {
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fpuFloat(regd);
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}
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@ -570,14 +598,138 @@ FPURECOMPILE_CONSTCODE(ABS_S, XMMINFO_WRITED|XMMINFO_READS);
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//------------------------------------------------------------------
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//------------------------------------------------------------------
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// FPU_ADD_SUB (Used to mimic PS2's FPU add/sub behavior)
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//------------------------------------------------------------------
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// Compliant IEEE FPU uses, in computations, uses additional "guard" bits to the right of the mantissa
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// but EE-FPU doesn't. Substraction (and addition of positive and negative) may shift the mantissa left,
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// causing those bits to appear in the result; this function masks out the bits of the mantissa that will
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// get shifted right to the guard bits to ensure that the guard bits are empty.
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// The difference of the exponents = the amount that the smaller operand will be shifted right by.
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// Modification - the PS2 uses a single guard bit? (Coded by Nneeve)
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//------------------------------------------------------------------
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void FPU_ADD_SUB(int regd, int regt, int issub)
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{
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static u32 PCSX2_ALIGNED16(roundmode_temp[4]) = { 0x00000000, 0x00000000, 0x00000000, 0x00000000 };
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int tempecx = _allocX86reg(ECX, X86TYPE_TEMP, 0, 0); //receives regd
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int temp2 = _allocX86reg(-1, X86TYPE_TEMP, 0, 0); //receives regt
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int xmmtemp = _allocTempXMMreg(XMMT_FPS, -1); //temporary for anding with regd/regt
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int roundmodeFlag = 0;
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if (tempecx != ECX) { SysPrintf("FPU: ADD/SUB Allocation Error!\n"); tempecx = ECX;}
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if (temp2 == -1) { SysPrintf("FPU: ADD/SUB Allocation Error!\n"); temp2 = EAX;}
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if (xmmtemp == -1) { SysPrintf("FPU: ADD/SUB Allocation Error!\n"); xmmtemp = XMM0;}
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if ((g_sseMXCSR & 0x00006000) != 0x00006000) { // Set roundmode to chop if it isn't already
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roundmode_temp[0] = (g_sseMXCSR & 0xFFFF9FFF) | 0x00006000; // Set new roundmode
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roundmode_temp[1] = g_sseMXCSR; // Backup old Roundmode
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SSE_LDMXCSR ((uptr)&roundmode_temp[0]); // Recompile Roundmode Change
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roundmodeFlag = 1;
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}
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SSE2_MOVD_XMM_to_R(tempecx, regd);
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SSE2_MOVD_XMM_to_R(temp2, regt);
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//mask the exponents
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SHR32ItoR(tempecx, 23);
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SHR32ItoR(temp2, 23);
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AND32ItoR(tempecx, 0xff);
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AND32ItoR(temp2, 0xff);
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SUB32RtoR(tempecx, temp2); //tempecx = exponent difference
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CMP32ItoR(tempecx, 25);
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j8Ptr[0] = JGE8(0);
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CMP32ItoR(tempecx, 0);
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j8Ptr[1] = JG8(0);
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j8Ptr[2] = JE8(0);
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CMP32ItoR(tempecx, -25);
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j8Ptr[3] = JLE8(0);
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//diff = -24 .. -1 , expd < expt
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NEG32R(tempecx);
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DEC32R(tempecx);
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MOV32ItoR(temp2, 0xffffffff);
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SHL32CLtoR(temp2); //temp2 = 0xffffffff << tempecx
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SSE2_MOVD_R_to_XMM(xmmtemp, temp2);
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SSE_ANDPS_XMM_to_XMM(regd, xmmtemp);
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if (issub)
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SSE_SUBSS_XMM_to_XMM(regd, regt);
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else
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SSE_ADDSS_XMM_to_XMM(regd, regt);
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j8Ptr[4] = JMP8(0);
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x86SetJ8(j8Ptr[0]);
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//diff = 25 .. 255 , expt < expd
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SSE_MOVAPS_XMM_to_XMM(xmmtemp, regt);
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SSE_ANDPS_M128_to_XMM(xmmtemp, (uptr)s_neg);
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if (issub)
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SSE_SUBSS_XMM_to_XMM(regd, xmmtemp);
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else
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SSE_ADDSS_XMM_to_XMM(regd, xmmtemp);
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j8Ptr[5] = JMP8(0);
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x86SetJ8(j8Ptr[1]);
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//diff = 1 .. 24, expt < expd
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DEC32R(tempecx);
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MOV32ItoR(temp2, 0xffffffff);
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SHL32CLtoR(temp2); //temp2 = 0xffffffff << tempecx
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SSE2_MOVD_R_to_XMM(xmmtemp, temp2);
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SSE_ANDPS_XMM_to_XMM(xmmtemp, regt);
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if (issub)
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SSE_SUBSS_XMM_to_XMM(regd, xmmtemp);
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else
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SSE_ADDSS_XMM_to_XMM(regd, xmmtemp);
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j8Ptr[6] = JMP8(0);
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x86SetJ8(j8Ptr[3]);
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//diff = -255 .. -25, expd < expt
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SSE_ANDPS_M128_to_XMM(regd, (uptr)s_neg);
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if (issub)
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SSE_SUBSS_XMM_to_XMM(regd, regt);
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else
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SSE_ADDSS_XMM_to_XMM(regd, regt);
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j8Ptr[7] = JMP8(0);
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x86SetJ8(j8Ptr[2]);
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//diff == 0
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if (issub)
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SSE_SUBSS_XMM_to_XMM(regd, regt);
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else
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SSE_ADDSS_XMM_to_XMM(regd, regt);
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x86SetJ8(j8Ptr[4]);
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x86SetJ8(j8Ptr[5]);
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x86SetJ8(j8Ptr[6]);
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x86SetJ8(j8Ptr[7]);
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if (roundmodeFlag == 1) { // Set roundmode back if it was changed
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SSE_LDMXCSR ((uptr)&roundmode_temp[1]);
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}
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_freeXMMreg(xmmtemp);
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_freeX86reg(temp2);
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_freeX86reg(tempecx);
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}
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void FPU_ADD(int regd, int regt) {
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if (FPU_ADD_SUB_HACK) FPU_ADD_SUB(regd, regt, 0);
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else SSE_ADDSS_XMM_to_XMM(regd, regt);
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}
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void FPU_SUB(int regd, int regt) {
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if (FPU_ADD_SUB_HACK) FPU_ADD_SUB(regd, regt, 1);
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else SSE_SUBSS_XMM_to_XMM(regd, regt);
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}
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//------------------------------------------------------------------
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// CommutativeOp XMM (used for ADD, MUL, MAX, and MIN opcodes)
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//------------------------------------------------------------------
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static void (*recComOpXMM_to_XMM[] )(x86SSERegType, x86SSERegType) = {
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SSE_ADDSS_XMM_to_XMM, SSE_MULSS_XMM_to_XMM, SSE_MAXSS_XMM_to_XMM, SSE_MINSS_XMM_to_XMM };
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FPU_ADD, SSE_MULSS_XMM_to_XMM, SSE_MAXSS_XMM_to_XMM, SSE_MINSS_XMM_to_XMM };
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static void (*recComOpM32_to_XMM[] )(x86SSERegType, uptr) = {
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SSE_ADDSS_M32_to_XMM, SSE_MULSS_M32_to_XMM, SSE_MAXSS_M32_to_XMM, SSE_MINSS_M32_to_XMM };
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//static void (*recComOpM32_to_XMM[] )(x86SSERegType, uptr) = {
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// SSE_ADDSS_M32_to_XMM, SSE_MULSS_M32_to_XMM, SSE_MAXSS_M32_to_XMM, SSE_MINSS_M32_to_XMM };
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int recCommutativeOp(int info, int regd, int op)
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{
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@ -1552,7 +1704,7 @@ FPURECOMPILE_CONSTCODE(NEG_S, XMMINFO_WRITED|XMMINFO_READS);
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void recSUBhelper(int regd, int regt)
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{
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if (CHECK_FPU_EXTRA_OVERFLOW /*&& !CHECK_FPUCLAMPHACK*/) { fpuFloat(regd); fpuFloat(regt); }
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SSE_SUBSS_XMM_to_XMM(regd, regt);
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FPU_SUB(regd, regt);
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}
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void recSUBop(int info, int regd)
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