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Fix for Tekken Tag Issue 259 

Removed the doubled up timings on SIF DMA cycles (should have been done when it was spotted really)
Put in a fix for Scratchpad reads which cause a VTLB error.

git-svn-id: http://pcsx2.googlecode.com/svn/trunk@1323 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
refraction 2009-06-04 17:50:56 +00:00
parent e9ad2ffe7b
commit 480519efad
4 changed files with 31 additions and 13 deletions
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33
pcsx2/Gif.cpp
View File

@ -250,7 +250,7 @@ void GIFdma()
if (((gif->qwc == 0) && (gif->chcr & 0xc) == 0))
gspath3done = 1;
else if(gif->qwc > 0)
else if(gif->qwc > 0 || gscycles)
{
GIFdmaEnd();
return;
@ -328,19 +328,20 @@ void dmaGIF() {
//We used to addd wait time for the buffer to fill here, fixing some timing problems in path 3 masking
//It takes the time of 24 QW for the BUS to become ready - The Punisher, And1 Streetball
GIF_LOG("dmaGIFstart chcr = %lx, madr = %lx, qwc = %lx\n tadr = %lx, asr0 = %lx, asr1 = %lx", gif->chcr, gif->madr, gif->qwc, gif->tadr, gif->asr0, gif->asr1);
if ((psHu32(DMAC_CTRL) & 0xC) == 0xC ) { // GIF MFIFO
//Console::WriteLn("GIF MFIFO");
gifMFIFOInterrupt();
return;
}
Path3progress = 2;
gspath3done = 0; // For some reason this doesnt clear? So when the system starts the thread, we will clear it :)
psHu32(GIF_STAT) |= GIF_STAT_P3Q;
GSCSRr &= ~0xC000; //Clear FIFO stuff
GSCSRr |= 0x8000; //FIFO full
psHu32(GIF_STAT)|= 0x10000000; // FQC=31, hack ;) [used to be 0xE00; // OPH=1 | APATH=3]
Path3progress = 2;
if ((psHu32(DMAC_CTRL) & 0xC) == 0xC ) { // GIF MFIFO
//Console::WriteLn("GIF MFIFO");
gifMFIFOInterrupt();
return;
}
if ((gif->qwc == 0) && ((gif->chcr & 0xc) != 0)){
u32 *ptag;
@ -536,11 +537,22 @@ void mfifoGIFtransfer(int qwc) {
void gifMFIFOInterrupt()
{
mfifocycles = 0;
if(Path3progress == 2) psHu32(GIF_STAT)&= ~(GIF_STAT_APATH3 | GIF_STAT_OPH); // OPH=0 | APATH=0
if (!(gif->chcr & 0x100)) {
Console::WriteLn("WTF GIFMFIFO");
cpuRegs.interrupt &= ~(1 << 11);
return ;
}
if(((psHu32(GIF_STAT) & 0x100) || (vif1.cmd & 0x7f) == 0x50) && (psHu32(GIF_MODE) & 0x4) && Path3progress == 0) //Path2 gets priority in intermittent mode
{
//GIF_LOG("Waiting VU %x, PATH2 %x, GIFMODE %x Progress %x", psHu32(GIF_STAT) & 0x100, (vif1.cmd & 0x7f), psHu32(GIF_MODE), Path3progress);
CPU_INT(11,mfifocycles);
return;
}
if((spr0->chcr & 0x100) && spr0->qwc == 0)
{
spr0->chcr &= ~0x100;
@ -566,6 +578,11 @@ void gifMFIFOInterrupt()
#endif
//if(gifqwc > 0) Console::WriteLn("GIF MFIFO ending with stuff in it %x", params gifqwc);
if (!gifmfifoirq) gifqwc = 0;
gspath3done = 0;
gscycles = 0;
psHu32(GIF_STAT)&= ~(GIF_STAT_APATH3 | GIF_STAT_OPH); // OPH=0 | APATH=0
psHu32(GIF_STAT) &= ~GIF_STAT_P3Q;
gifstate = GIF_STATE_READY;
gif->chcr &= ~0x100;
vif1Regs->stat &= ~VIF1_STAT_VGW;

4
pcsx2/Hw.h
View File

@ -434,8 +434,8 @@ static __forceinline void *dmaGetAddr(u32 addr) {
// if (addr & 0xf) { DMA_LOG("*PCSX2*: DMA address not 128bit aligned: %8.8x", addr); }
// teh sux why the f00k 0xE0000000
if (addr & 0x80000000) return (void*)&psS[addr & 0x3ff0];
// Need to check the physical address as well as just the "SPR" flag, as VTLB doesnt seem to handle it
if ((addr & 0x80000000) || (addr & 0x70000000) == 0x70000000) return (void*)&psS[addr & 0x3ff0];
ptr = (u8*)vtlb_GetPhyPtr(addr&0x1FFFFFF0);
if (ptr == NULL) {

3
pcsx2/IopCounters.cpp
View File

@ -576,7 +576,7 @@ __forceinline void psxRcntWmode16( int index, u32 value )
{
// gated counters are added up as per the h/vblank timers.
// (the PIXEL alt source becomes a vsync gate)
counter.mode |= IOPCNT_STOPPED;
PSXCNT_LOG( "IOP Counter[%d] Gate Check set, value = 0x%04X", index, value );
if( index == 0 )
psxhblankgate |= 1; // fixme: these gate flags should be one var >_<
@ -621,6 +621,7 @@ __forceinline void psxRcntWmode32( int index, u32 value )
if(counter.mode & IOPCNT_ENABLE_GATE)
{
PSXCNT_LOG("IOP Counter[3] Gate Check set, value = %x", value);
counter.mode |= IOPCNT_STOPPED;
psxvblankgate |= 1<<3;
}
else psxvblankgate &= ~(1<<3);

4
pcsx2/Sif.cpp
View File

@ -212,7 +212,7 @@ __forceinline void SIF0Dma()
// Clearing handled by vtlb memory protection and manual blocks.
//Cpu->Clear(sif0dma->madr, readSize*4);
cycles += readSize * BIAS; // fixme : BIAS is factored in below
cycles += readSize; // fixme : BIAS is factored in below
sif0dma->qwc -= readSize;
sif0dma->madr += readSize << 4;
}
@ -364,7 +364,7 @@ __forceinline void SIF1Dma()
SIF1write(data, qwTransfer << 2);
sif1dma->madr += qwTransfer << 4;
cycles += qwTransfer * BIAS; // fixme : BIAS is factored in above
cycles += qwTransfer; // fixme : BIAS is factored in above
sif1dma->qwc -= qwTransfer;
}
}