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Moved Coissued Load/Store instructions into iR5900CoissuedLoadStore.cpp, and disabled them via the #define PCSX2_VM_COISSUES (coissues are a very minor speedup and could have led to other emulation compatibility problems, and required in enormous amount of complicated code to implement) 

Moved VM specific code in Memory.cpp into MemoryVM.cpp.

git-svn-id: http://pcsx2-playground.googlecode.com/svn/trunk@641 a6443dda-0b58-4228-96e9-037be469359c
This commit is contained in:
Jake.Stine 2009-01-26 19:09:23 +00:00 committed by Gregory Hainaut
parent 74a305bd0a
commit 4781be9e59
16 changed files with 3993 additions and 3953 deletions
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2
pcsx2/Hw.h
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@ -401,4 +401,6 @@ void iMemRead32Check();
extern void intcInterrupt();
extern void dmacInterrupt();
extern int rdram_devices, rdram_sdevid;
#endif /* __HW_H__ */

2174
pcsx2/Memory.cpp
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File diff suppressed because it is too large Load Diff

2
pcsx2/Memory.h
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@ -306,4 +306,6 @@ void __fastcall _memWrite128(u32 mem, u64 *value);
#define recMemConstWrite128 0&&
#endif
extern void loadBiosRom( const char *ext, u8 *dest, long maxSize );
extern u16 ba0R16(u32 mem);
#endif

2140
pcsx2/MemoryVM.cpp Normal file
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File diff suppressed because it is too large Load Diff

1
pcsx2/R5900OpcodeTables.h
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@ -39,6 +39,7 @@ namespace R5900
namespace Dynarec {
namespace OpcodeImpl
{
void recNULL();
void recUnknown();
void recMMI_Unknown();
void recCOP0_Unknown();

32
pcsx2/windows/VCprojects/pcsx2_2008.vcproj
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@ -1202,30 +1202,6 @@
<File
RelativePath="..\..\x86\ix86\ix86_cpudetect.cpp"
>
<FileConfiguration
Name="Devel vm|Win32"
>
<Tool
Name="VCCLCompilerTool"
UsePrecompiledHeader="2"
/>
</FileConfiguration>
<FileConfiguration
Name="Debug vm|Win32"
>
<Tool
Name="VCCLCompilerTool"
UsePrecompiledHeader="2"
/>
</FileConfiguration>
<FileConfiguration
Name="Debug vtlb|Win32"
>
<Tool
Name="VCCLCompilerTool"
UsePrecompiledHeader="2"
/>
</FileConfiguration>
</File>
<File
RelativePath="..\..\x86\ix86\ix86_fpu.cpp"
@ -2395,6 +2371,10 @@
RelativePath="..\..\x86\iR5900Branch.h"
>
</File>
<File
RelativePath="..\..\x86\iR5900CoissuedLoadStore.cpp"
>
</File>
<File
RelativePath="..\..\x86\iR5900Jump.h"
>
@ -2712,6 +2692,10 @@
RelativePath="..\..\Memory.h"
>
</File>
<File
RelativePath="..\..\MemoryVM.cpp"
>
</File>
<File
RelativePath="..\..\vtlb.cpp"
>

2
pcsx2/x86/iCore.h
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@ -232,8 +232,10 @@ int _signExtendXMMtoM(u32 to, x86SSERegType from, int candestroy); // returns tr
#define EEINSTINFO_COP1 1
#define EEINSTINFO_COP2 2
#ifdef PCSX2_VM_COISSUE
#define EEINSTINFO_NOREC 4 // if set, inst is recompiled alone
#define EEINSTINFO_COREC 8 // if set, inst is recompiled with another similar inst
#endif
#define EEINSTINFO_MMX EEINST_MMX
#define EEINSTINFO_XMM EEINST_XMM

5
pcsx2/x86/iHw.cpp
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@ -279,7 +279,10 @@ int hwConstRead32(u32 x86reg, u32 mem)
{
//IPU regs
if ((mem>=0x10002000) && (mem<0x10003000)) {
return ipuConstRead32(x86reg, mem);
//return ipuConstRead32(x86reg, mem);
iFlushCall(0);
PUSH32I( mem );
CALLFunc( (uptr)ipuRead32 );
}
switch (mem) {

3
pcsx2/x86/iPsxMem.cpp
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@ -18,11 +18,12 @@
#include "PrecompiledHeader.h"
#include "PsxCommon.h"
#include "iR3000A.h"
#include "VU.h"
extern int g_psxWriteOk;
extern int g_psxWriteOk;
extern u32 g_psxMaxRecMem;
static u32 writectrl;

44
pcsx2/x86/iR3000A.cpp
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@ -1195,16 +1195,13 @@ void psxRecompileNextInstruction(int delayslot)
g_pCurInstInfo++;
// peephole optimizations
if( g_pCurInstInfo->info & EEINSTINFO_COREC ) {
assert(0);
}
else {
assert( !(g_pCurInstInfo->info & EEINSTINFO_NOREC) );
g_iopCyclePenalty = 0;
rpsxBSC[ psxRegs.code >> 26 ]();
s_psxBlockCycles += g_iopCyclePenalty;
}
#ifdef PCSX2_VM_COISSUE
assert( g_pCurInstInfo->info & EEINSTINFO_COREC );
#endif
g_iopCyclePenalty = 0;
rpsxBSC[ psxRegs.code >> 26 ]();
s_psxBlockCycles += g_iopCyclePenalty;
if( !delayslot ) {
if( s_bFlushReg ) {
@ -1453,33 +1450,6 @@ StartRecomp:
}
}
// peephole optimizations //
// {
// g_pCurInstInfo = s_pInstCache;
//
// for(i = startpc; i < s_nEndBlock-4; i += 4) {
// g_pCurInstInfo++;
// if( psxRecompileCodeSafe(i) ) {
// u32 curcode = *(u32*)PSXM(i);
// u32 nextcode = *(u32*)PSXM(i+4);
// if( _psxIsLoadStore(curcode) && _psxIsLoadStore(nextcode) && (curcode>>26) == (nextcode>>26) && rpsxBSC_co[curcode>>26] != NULL ) {
//
// // rs has to be the same, and cannot be just written
// if( ((curcode >> 21) & 0x1F) == ((nextcode >> 21) & 0x1F) && !_psxLoadWritesRs(curcode) ) {
//
// // good enough
// g_pCurInstInfo[0].info |= EEINSTINFO_COREC;
// g_pCurInstInfo[0].numpeeps = 1;
// g_pCurInstInfo[1].info |= EEINSTINFO_NOREC;
// g_pCurInstInfo++;
// i += 4;
// continue;
// }
// }
// }
// }
// }
#ifdef _DEBUG
// dump code
for(i = 0; i < ARRAYSIZE(s_psxrecblocks); ++i) {

2
pcsx2/x86/iR3000Atables.cpp
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@ -19,7 +19,7 @@
#include "PrecompiledHeader.h"
#include <time.h>
#include "Misc.h"
#include "PsxCommon.h"
#include "ix86/ix86.h"
#include "iR3000A.h"
#include "IopMem.h"

1739
pcsx2/x86/iR5900CoissuedLoadStore.cpp Normal file
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File diff suppressed because it is too large Load Diff

4
pcsx2/x86/iR5900LoadStore.h
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@ -53,8 +53,8 @@ namespace OpcodeImpl {
void recLQC2( void );
void recSQC2( void );
// coissues
#ifdef PCSX2_VIRTUAL_MEM
// coissues
#ifdef PCSX2_VM_COISSUE
void recLB_co( void );
void recLBU_co( void );
void recLH_co( void );

15
pcsx2/x86/ir5900tables.cpp
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@ -68,7 +68,7 @@ void recCall( void (*func)(), int delreg )
using namespace R5900::Dynarec::OpcodeImpl;
#ifdef PCSX2_VIRTUAL_MEM
#ifdef PCSX2_VM_COISSUE
// coissued insts
void (*recBSC_co[64] )() = {
recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, recNULL,
@ -83,19 +83,6 @@ void (*recBSC_co[64] )() = {
#endif
/*
////////////////////////////////////////////////////
static void recCOP0BC0( void )
{
recCP0BC0[ ( cpuRegs.code >> 16 ) & 0x03 ]( );
}
////////////////////////////////////////////////////
static void recCOP0C0( void )
{
recCP0C0[ _Funct_ ]( );
}*/
////////////////////////////////////////////////
// Back-Prob Function Tables - Gathering Info //
////////////////////////////////////////////////

25
pcsx2/x86/ix86-32/iR5900-32.cpp
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@ -1434,17 +1434,17 @@ void recompileNextInstruction(int delayslot)
const OPCODE& opcode = GetCurrentInstruction();
// peephole optimizations
#ifdef PCSX2_VM_COISSUE
if( g_pCurInstInfo->info & EEINSTINFO_COREC ) {
#ifdef PCSX2_VIRTUAL_MEM
if( g_pCurInstInfo->numpeeps > 1 ) {
switch(_Opcode_) {
case 30: OpcodeImpl::recLQ_coX(g_pCurInstInfo->numpeeps); break;
case 31: OpcodeImpl::recSQ_coX(g_pCurInstInfo->numpeeps); break;
case 49: OpcodeImpl::recLWC1_coX(g_pCurInstInfo->numpeeps); break;
case 57: OpcodeImpl::recSWC1_coX(g_pCurInstInfo->numpeeps); break;
case 55: OpcodeImpl::recLD_coX(g_pCurInstInfo->numpeeps); break;
case 63: OpcodeImpl::recSD_coX(g_pCurInstInfo->numpeeps, 1); break; //not sure if should be set to 1 or 0; looks like "1" handles alignment, so i'm going with that for now
case 30: recLQ_coX(g_pCurInstInfo->numpeeps); break;
case 31: recSQ_coX(g_pCurInstInfo->numpeeps); break;
case 49: recLWC1_coX(g_pCurInstInfo->numpeeps); break;
case 57: recSWC1_coX(g_pCurInstInfo->numpeeps); break;
case 55: recLD_coX(g_pCurInstInfo->numpeeps); break;
case 63: recSD_coX(g_pCurInstInfo->numpeeps, 1); break; //not sure if should be set to 1 or 0; looks like "1" handles alignment, so i'm going with that for now
jNO_DEFAULT
}
@ -1458,12 +1458,11 @@ void recompileNextInstruction(int delayslot)
g_pCurInstInfo++;
s_nBlockCycles += opcode.cycles*2;
}
#else
assert(0);
#endif
}
else {
assert( !(g_pCurInstInfo->info & EEINSTINFO_NOREC) );
else
#endif
{
//assert( !(g_pCurInstInfo->info & EEINSTINFO_NOREC) );
// if this instruction is a jump or a branch, exit right away
if( delayslot ) {
@ -1804,7 +1803,7 @@ StartRecomp:
if( usecop2 ) vucycle++;
// peephole optimizations //
#ifdef PCSX2_VIRTUAL_MEM
#ifdef PCSX2_VM_COISSUE
if( i < s_nEndBlock-4 && recompileCodeSafe(i) ) {
u32 curcode = cpuRegs.code;
u32 nextcode = *(u32*)PSM(i+4);

1756
pcsx2/x86/ix86-32/iR5900LoadStore.cpp
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File diff suppressed because it is too large Load Diff