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Reduce compiler warnings to a more reasonable level in Linux. 

git-svn-id: http://pcsx2.googlecode.com/svn/trunk@994 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
arcum42 2009-04-17 00:35:55 +00:00
parent ecbef93c6b
commit 4704ac9436
6 changed files with 54 additions and 54 deletions
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6
pcsx2/x86/ix86/implement/dwshift.h
View File

@ -32,7 +32,7 @@ class DwordShiftImpl : public ImplementationHelper< ImmType >
protected: protected:
static void basesibform( bool isCL ) static void basesibform( bool isCL )
{ {
prefix16(); ImplementationHelper<ImmType>::prefix16();
write8( 0x0f ); write8( 0x0f );
write8( (isCL ? 0xa5 : 0xa4) | (isShiftRight ? 0x8 : 0) ); write8( (isCL ? 0xa5 : 0xa4) | (isShiftRight ? 0x8 : 0) );
} }
@ -42,7 +42,7 @@ public:
static __emitinline void Emit( const iRegister<ImmType>& to, const iRegister<ImmType>& from ) static __emitinline void Emit( const iRegister<ImmType>& to, const iRegister<ImmType>& from )
{ {
prefix16(); ImplementationHelper<ImmType>::prefix16();
write16( 0xa50f | (isShiftRight ? 0x800 : 0) ); write16( 0xa50f | (isShiftRight ? 0x800 : 0) );
ModRM_Direct( from.Id, to.Id ); ModRM_Direct( from.Id, to.Id );
} }
@ -50,7 +50,7 @@ public:
static __emitinline void Emit( const iRegister<ImmType>& to, const iRegister<ImmType>& from, u8 imm ) static __emitinline void Emit( const iRegister<ImmType>& to, const iRegister<ImmType>& from, u8 imm )
{ {
if( imm == 0 ) return; if( imm == 0 ) return;
prefix16(); ImplementationHelper<ImmType>::prefix16();
write16( 0xa40f | (isShiftRight ? 0x800 : 0) ); write16( 0xa40f | (isShiftRight ? 0x800 : 0) );
ModRM_Direct( from.Id, to.Id ); ModRM_Direct( from.Id, to.Id );
write8( imm ); write8( imm );

32
pcsx2/x86/ix86/implement/group1.h
View File

@ -42,43 +42,43 @@ public:
static __emitinline void Emit( const iRegister<ImmType>& to, const iRegister<ImmType>& from ) static __emitinline void Emit( const iRegister<ImmType>& to, const iRegister<ImmType>& from )
{ {
prefix16(); ImplementationHelper<ImmType>::prefix16();
iWrite<u8>( (Is8BitOperand() ? 0 : 1) | (InstType<<3) ); iWrite<u8>( (ImplementationHelper<ImmType>::Is8BitOperand() ? 0 : 1) | (InstType<<3) );
ModRM_Direct( from.Id, to.Id ); ModRM_Direct( from.Id, to.Id );
} }
static __emitinline void Emit( const ModSibBase& sibdest, const iRegister<ImmType>& from ) static __emitinline void Emit( const ModSibBase& sibdest, const iRegister<ImmType>& from )
{ {
prefix16(); ImplementationHelper<ImmType>::prefix16();
iWrite<u8>( (Is8BitOperand() ? 0 : 1) | (InstType<<3) ); iWrite<u8>( (ImplementationHelper<ImmType>::Is8BitOperand() ? 0 : 1) | (InstType<<3) );
EmitSibMagic( from.Id, sibdest ); EmitSibMagic( from.Id, sibdest );
} }
static __emitinline void Emit( const iRegister<ImmType>& to, const ModSibBase& sibsrc ) static __emitinline void Emit( const iRegister<ImmType>& to, const ModSibBase& sibsrc )
{ {
prefix16(); ImplementationHelper<ImmType>::prefix16();
iWrite<u8>( (Is8BitOperand() ? 2 : 3) | (InstType<<3) ); iWrite<u8>( (ImplementationHelper<ImmType>::Is8BitOperand() ? 2 : 3) | (InstType<<3) );
EmitSibMagic( to.Id, sibsrc ); EmitSibMagic( to.Id, sibsrc );
} }
static __emitinline void Emit( void* dest, const iRegister<ImmType>& from ) static __emitinline void Emit( void* dest, const iRegister<ImmType>& from )
{ {
prefix16(); ImplementationHelper<ImmType>::prefix16();
iWrite<u8>( (Is8BitOperand() ? 0 : 1) | (InstType<<3) ); iWrite<u8>( (ImplementationHelper<ImmType>::Is8BitOperand() ? 0 : 1) | (InstType<<3) );
iWriteDisp( from.Id, dest ); iWriteDisp( from.Id, dest );
} }
static __emitinline void Emit( const iRegister<ImmType>& to, const void* src ) static __emitinline void Emit( const iRegister<ImmType>& to, const void* src )
{ {
prefix16(); ImplementationHelper<ImmType>::prefix16();
iWrite<u8>( (Is8BitOperand() ? 2 : 3) | (InstType<<3) ); iWrite<u8>( (ImplementationHelper<ImmType>::Is8BitOperand() ? 2 : 3) | (InstType<<3) );
iWriteDisp( to.Id, src ); iWriteDisp( to.Id, src );
} }
static __emitinline void Emit( const iRegister<ImmType>& to, int imm ) static __emitinline void Emit( const iRegister<ImmType>& to, int imm )
{ {
prefix16(); ImplementationHelper<ImmType>::prefix16();
if( !Is8BitOperand() && is_s8( imm ) ) if( !ImplementationHelper<ImmType>::Is8BitOperand() && is_s8( imm ) )
{ {
iWrite<u8>( 0x83 ); iWrite<u8>( 0x83 );
ModRM_Direct( InstType, to.Id ); ModRM_Direct( InstType, to.Id );
@ -87,10 +87,10 @@ public:
else else
{ {
if( to.IsAccumulator() ) if( to.IsAccumulator() )
iWrite<u8>( (Is8BitOperand() ? 4 : 5) | (InstType<<3) ); iWrite<u8>( (ImplementationHelper<ImmType>::Is8BitOperand() ? 4 : 5) | (InstType<<3) );
else else
{ {
iWrite<u8>( Is8BitOperand() ? 0x80 : 0x81 ); iWrite<u8>( ImplementationHelper<ImmType>::Is8BitOperand() ? 0x80 : 0x81 );
ModRM_Direct( InstType, to.Id ); ModRM_Direct( InstType, to.Id );
} }
iWrite<ImmType>( imm ); iWrite<ImmType>( imm );
@ -99,7 +99,7 @@ public:
static __emitinline void Emit( const ModSibStrict<ImmType>& sibdest, int imm ) static __emitinline void Emit( const ModSibStrict<ImmType>& sibdest, int imm )
{ {
if( Is8BitOperand() ) if( ImplementationHelper<ImmType>::Is8BitOperand() )
{ {
iWrite<u8>( 0x80 ); iWrite<u8>( 0x80 );
EmitSibMagic( InstType, sibdest ); EmitSibMagic( InstType, sibdest );
@ -107,7 +107,7 @@ public:
} }
else else
{ {
prefix16(); ImplementationHelper<ImmType>::prefix16();
iWrite<u8>( is_s8( imm ) ? 0x83 : 0x81 ); iWrite<u8>( is_s8( imm ) ? 0x83 : 0x81 );
EmitSibMagic( InstType, sibdest ); EmitSibMagic( InstType, sibdest );
if( is_s8( imm ) ) if( is_s8( imm ) )

20
pcsx2/x86/ix86/implement/group2.h
View File

@ -46,8 +46,8 @@ public:
static __emitinline void Emit( const iRegister<ImmType>& to ) static __emitinline void Emit( const iRegister<ImmType>& to )
{ {
prefix16(); ImplementationHelper<ImmType>::prefix16();
iWrite<u8>( Is8BitOperand() ? 0xd2 : 0xd3 ); iWrite<u8>( ImplementationHelper<ImmType>::Is8BitOperand() ? 0xd2 : 0xd3 );
ModRM_Direct( InstType, to.Id ); ModRM_Direct( InstType, to.Id );
} }
@ -55,16 +55,16 @@ public:
{ {
if( imm == 0 ) return; if( imm == 0 ) return;
prefix16(); ImplementationHelper<ImmType>::prefix16();
if( imm == 1 ) if( imm == 1 )
{ {
// special encoding of 1's // special encoding of 1's
iWrite<u8>( Is8BitOperand() ? 0xd0 : 0xd1 ); iWrite<u8>( ImplementationHelper<ImmType>::Is8BitOperand() ? 0xd0 : 0xd1 );
ModRM_Direct( InstType, to.Id ); ModRM_Direct( InstType, to.Id );
} }
else else
{ {
iWrite<u8>( Is8BitOperand() ? 0xc0 : 0xc1 ); iWrite<u8>( ImplementationHelper<ImmType>::Is8BitOperand() ? 0xc0 : 0xc1 );
ModRM_Direct( InstType, to.Id ); ModRM_Direct( InstType, to.Id );
iWrite<u8>( imm ); iWrite<u8>( imm );
} }
@ -72,8 +72,8 @@ public:
static __emitinline void Emit( const ModSibStrict<ImmType>& sibdest ) static __emitinline void Emit( const ModSibStrict<ImmType>& sibdest )
{ {
prefix16(); ImplementationHelper<ImmType>::prefix16();
iWrite<u8>( Is8BitOperand() ? 0xd2 : 0xd3 ); iWrite<u8>( ImplementationHelper<ImmType>::Is8BitOperand() ? 0xd2 : 0xd3 );
EmitSibMagic( InstType, sibdest ); EmitSibMagic( InstType, sibdest );
} }
@ -81,16 +81,16 @@ public:
{ {
if( imm == 0 ) return; if( imm == 0 ) return;
prefix16(); ImplementationHelper<ImmType>::prefix16();
if( imm == 1 ) if( imm == 1 )
{ {
// special encoding of 1's // special encoding of 1's
iWrite<u8>( Is8BitOperand() ? 0xd0 : 0xd1 ); iWrite<u8>( ImplementationHelper<ImmType>::Is8BitOperand() ? 0xd0 : 0xd1 );
EmitSibMagic( InstType, sibdest ); EmitSibMagic( InstType, sibdest );
} }
else else
{ {
iWrite<u8>( Is8BitOperand() ? 0xc0 : 0xc1 ); iWrite<u8>( ImplementationHelper<ImmType>::Is8BitOperand() ? 0xc0 : 0xc1 );
EmitSibMagic( InstType, sibdest ); EmitSibMagic( InstType, sibdest );
iWrite<u8>( imm ); iWrite<u8>( imm );
} }

8
pcsx2/x86/ix86/implement/group3.h
View File

@ -39,15 +39,15 @@ public:
static __emitinline void Emit( G3Type InstType, const iRegister<ImmType>& from ) static __emitinline void Emit( G3Type InstType, const iRegister<ImmType>& from )
{ {
prefix16(); ImplementationHelper<ImmType>::prefix16();
iWrite<u8>( Is8BitOperand() ? 0xf6 : 0xf7 ); iWrite<u8>(ImplementationHelper<ImmType>::Is8BitOperand() ? 0xf6 : 0xf7 );
ModRM_Direct( InstType, from.Id ); ModRM_Direct( InstType, from.Id );
} }
static __emitinline void Emit( G3Type InstType, const ModSibStrict<ImmType>& sibsrc ) static __emitinline void Emit( G3Type InstType, const ModSibStrict<ImmType>& sibsrc )
{ {
prefix16(); ImplementationHelper<ImmType>::prefix16();
iWrite<u8>( Is8BitOperand() ? 0xf6 : 0xf7 ); iWrite<u8>( ImplementationHelper<ImmType>::Is8BitOperand() ? 0xf6 : 0xf7 );
EmitSibMagic( InstType, sibsrc ); EmitSibMagic( InstType, sibsrc );
} }
}; };

6
pcsx2/x86/ix86/implement/incdec.h
View File

@ -31,21 +31,21 @@ public:
{ {
// There is no valid 8-bit form of direct register inc/dec, so fall // There is no valid 8-bit form of direct register inc/dec, so fall
// back on Mod/RM format instead: // back on Mod/RM format instead:
if( Is8BitOperand() ) if (ImplementationHelper<ImmType>::Is8BitOperand() )
{ {
write8( 0xfe ); write8( 0xfe );
ModRM_Direct( isDec ? 1 : 0, to.Id ); ModRM_Direct( isDec ? 1 : 0, to.Id );
} }
else else
{ {
prefix16(); ImplementationHelper<ImmType>::prefix16();
write8( (isDec ? 0x48 : 0x40) | to.Id ); write8( (isDec ? 0x48 : 0x40) | to.Id );
} }
} }
static __emitinline void Emit( bool isDec, const ModSibStrict<ImmType>& dest ) static __emitinline void Emit( bool isDec, const ModSibStrict<ImmType>& dest )
{ {
write8( Is8BitOperand() ? 0xfe : 0xff ); write8( ImplementationHelper<ImmType>::Is8BitOperand() ? 0xfe : 0xff );
EmitSibMagic( isDec ? 1: 0, dest ); EmitSibMagic( isDec ? 1: 0, dest );
} }
}; };

36
pcsx2/x86/ix86/implement/movs.h
View File

@ -33,27 +33,27 @@ public:
{ {
if( to == from ) return; // ignore redundant MOVs. if( to == from ) return; // ignore redundant MOVs.
prefix16(); ImplementationHelper<ImmType>::prefix16();
iWrite<u8>( Is8BitOperand() ? 0x88 : 0x89 ); iWrite<u8>( ImplementationHelper<ImmType>::Is8BitOperand() ? 0x88 : 0x89 );
ModRM( 3, from.Id, to.Id ); ModRM( 3, from.Id, to.Id );
} }
// ------------------------------------------------------------------------ // ------------------------------------------------------------------------
static __forceinline void Emit( const ModSibBase& dest, const iRegister<ImmType>& from ) static __forceinline void Emit( const ModSibBase& dest, const iRegister<ImmType>& from )
{ {
prefix16(); ImplementationHelper<ImmType>::prefix16();
// mov eax has a special from when writing directly to a DISP32 address // mov eax has a special from when writing directly to a DISP32 address
// (sans any register index/base registers). // (sans any register index/base registers).
if( from.IsAccumulator() && dest.Index.IsEmpty() && dest.Base.IsEmpty() ) if( from.IsAccumulator() && dest.Index.IsEmpty() && dest.Base.IsEmpty() )
{ {
iWrite<u8>( Is8BitOperand() ? 0xa2 : 0xa3 ); iWrite<u8>( ImplementationHelper<ImmType>::Is8BitOperand() ? 0xa2 : 0xa3 );
iWrite<u32>( dest.Displacement ); iWrite<u32>( dest.Displacement );
} }
else else
{ {
iWrite<u8>( Is8BitOperand() ? 0x88 : 0x89 ); iWrite<u8>( ImplementationHelper<ImmType>::Is8BitOperand() ? 0x88 : 0x89 );
EmitSibMagic( from.Id, dest ); EmitSibMagic( from.Id, dest );
} }
} }
@ -61,19 +61,19 @@ public:
// ------------------------------------------------------------------------ // ------------------------------------------------------------------------
static __forceinline void Emit( const iRegister<ImmType>& to, const ModSibBase& src ) static __forceinline void Emit( const iRegister<ImmType>& to, const ModSibBase& src )
{ {
prefix16(); ImplementationHelper<ImmType>::prefix16();
// mov eax has a special from when reading directly from a DISP32 address // mov eax has a special from when reading directly from a DISP32 address
// (sans any register index/base registers). // (sans any register index/base registers).
if( to.IsAccumulator() && src.Index.IsEmpty() && src.Base.IsEmpty() ) if( to.IsAccumulator() && src.Index.IsEmpty() && src.Base.IsEmpty() )
{ {
iWrite<u8>( Is8BitOperand() ? 0xa0 : 0xa1 ); iWrite<u8>( ImplementationHelper<ImmType>::Is8BitOperand() ? 0xa0 : 0xa1 );
iWrite<u32>( src.Displacement ); iWrite<u32>( src.Displacement );
} }
else else
{ {
iWrite<u8>( Is8BitOperand() ? 0x8a : 0x8b ); iWrite<u8>( ImplementationHelper<ImmType>::Is8BitOperand() ? 0x8a : 0x8b );
EmitSibMagic( to.Id, src ); EmitSibMagic( to.Id, src );
} }
} }
@ -81,18 +81,18 @@ public:
// ------------------------------------------------------------------------ // ------------------------------------------------------------------------
static __forceinline void Emit( void* dest, const iRegister<ImmType>& from ) static __forceinline void Emit( void* dest, const iRegister<ImmType>& from )
{ {
prefix16(); ImplementationHelper<ImmType>::prefix16();
// mov eax has a special from when writing directly to a DISP32 address // mov eax has a special from when writing directly to a DISP32 address
if( from.IsAccumulator() ) if( from.IsAccumulator() )
{ {
iWrite<u8>( Is8BitOperand() ? 0xa2 : 0xa3 ); iWrite<u8>( ImplementationHelper<ImmType>::Is8BitOperand() ? 0xa2 : 0xa3 );
iWrite<s32>( (s32)dest ); iWrite<s32>( (s32)dest );
} }
else else
{ {
iWrite<u8>( Is8BitOperand() ? 0x88 : 0x89 ); iWrite<u8>( ImplementationHelper<ImmType>::Is8BitOperand() ? 0x88 : 0x89 );
iWriteDisp( from.Id, dest ); iWriteDisp( from.Id, dest );
} }
} }
@ -100,18 +100,18 @@ public:
// ------------------------------------------------------------------------ // ------------------------------------------------------------------------
static __forceinline void Emit( const iRegister<ImmType>& to, const void* src ) static __forceinline void Emit( const iRegister<ImmType>& to, const void* src )
{ {
prefix16(); ImplementationHelper<ImmType>::prefix16();
// mov eax has a special from when reading directly from a DISP32 address // mov eax has a special from when reading directly from a DISP32 address
if( to.IsAccumulator() ) if( to.IsAccumulator() )
{ {
iWrite<u8>( Is8BitOperand() ? 0xa0 : 0xa1 ); iWrite<u8>( ImplementationHelper<ImmType>::Is8BitOperand() ? 0xa0 : 0xa1 );
iWrite<s32>( (s32)src ); iWrite<s32>( (s32)src );
} }
else else
{ {
iWrite<u8>( Is8BitOperand() ? 0x8a : 0x8b ); iWrite<u8>( ImplementationHelper<ImmType>::Is8BitOperand() ? 0x8a : 0x8b );
iWriteDisp( to.Id, src ); iWriteDisp( to.Id, src );
} }
} }
@ -121,16 +121,16 @@ public:
{ {
// Note: MOV does not have (reg16/32,imm8) forms. // Note: MOV does not have (reg16/32,imm8) forms.
prefix16(); ImplementationHelper<ImmType>::prefix16();
iWrite<u8>( (Is8BitOperand() ? 0xb0 : 0xb8) | to.Id ); iWrite<u8>( (ImplementationHelper<ImmType>::Is8BitOperand() ? 0xb0 : 0xb8) | to.Id );
iWrite<ImmType>( imm ); iWrite<ImmType>( imm );
} }
// ------------------------------------------------------------------------ // ------------------------------------------------------------------------
static __forceinline void Emit( ModSibStrict<ImmType> dest, ImmType imm ) static __forceinline void Emit( ModSibStrict<ImmType> dest, ImmType imm )
{ {
prefix16(); ImplementationHelper<ImmType>::prefix16();
iWrite<u8>( Is8BitOperand() ? 0xc6 : 0xc7 ); iWrite<u8>( ImplementationHelper<ImmType>::Is8BitOperand() ? 0xc6 : 0xc7 );
EmitSibMagic( 0, dest ); EmitSibMagic( 0, dest );
iWrite<ImmType>( imm ); iWrite<ImmType>( imm );
} }