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ZeroSPU2: Reformat zerospu2.cpp & h so that they are readable. Change a few unneccessary case statements into if statements. 

git-svn-id: http://pcsx2-playground.googlecode.com/svn/trunk@505 a6443dda-0b58-4228-96e9-037be469359c
This commit is contained in:
arcum42 2008-12-26 14:25:22 +00:00 committed by Gregory Hainaut
parent 6ba8e669e7
commit 4531a1406f
3 changed files with 1734 additions and 1640 deletions
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16
plugins/zerospu2/Linux/Alsa.cpp
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@ -34,18 +34,12 @@ int AlsaSetupSound()
snd_pcm_hw_params_t *hwparams; snd_pcm_hw_params_t *hwparams;
snd_pcm_sw_params_t *swparams; snd_pcm_sw_params_t *swparams;
snd_pcm_status_t *status; snd_pcm_status_t *status;
unsigned int pspeed; unsigned int pspeed = 48000;
int pchannels; int pchannels = 2;
snd_pcm_format_t format; snd_pcm_format_t format = SND_PCM_FORMAT_S16_LE;
unsigned int buffer_time, period_time; unsigned int buffer_time = SOUNDSIZE;
unsigned int period_time= buffer_time / 4;
int err; int err;
pchannels=2;
pspeed = 48000;
format = SND_PCM_FORMAT_S16_LE;
buffer_time = SOUNDSIZE;
period_time = buffer_time / 4;
err = snd_pcm_open(&handle, "default", SND_PCM_STREAM_PLAYBACK, SND_PCM_NONBLOCK); err = snd_pcm_open(&handle, "default", SND_PCM_STREAM_PLAYBACK, SND_PCM_NONBLOCK);
if(err < 0) { if(err < 0) {

2941
plugins/zerospu2/zerospu2.cpp
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File diff suppressed because it is too large Load Diff

417
plugins/zerospu2/zerospu2.h
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@ -33,21 +33,21 @@ extern "C" {
#ifdef __LINUX__ #ifdef __LINUX__
#include <unistd.h> #include <unistd.h>
#include <gtk/gtk.h> #include <gtk/gtk.h>
#include <sys/timeb.h> // ftime(), struct timeb #include <sys/timeb.h> // ftime(), struct timeb
#define Sleep(ms) usleep(1000*ms) #define Sleep(ms) usleep(1000*ms)
inline unsigned long timeGetTime() inline unsigned long timeGetTime()
{ {
#ifdef _WIN32 #ifdef _WIN32
_timeb t; _timeb t;
_ftime(&t); _ftime(&t);
#else #else
timeb t; timeb t;
ftime(&t); ftime(&t);
#endif #endif
return (unsigned long)(t.time*1000+t.millitm); return (unsigned long)(t.time*1000+t.millitm);
} }
#include <sys/time.h> #include <sys/time.h>
@ -56,21 +56,21 @@ inline unsigned long timeGetTime()
#include <windows.h> #include <windows.h>
#include <windowsx.h> #include <windowsx.h>
#include <sys/timeb.h> // ftime(), struct timeb #include <sys/timeb.h> // ftime(), struct timeb
#endif #endif
inline u64 GetMicroTime() inline u64 GetMicroTime()
{ {
#ifdef _WIN32 #ifdef _WIN32
extern LARGE_INTEGER g_counterfreq; extern LARGE_INTEGER g_counterfreq;
LARGE_INTEGER count; LARGE_INTEGER count;
QueryPerformanceCounter(&count); QueryPerformanceCounter(&count);
return count.QuadPart * 1000000 / g_counterfreq.QuadPart; return count.QuadPart * 1000000 / g_counterfreq.QuadPart;
#else #else
timeval t; timeval t;
gettimeofday(&t, NULL); gettimeofday(&t, NULL);
return t.tv_sec*1000000+t.tv_usec; return t.tv_sec*1000000+t.tv_usec;
#endif #endif
} }
@ -88,7 +88,7 @@ extern FILE *spu2Log;
#define SPU2_VERSION PS2E_SPU2_VERSION #define SPU2_VERSION PS2E_SPU2_VERSION
#define SPU2_REVISION 0 #define SPU2_REVISION 0
#define SPU2_BUILD 4 // increase that with each version #define SPU2_BUILD 4 // increase that with each version
#define SPU2_MINOR 6 #define SPU2_MINOR 6
#define OPTION_TIMESTRETCH 1 // stretches samples without changing pitch to reduce cracking #define OPTION_TIMESTRETCH 1 // stretches samples without changing pitch to reduce cracking
@ -97,8 +97,8 @@ extern FILE *spu2Log;
#define OPTION_RECORDING 8 #define OPTION_RECORDING 8
typedef struct { typedef struct {
int Log; int Log;
int options; int options;
} Config; } Config;
extern Config conf; extern Config conf;
@ -125,7 +125,7 @@ void SoundFeedVoiceData(unsigned char* pSound,long lBytes);
// declare linux equivalents // declare linux equivalents
extern __forceinline void* pcsx2_aligned_malloc(size_t size, size_t align) extern __forceinline void* pcsx2_aligned_malloc(size_t size, size_t align)
{ {
assert( align < 0x10000 ); assert( align < 0x10000 );
char* p = (char*)malloc(size+align); char* p = (char*)malloc(size+align);
int off = 2+align - ((int)(uptr)(p+2) % align); int off = 2+align - ((int)(uptr)(p+2) % align);
@ -137,10 +137,10 @@ extern __forceinline void* pcsx2_aligned_malloc(size_t size, size_t align)
extern __forceinline void pcsx2_aligned_free(void* pmem) extern __forceinline void pcsx2_aligned_free(void* pmem)
{ {
if( pmem != NULL ) { if( pmem != NULL ) {
char* p = (char*)pmem; char* p = (char*)pmem;
free(p - (int)*(u16*)(p-2)); free(p - (int)*(u16*)(p-2));
} }
} }
#define _aligned_malloc pcsx2_aligned_malloc #define _aligned_malloc pcsx2_aligned_malloc
@ -148,54 +148,77 @@ extern __forceinline void pcsx2_aligned_free(void* pmem)
#endif #endif
// Atomic Operations
#if defined (_WIN32)
#ifndef __x86_64__
extern "C" LONG __cdecl _InterlockedExchangeAdd(LPLONG volatile Addend, LONG Value);
#endif
#pragma intrinsic (_InterlockedExchangeAdd)
#define InterlockedExchangeAdd _InterlockedExchangeAdd
#else
typedef void* PVOID;
__forceinline long InterlockedExchangeAdd(long volatile* Addend, long Value)
{
__asm__ __volatile__(".intel_syntax\n"
"lock xadd [%0], %%eax\n"
".att_syntax\n" : : "r"(Addend), "a"(Value) : "memory" );
}
#endif
//////////////////// ////////////////////
// SPU2 Registers // // SPU2 Registers //
//////////////////// ////////////////////
#define REG_VP_VOLL 0x0000 #define REG_VP_VOLL 0x0000
#define REG_VP_VOLR 0x0002 #define REG_VP_VOLR 0x0002
#define REG_VP_PITCH 0x0004 #define REG_VP_PITCH 0x0004
#define REG_VP_ADSR1 0x0006 #define REG_VP_ADSR1 0x0006
#define REG_VP_ADSR2 0x0008 #define REG_VP_ADSR2 0x0008
#define REG_VP_ENVX 0x000A #define REG_VP_ENVX 0x000A
#define REG_VP_VOLXL 0x000C #define REG_VP_VOLXL 0x000C
#define REG_VP_VOLXR 0x000E #define REG_VP_VOLXR 0x000E
#define REG_C0_FMOD1 0x0180 #define REG_C0_FMOD1 0x0180
#define REG_C0_FMOD2 0x0182 #define REG_C0_FMOD2 0x0182
#define REG_C0_VMIXL1 0x0188 #define REG_C0_VMIXL1 0x0188
#define REG_C0_VMIXL2 0x018A #define REG_C0_VMIXL2 0x018A
#define REG_C0_VMIXR1 0x0190 #define REG_C0_VMIXR1 0x0190
#define REG_C0_VMIXR2 0x0192 #define REG_C0_VMIXR2 0x0192
#define REG_C0_MMIX 0x0198 #define REG_C0_MMIX 0x0198
#define REG_C0_CTRL 0x019A #define REG_C0_CTRL 0x019A
#define REG_C0_IRQA_HI 0x019C #define REG_C0_IRQA_HI 0x019C
#define REG_C0_IRQA_LO 0x019E #define REG_C0_IRQA_LO 0x019E
#define REG_C0_SPUON1 0x1A0 #define REG_C0_SPUON1 0x1A0
#define REG_C0_SPUON2 0x1A2 #define REG_C0_SPUON2 0x1A2
#define REG_C0_SPUOFF1 0x1A4 #define REG_C0_SPUOFF1 0x1A4
#define REG_C0_SPUOFF2 0x1A6 #define REG_C0_SPUOFF2 0x1A6
#define REG_C0_SPUADDR_HI 0x01A8 #define REG_C0_SPUADDR_HI 0x01A8
#define REG_C0_SPUADDR_LO 0x01AA #define REG_C0_SPUADDR_LO 0x01AA
#define REG_C0_SPUDATA 0x01AC #define REG_C0_SPUDATA 0x01AC
#define REG_C0_DMACTRL 0x01AE #define REG_C0_DMACTRL 0x01AE
#define REG_C0_ADMAS 0x01B0 #define REG_C0_ADMAS 0x01B0
#define REG_C0_END1 0x0340 #define REG_C0_END1 0x0340
#define REG_C0_END2 0x0342 #define REG_C0_END2 0x0342
#define REG_C0_SPUSTAT 0x0344 #define REG_C0_SPUSTAT 0x0344
#define REG_C0_BVOLL 0x076C #define REG_C0_BVOLL 0x076C
#define REG_C0_BVOLR 0x076E #define REG_C0_BVOLR 0x076E
//#define SPU2_TRANS_BY_DMA (0x0<<3) //#define SPU2_TRANS_BY_DMA (0x0<<3)
//#define SPU2_TRANS_BY_IO (0x1<<3) //#define SPU2_TRANS_BY_IO (0x1<<3)
// //
//#define SPU2_BLOCK_ONESHOT (0<<4) //#define SPU2_BLOCK_ONESHOT (0<<4)
//#define SPU2_BLOCK_LOOP (1<<4) //#define SPU2_BLOCK_LOOP (1<<4)
//#define SPU2_BLOCK_HANDLER (1<<7) //#define SPU2_BLOCK_HANDLER (1<<7)
//#define SPU2_BLOCK_C0_VOICE1 ( 0x0<<8 ) //#define SPU2_BLOCK_C0_VOICE1 ( 0x0<<8 )
//#define SPU2_BLOCK_C0_VOICE3 ( 0x1<<8 ) //#define SPU2_BLOCK_C0_VOICE3 ( 0x1<<8 )
//#define SPU2_BLOCK_C1_SINL ( 0x2<<8 ) //#define SPU2_BLOCK_C1_SINL ( 0x2<<8 )
//#define SPU2_BLOCK_C1_SINR ( 0x3<<8 ) //#define SPU2_BLOCK_C1_SINR ( 0x3<<8 )
//#define SPU2_BLOCK_C1_VOICE1 ( 0x4<<8 ) //#define SPU2_BLOCK_C1_VOICE1 ( 0x4<<8 )
//#define SPU2_BLOCK_C1_VOICE3 ( 0x5<<8 ) //#define SPU2_BLOCK_C1_VOICE3 ( 0x5<<8 )
//#define SPU2_BLOCK_C0_MEMOUTL ( 0x6<<8 ) //#define SPU2_BLOCK_C0_MEMOUTL ( 0x6<<8 )
//#define SPU2_BLOCK_C0_MEMOUTR ( 0x7<<8 ) //#define SPU2_BLOCK_C0_MEMOUTR ( 0x7<<8 )
//#define SPU2_BLOCK_C0_MEMOUTEL ( 0x8<<8 ) //#define SPU2_BLOCK_C0_MEMOUTEL ( 0x8<<8 )
@ -237,57 +260,57 @@ extern __forceinline void pcsx2_aligned_free(void* pmem)
//#define SPU2_REV_SIZE_DELAY 0x18040 //#define SPU2_REV_SIZE_DELAY 0x18040
//#define SPU2_REV_SIZE_PIPE 0x3c00 //#define SPU2_REV_SIZE_PIPE 0x3c00
// //
//#define SPU2_SOUNDOUT_TOPADDR 0x0 //#define SPU2_SOUNDOUT_TOPADDR 0x0
//#define SPU2_SOUNDIN_TOPADDR 0x4000 //#define SPU2_SOUNDIN_TOPADDR 0x4000
//#define SPU2_USERAREA_TOPADDR 0x5010 //#define SPU2_USERAREA_TOPADDR 0x5010
// //
//#define SPU2_INIT_COLD 0 //#define SPU2_INIT_COLD 0
//#define SPU2_INIT_HOT 1 //#define SPU2_INIT_HOT 1
#define REG_C1_FMOD1 0x0580 #define REG_C1_FMOD1 0x0580
#define REG_C1_FMOD2 0x0582 #define REG_C1_FMOD2 0x0582
#define REG_S_NON 0x0184 #define REG_S_NON 0x0184
#define REG_C1_VMIXL1 0x0588 #define REG_C1_VMIXL1 0x0588
#define REG_C1_VMIXL2 0x058A #define REG_C1_VMIXL2 0x058A
#define REG_S_VMIXEL 0x018C #define REG_S_VMIXEL 0x018C
#define REG_C1_VMIXR1 0x0590 #define REG_C1_VMIXR1 0x0590
#define REG_C1_VMIXR2 0x0592 #define REG_C1_VMIXR2 0x0592
#define REG_S_VMIXER 0x0194 #define REG_S_VMIXER 0x0194
#define REG_C1_MMIX 0x0598 #define REG_C1_MMIX 0x0598
#define REG_C1_IRQA_HI 0x059C #define REG_C1_IRQA_HI 0x059C
#define REG_C1_IRQA_LO 0x059E #define REG_C1_IRQA_LO 0x059E
#define REG_C1_SPUON1 0x5A0 #define REG_C1_SPUON1 0x5A0
#define REG_C1_SPUON2 0x5A2 #define REG_C1_SPUON2 0x5A2
#define REG_C1_SPUOFF1 0x5A4 #define REG_C1_SPUOFF1 0x5A4
#define REG_C1_SPUOFF2 0x5A6 #define REG_C1_SPUOFF2 0x5A6
#define REG_C1_SPUADDR_HI 0x05A8 #define REG_C1_SPUADDR_HI 0x05A8
#define REG_C1_SPUADDR_LO 0x05AA #define REG_C1_SPUADDR_LO 0x05AA
#define REG_C1_SPUDATA 0x05AC #define REG_C1_SPUDATA 0x05AC
#define REG_C1_DMACTRL 0x05AE #define REG_C1_DMACTRL 0x05AE
#define REG_VA_SSA 0x01C0 #define REG_VA_SSA 0x01C0
#define REG_VA_LSAX 0x01C4 #define REG_VA_LSAX 0x01C4
#define REG_VA_NAX 0x01C8 #define REG_VA_NAX 0x01C8
#define REG_A_ESA 0x02E0 #define REG_A_ESA 0x02E0
#define REG_A_EEA 0x033C #define REG_A_EEA 0x033C
#define REG_C1_END1 0x0740 #define REG_C1_END1 0x0740
#define REG_C1_END2 0x0742 #define REG_C1_END2 0x0742
#define REG_C1_CTRL 0x059A #define REG_C1_CTRL 0x059A
#define REG_C1_ADMAS 0x05B0 #define REG_C1_ADMAS 0x05B0
#define REG_C1_SPUSTAT 0x0744 #define REG_C1_SPUSTAT 0x0744
#define REG_P_MVOLL 0x0760 #define REG_P_MVOLL 0x0760
#define REG_P_MVOLR 0x0762 #define REG_P_MVOLR 0x0762
#define REG_P_EVOLL 0x0764 #define REG_P_EVOLL 0x0764
#define REG_P_EVOLR 0x0766 #define REG_P_EVOLR 0x0766
#define REG_P_AVOLL 0x0768 #define REG_P_AVOLL 0x0768
#define REG_P_AVOLR 0x076A #define REG_P_AVOLR 0x076A
#define REG_C1_BVOLL 0x0794 #define REG_C1_BVOLL 0x0794
#define REG_C1_BVOLR 0x0796 #define REG_C1_BVOLR 0x0796
#define REG_P_MVOLXL 0x0770 #define REG_P_MVOLXL 0x0770
#define REG_P_MVOLXR 0x0772 #define REG_P_MVOLXR 0x0772
#define SPDIF_OUT 0x07C0 #define SPDIF_OUT 0x07C0
#define REG_IRQINFO 0x07C2 #define REG_IRQINFO 0x07C2
#define SPDIF_MODE 0x07C6 #define SPDIF_MODE 0x07C6
#define SPDIF_MEDIA 0x07C8 #define SPDIF_MEDIA 0x07C8
#define SPU_AUTODMA_ONESHOT 0 //spu2 #define SPU_AUTODMA_ONESHOT 0 //spu2
#define SPU_AUTODMA_LOOP 1 //spu2 #define SPU_AUTODMA_LOOP 1 //spu2
@ -302,9 +325,9 @@ extern __forceinline void pcsx2_aligned_free(void* pmem)
#define SPU2_GET32BIT(lo,hi) (((u32)(spu2Ru16(hi)&0x3f)<<16)|(u32)spu2Ru16(lo)) #define SPU2_GET32BIT(lo,hi) (((u32)(spu2Ru16(hi)&0x3f)<<16)|(u32)spu2Ru16(lo))
#define SPU2_SET32BIT(value, lo, hi) { \ #define SPU2_SET32BIT(value, lo, hi) { \
spu2Ru16(hi) = ((value)>>16)&0x3f; \ spu2Ru16(hi) = ((value)>>16)&0x3f; \
spu2Ru16(lo) = (value)&0xffff; \ spu2Ru16(lo) = (value)&0xffff; \
} \ } \
#define C0_IRQA SPU2_GET32BIT(REG_C0_IRQA_LO, REG_C0_IRQA_HI) #define C0_IRQA SPU2_GET32BIT(REG_C0_IRQA_LO, REG_C0_IRQA_HI)
#define C1_IRQA SPU2_GET32BIT(REG_C1_IRQA_LO, REG_C1_IRQA_HI) #define C1_IRQA SPU2_GET32BIT(REG_C1_IRQA_LO, REG_C1_IRQA_HI)
@ -315,20 +338,20 @@ extern __forceinline void pcsx2_aligned_free(void* pmem)
#define C0_SPUADDR_SET(value) SPU2_SET32BIT(value, REG_C0_SPUADDR_LO, REG_C0_SPUADDR_HI) #define C0_SPUADDR_SET(value) SPU2_SET32BIT(value, REG_C0_SPUADDR_LO, REG_C0_SPUADDR_HI)
#define C1_SPUADDR_SET(value) SPU2_SET32BIT(value, REG_C1_SPUADDR_LO, REG_C1_SPUADDR_HI) #define C1_SPUADDR_SET(value) SPU2_SET32BIT(value, REG_C1_SPUADDR_LO, REG_C1_SPUADDR_HI)
#define SPU_NUMBER_VOICES 48 #define SPU_NUMBER_VOICES 48
struct SPU_CONTROL_ struct SPU_CONTROL_
{ {
u16 extCd : 1; u16 extCd : 1;
u16 extAudio : 1; u16 extAudio : 1;
u16 cdreverb : 1; u16 cdreverb : 1;
u16 extr : 1; // external reverb u16 extr : 1; // external reverb
u16 dma : 2; // 1 - no dma, 2 - write, 3 - read u16 dma : 2; // 1 - no dma, 2 - write, 3 - read
u16 irq : 1; u16 irq : 1;
u16 reverb : 1; u16 reverb : 1;
u16 noiseFreq : 6; u16 noiseFreq : 6;
u16 spuUnmute : 1; u16 spuUnmute : 1;
u16 spuon : 1; u16 spuon : 1;
}; };
#if defined(_MSC_VER) #if defined(_MSC_VER)
@ -337,42 +360,42 @@ struct SPU_CONTROL_
// the layout of each voice in wSpuRegs // the layout of each voice in wSpuRegs
struct _SPU_VOICE struct _SPU_VOICE
{ {
union union
{ {
struct { struct {
u16 Vol : 14; u16 Vol : 14;
u16 Inverted : 1; u16 Inverted : 1;
u16 Sweep0 : 1; u16 Sweep0 : 1;
} vol; } vol;
struct { struct {
u16 Vol : 7; u16 Vol : 7;
u16 res1 : 5; u16 res1 : 5;
u16 Inverted : 1; u16 Inverted : 1;
u16 Decrease : 1; // if 0, increase u16 Decrease : 1; // if 0, increase
u16 ExpSlope : 1; // if 0, linear slope u16 ExpSlope : 1; // if 0, linear slope
u16 Sweep1 : 1; // always one u16 Sweep1 : 1; // always one
} sweep; } sweep;
u16 word; u16 word;
} left, right; } left, right;
u16 pitch : 14; // 1000 - no pitch, 2000 - pitch + 1, etc u16 pitch : 14; // 1000 - no pitch, 2000 - pitch + 1, etc
u16 res0 : 2; u16 res0 : 2;
u16 SustainLvl : 4; u16 SustainLvl : 4;
u16 DecayRate : 4; u16 DecayRate : 4;
u16 AttackRate : 7; u16 AttackRate : 7;
u16 AttackExp : 1; // if 0, linear u16 AttackExp : 1; // if 0, linear
u16 ReleaseRate : 5; u16 ReleaseRate : 5;
u16 ReleaseExp : 1; // if 0, linear u16 ReleaseExp : 1; // if 0, linear
u16 SustainRate : 7; u16 SustainRate : 7;
u16 res1 : 1; u16 res1 : 1;
u16 SustainDec : 1; // if 0, inc u16 SustainDec : 1; // if 0, inc
u16 SustainExp : 1; // if 0, linear u16 SustainExp : 1; // if 0, linear
u16 AdsrVol; u16 AdsrVol;
u16 Address; // add / 8 u16 Address; // add / 8
u16 RepeatAddr; // gets reset when sample starts u16 RepeatAddr; // gets reset when sample starts
#if defined(_MSC_VER) #if defined(_MSC_VER)
}; //+22 }; //+22
#else #else
@ -382,84 +405,84 @@ struct _SPU_VOICE
// ADSR INFOS PER CHANNEL // ADSR INFOS PER CHANNEL
struct ADSRInfoEx struct ADSRInfoEx
{ {
int State; int State;
int AttackModeExp; int AttackModeExp;
int AttackRate; int AttackRate;
int DecayRate; int DecayRate;
int SustainLevel; int SustainLevel;
int SustainModeExp; int SustainModeExp;
int SustainIncrease; int SustainIncrease;
int SustainRate; int SustainRate;
int ReleaseModeExp; int ReleaseModeExp;
int ReleaseRate; int ReleaseRate;
int EnvelopeVol; int EnvelopeVol;
long lVolume; long lVolume;
}; };
#define SPU_VOICE_STATE_SIZE (sizeof(VOICE_PROCESSED)-4*sizeof(void*)) #define SPU_VOICE_STATE_SIZE (sizeof(VOICE_PROCESSED)-4*sizeof(void*))
struct VOICE_PROCESSED struct VOICE_PROCESSED
{ {
VOICE_PROCESSED() VOICE_PROCESSED()
{ {
memset(this, 0, sizeof(VOICE_PROCESSED)); memset(this, 0, sizeof(VOICE_PROCESSED));
} }
void SetVolume(int right); void SetVolume(int right);
void StartSound(); void StartSound();
void VoiceChangeFrequency(); void VoiceChangeFrequency();
void InterpolateUp(); void InterpolateUp();
void InterpolateDown(); void InterpolateDown();
void FModChangeFrequency(int ns); void FModChangeFrequency(int ns);
int iGetNoiseVal(); int iGetNoiseVal();
void StoreInterpolationVal(int fa); void StoreInterpolationVal(int fa);
int iGetInterpolationVal(); int iGetInterpolationVal();
void Stop(); void Stop();
SPU_CONTROL_* GetCtrl(); SPU_CONTROL_* GetCtrl();
// start save state // start save state
int leftvol, rightvol; // left right volumes int leftvol, rightvol; // left right volumes
int iSBPos; // mixing stuff int iSBPos; // mixing stuff
int SB[32+32]; int SB[32+32];
int spos; int spos;
int sinc; int sinc;
int iIrqDone; // debug irq done flag int iIrqDone; // debug irq done flag
int s_1; // last decoding infos int s_1; // last decoding infos
int s_2; int s_2;
int iOldNoise; // old noise val for this channel int iOldNoise; // old noise val for this channel
int iActFreq; // current psx pitch int iActFreq; // current psx pitch
int iUsedFreq; // current pc pitch int iUsedFreq; // current pc pitch
int iStartAddr, iLoopAddr, iNextAddr; int iStartAddr, iLoopAddr, iNextAddr;
int bFMod; int bFMod;
ADSRInfoEx ADSRX; // next ADSR settings (will be moved to active on sample start) ADSRInfoEx ADSRX; // next ADSR settings (will be moved to active on sample start)
int memoffset; // if first core, 0, if second, 0x400 int memoffset; // if first core, 0, if second, 0x400
int chanid; // channel id int chanid; // channel id
bool bIgnoreLoop, bNew, bNoise, bReverb, bOn, bStop, bVolChanged; bool bIgnoreLoop, bNew, bNoise, bReverb, bOn, bStop, bVolChanged;
bool bVolumeR, bVolumeL; bool bVolumeR, bVolumeL;
// end save state // end save state
/////////////////// ///////////////////
// Sound Buffers // // Sound Buffers //
/////////////////// ///////////////////
u8* pStart; // start and end addresses u8* pStart; // start and end addresses
u8* pLoop, *pCurr; u8* pLoop, *pCurr;
_SPU_VOICE* pvoice; _SPU_VOICE* pvoice;
}; };
struct ADMA struct ADMA
{ {
unsigned short * MemAddr; unsigned short * MemAddr;
int Index; int Index;
int AmountLeft; int AmountLeft;
int Enabled; // used to make sure that ADMA doesn't get interrupted with a writeDMA call int Enabled; // used to make sure that ADMA doesn't get interrupted with a writeDMA call
}; };
#endif /* __SPU2_H__ */ #endif /* __SPU2_H__ */