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Odds and ends. Various defines involving vif->stat are now enums, and are now used in various places. Added a new file to GSnull. Moved the new Vif functions to Vif.h. 

git-svn-id: http://pcsx2.googlecode.com/svn/trunk@1670 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
arcum42 2009-08-22 09:52:00 +00:00
parent 21fed6e90c
commit 44bb5cdbb5
13 changed files with 194 additions and 109 deletions
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6
pcsx2/FiFo.cpp
View File

@ -72,10 +72,10 @@ void __fastcall ReadFIFO_page_5(u32 mem, u64 *out)
if( vif1Regs->stat & (VIF1_STAT_INT|VIF1_STAT_VSS|VIF1_STAT_VIS|VIF1_STAT_VFS) ) if( vif1Regs->stat & (VIF1_STAT_INT|VIF1_STAT_VSS|VIF1_STAT_VIS|VIF1_STAT_VFS) )
DevCon::Notice( "Reading from vif1 fifo when stalled" ); DevCon::Notice( "Reading from vif1 fifo when stalled" );
if (vif1Regs->stat & 0x800000) if (vif1Regs->stat & VIF1_STAT_FDR)
{ {
if (--psHu32(D1_QWC) == 0) if (--psHu32(D1_QWC) == 0)
vif1Regs->stat&= ~0x1f000000; vif1Regs->stat&= ~VIF1_STAT_FQC;
} }
//out[0] = psHu64(mem ); //out[0] = psHu64(mem );
@ -154,7 +154,7 @@ void __fastcall WriteFIFO_page_5(u32 mem, const mem128_t *value)
if(vif1Regs->stat & VIF1_STAT_FDR) if(vif1Regs->stat & VIF1_STAT_FDR)
DevCon::Notice("writing to fifo when fdr is set!"); DevCon::Notice("writing to fifo when fdr is set!");
if( vif1Regs->stat & (VIF1_STAT_INT|VIF1_STAT_VSS|VIF1_STAT_VIS|VIF1_STAT_VFS) ) if( vif1Regs->stat & (VIF1_STAT_INT | VIF1_STAT_VSS | VIF1_STAT_VIS | VIF1_STAT_VFS) )
DevCon::Notice("writing to vif1 fifo when stalled"); DevCon::Notice("writing to vif1 fifo when stalled");
vif1ch->qwc += 1; vif1ch->qwc += 1;

81
pcsx2/Hw.h
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@ -311,51 +311,44 @@ enum DMACIrqs
DMAC_ERROR = 15, DMAC_ERROR = 15,
}; };
#define VIF0_STAT_VPS_W (1) enum vif0_stat_flags
#define VIF0_STAT_VPS_D (2) {
#define VIF0_STAT_VPS_T (3) VIF0_STAT_VPS_W = (1),
#define VIF0_STAT_VPS (3) VIF0_STAT_VPS_D = (2),
#define VIF0_STAT_VEW (1<<2) VIF0_STAT_VPS_T = (3),
#define VIF0_STAT_MRK (1<<6) VIF0_STAT_VPS = (3),
#define VIF0_STAT_DBF (1<<7) VIF0_STAT_VEW = (1<<2),
#define VIF0_STAT_VSS (1<<8) VIF0_STAT_MRK = (1<<6),
#define VIF0_STAT_VFS (1<<9) VIF0_STAT_DBF = (1<<7),
#define VIF0_STAT_VIS (1<<10) VIF0_STAT_VSS = (1<<8),
#define VIF0_STAT_INT (1<<11) VIF0_STAT_VFS = (1<<9),
#define VIF0_STAT_ER0 (1<<12) VIF0_STAT_VIS = (1<<10),
#define VIF0_STAT_ER1 (1<<13) VIF0_STAT_INT = (1<<11),
VIF0_STAT_ER0 = (1<<12),
VIF0_STAT_ER1 = (1<<13),
VIF0_STAT_FQC = (15<<24)
};
#define VIF1_STAT_VPS_W (1) enum vif1_stat_flags
#define VIF1_STAT_VPS_D (2) {
#define VIF1_STAT_VPS_T (3) VIF1_STAT_VPS_W = (1),
#define VIF1_STAT_VPS (3) VIF1_STAT_VPS_D = (2),
#define VIF1_STAT_VEW (1<<2) VIF1_STAT_VPS_T = (3),
#define VIF1_STAT_VGW (1<<3) VIF1_STAT_VPS = (3),
#define VIF1_STAT_MRK (1<<6) VIF1_STAT_VEW = (1<<2),
#define VIF1_STAT_DBF (1<<7) VIF1_STAT_VGW = (1<<3),
#define VIF1_STAT_VSS (1<<8) VIF1_STAT_MRK = (1<<6),
#define VIF1_STAT_VFS (1<<9) VIF1_STAT_DBF = (1<<7),
#define VIF1_STAT_VIS (1<<10) VIF1_STAT_VSS = (1<<8),
#define VIF1_STAT_INT (1<<11) VIF1_STAT_VFS = (1<<9),
#define VIF1_STAT_ER0 (1<<12) VIF1_STAT_VIS = (1<<10),
#define VIF1_STAT_ER1 (1<<13) VIF1_STAT_INT = (1<<11),
#define VIF1_STAT_FDR (1<<23) VIF1_STAT_ER0 = (1<<12),
VIF1_STAT_ER1 = (1<<13),
#define VIF_STAT_VPS_W (1) VIF1_STAT_FDR = (1<<23),
#define VIF_STAT_VPS_D (2) VIF1_STAT_FQC = (31<<24)
#define VIF_STAT_VPS_T (3) };
#define VIF_STAT_VPS (3)
#define VIF_STAT_VEW (1<<2)
#define VIF_STAT_VGW (1<<3)
#define VIF_STAT_MRK (1<<6)
#define VIF_STAT_DBF (1<<7)
#define VIF_STAT_VSS (1<<8)
#define VIF_STAT_VFS (1<<9)
#define VIF_STAT_VIS (1<<10)
#define VIF_STAT_INT (1<<11)
#define VIF_STAT_ER0 (1<<12)
#define VIF_STAT_ER1 (1<<13)
#define VIF_STAT_FDR (1<<23)
//GIF_STAT //GIF_STAT

2
pcsx2/IPU/IPU.h
View File

@ -104,7 +104,7 @@ union tIPU_CTRL {
u32 AS : 1; // Alternate scan u32 AS : 1; // Alternate scan
u32 IVF : 1; // Intra VLC format u32 IVF : 1; // Intra VLC format
u32 QST : 1; // Q scale step u32 QST : 1; // Q scale step
u32 MP1 : 1; // MPEG1 bit strea u32 MP1 : 1; // MPEG1 bit stream
u32 PCT : 3; // Picture Type u32 PCT : 3; // Picture Type
u32 resv1 : 3; u32 resv1 : 3;
u32 RST : 1; // Reset u32 RST : 1; // Reset

22
pcsx2/Tags.h
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@ -22,8 +22,6 @@
// Actually, looks like I didn't need templates after all... :) // Actually, looks like I didn't need templates after all... :)
#include "Vif.h"
enum mfd_type enum mfd_type
{ {
NO_MFD, NO_MFD,
@ -291,26 +289,6 @@ namespace QWC
} }
} }
enum vif_errors
{
VIF_ERR_MII = 0x1,
VIF_ERR_ME0 = 0x2,
VIF_ERR_ME1 = 0x4
};
// Masks or unmasks errors
namespace VIF_ERR
{
// If true, interrupts by the i bit of Vifcode are masked.
static __forceinline bool MII(VIFregisters *tag) { return !!(tag->err & VIF_ERR_MII); }
// If true, DMAtag Mismatch errors are masked. (We never check for this?)
static __forceinline bool ME0(VIFregisters *tag) { return !!(tag->err & VIF_ERR_ME0); }
// If true, VifCode errors are masked.
static __forceinline bool ME1(VIFregisters *tag) { return !!(tag->err & VIF_ERR_ME1); }
}
namespace D_CTRL namespace D_CTRL
{ {
static __forceinline bool DMAE() { return !!(psHu32(DMAC_CTRL) & CTRL_DMAE); } static __forceinline bool DMAE() { return !!(psHu32(DMAC_CTRL) & CTRL_DMAE); }

2
pcsx2/VU0micro.cpp
View File

@ -43,7 +43,7 @@ void vu0ResetRegs()
{ {
VU0.VI[REG_VPU_STAT].UL &= ~0xff; // stop vu0 VU0.VI[REG_VPU_STAT].UL &= ~0xff; // stop vu0
VU0.VI[REG_FBRST].UL &= ~0xff; // stop vu0 VU0.VI[REG_FBRST].UL &= ~0xff; // stop vu0
vif0Regs->stat &= ~4; vif0Regs->stat &= ~VIF0_STAT_VEW;
} }
void VU0MI_XGKICK() { void VU0MI_XGKICK() {

2
pcsx2/VU0microInterp.cpp
View File

@ -169,7 +169,7 @@ static void _vu0Exec(VURegs* VU)
if( VU->ebit-- == 1 ) { if( VU->ebit-- == 1 ) {
_vuFlushAll(VU); _vuFlushAll(VU);
VU0.VI[REG_VPU_STAT].UL&= ~0x1; /* E flag */ VU0.VI[REG_VPU_STAT].UL&= ~0x1; /* E flag */
vif0Regs->stat&= ~0x4; vif0Regs->stat&= ~VIF0_STAT_VEW;
} }
} }
} }

4
pcsx2/VU1micro.cpp
View File

@ -43,7 +43,7 @@ void vu1ResetRegs()
{ {
VU0.VI[REG_VPU_STAT].UL &= ~0xff00; // stop vu1 VU0.VI[REG_VPU_STAT].UL &= ~0xff00; // stop vu1
VU0.VI[REG_FBRST].UL &= ~0xff00; // stop vu1 VU0.VI[REG_FBRST].UL &= ~0xff00; // stop vu1
vif1Regs->stat &= ~4; vif1Regs->stat &= ~VIF1_STAT_VEW;
} }
static int count; static int count;
@ -61,7 +61,7 @@ void vu1ExecMicro(u32 addr)
VU0.VI[REG_VPU_STAT].UL|= 0x100; VU0.VI[REG_VPU_STAT].UL|= 0x100;
VU0.VI[REG_VPU_STAT].UL&= ~0x7E000; VU0.VI[REG_VPU_STAT].UL&= ~0x7E000;
vif1Regs->stat|= 0x4; vif1Regs->stat|= VIF1_STAT_VEW;
if (addr != -1) VU1.VI[REG_TPC].UL = addr; if (addr != -1) VU1.VI[REG_TPC].UL = addr;
_vuExecMicroDebug(VU1); _vuExecMicroDebug(VU1);

2
pcsx2/VU1microInterp.cpp
View File

@ -162,7 +162,7 @@ static void _vu1Exec(VURegs* VU)
if( VU->ebit-- == 1 ) { if( VU->ebit-- == 1 ) {
_vuFlushAll(VU); _vuFlushAll(VU);
VU0.VI[REG_VPU_STAT].UL&= ~0x100; VU0.VI[REG_VPU_STAT].UL&= ~0x100;
vif1Regs->stat&= ~0x4; vif1Regs->stat&= ~VIF1_STAT_VEW;
} }
} }
} }

6
pcsx2/Vif.cpp
View File

@ -576,7 +576,7 @@ void vifMFIFOInterrupt()
// Console::WriteLn("Empty 1"); // Console::WriteLn("Empty 1");
vifqwc = 0; vifqwc = 0;
vif1.inprogress |= 0x10; vif1.inprogress |= 0x10;
vif1Regs->stat &= ~0x1F000000; // FQC=0 vif1Regs->stat &= ~VIF1_STAT_FQC; // FQC=0
hwDmacIrq(DMAC_14); hwDmacIrq(DMAC_14);
return; return;
} }
@ -600,7 +600,7 @@ void vifMFIFOInterrupt()
{ {
//Console::WriteLn("Empty 2"); //Console::WriteLn("Empty 2");
//vif1.inprogress |= 0x10; //vif1.inprogress |= 0x10;
vif1Regs->stat &= ~0x1F000000; // FQC=0 vif1Regs->stat &= ~VIF1_STAT_FQC; // FQC=0
hwDmacIrq(DMAC_14); hwDmacIrq(DMAC_14);
}*/ }*/
@ -610,6 +610,6 @@ void vifMFIFOInterrupt()
hwDmacIrq(DMAC_VIF1); hwDmacIrq(DMAC_VIF1);
VIF_LOG("vif mfifo dma end"); VIF_LOG("vif mfifo dma end");
vif1Regs->stat &= ~0x1F000000; // FQC=0 vif1Regs->stat &= ~VIF1_STAT_FQC; // FQC=0
} }

20
pcsx2/Vif.h
View File

@ -78,6 +78,26 @@ struct VIFregisters {
u32 addr; u32 addr;
}; };
enum vif_errors
{
VIF_ERR_MII = 0x1,
VIF_ERR_ME0 = 0x2,
VIF_ERR_ME1 = 0x4
};
// Masks or unmasks errors
namespace VIF_ERR
{
// If true, interrupts by the i bit of Vifcode are masked.
static __forceinline bool MII(VIFregisters *tag) { return !!(tag->err & VIF_ERR_MII); }
// If true, DMAtag Mismatch errors are masked. (We never check for this?)
static __forceinline bool ME0(VIFregisters *tag) { return !!(tag->err & VIF_ERR_ME0); }
// If true, VifCode errors are masked.
static __forceinline bool ME1(VIFregisters *tag) { return !!(tag->err & VIF_ERR_ME1); }
}
extern "C" extern "C"
{ {
// these use cdecl for Asm code references. // these use cdecl for Asm code references.

34
pcsx2/VifDma.cpp
View File

@ -1225,7 +1225,7 @@ static void Vif0CMDNull() // invalid opcode
if (!(VIF_ERR::ME1(vif0Regs))) //Ignore vifcode and tag mismatch error if (!(VIF_ERR::ME1(vif0Regs))) //Ignore vifcode and tag mismatch error
{ {
Console::WriteLn("UNKNOWN VifCmd: %x", params vif0.cmd); Console::WriteLn("UNKNOWN VifCmd: %x", params vif0.cmd);
vif0Regs->stat |= 1 << 13; vif0Regs->stat |= VIF0_STAT_ER1;
vif0.irq++; vif0.irq++;
} }
vif0.cmd &= ~0x7f; vif0.cmd &= ~0x7f;
@ -1277,7 +1277,7 @@ int VIF0transfer(u32 *data, int size, int istag)
if (!(VIF_ERR::ME1(vif0Regs))) //Ignore vifcode and tag mismatch error if (!(VIF_ERR::ME1(vif0Regs))) //Ignore vifcode and tag mismatch error
{ {
Console::WriteLn("UNKNOWN VifCmd: %x", params vif0.cmd); Console::WriteLn("UNKNOWN VifCmd: %x", params vif0.cmd);
vif0Regs->stat |= 1 << 13; vif0Regs->stat |= VIF0_STAT_ER1;
vif0.irq++; vif0.irq++;
} }
vif0.cmd = 0; vif0.cmd = 0;
@ -1425,7 +1425,7 @@ void vif0Interrupt()
if (vif0Regs->stat & (VIF0_STAT_VSS | VIF0_STAT_VIS | VIF0_STAT_VFS)) if (vif0Regs->stat & (VIF0_STAT_VSS | VIF0_STAT_VIS | VIF0_STAT_VFS))
{ {
vif0Regs->stat &= ~0xF000000; // FQC=0 vif0Regs->stat &= ~VIF0_STAT_FQC; // FQC=0
CHCR::clearSTR(vif0ch); CHCR::clearSTR(vif0ch);
return; return;
} }
@ -1467,7 +1467,7 @@ void vif0Interrupt()
CHCR::clearSTR(vif0ch); CHCR::clearSTR(vif0ch);
hwDmacIrq(DMAC_VIF0); hwDmacIrq(DMAC_VIF0);
vif0Regs->stat &= ~0xF000000; // FQC=0 vif0Regs->stat &= ~VIF0_STAT_FQC; // FQC=0
} }
// Vif1 Data Transfer Table // Vif1 Data Transfer Table
@ -1559,10 +1559,10 @@ void vif0Write32(u32 mem, u32 value)
vif0ch->qwc = 0; //? vif0ch->qwc = 0; //?
cpuRegs.interrupt &= ~1; //Stop all vif0 DMA's cpuRegs.interrupt &= ~1; //Stop all vif0 DMA's
psHu64(VIF0_FIFO) = 0; psHu64(VIF0_FIFO) = 0;
psHu64(0x10004008) = 0; // VIF0_FIFO + 8 psHu64(VIF0_FIFO + 8) = 0; // VIF0_FIFO + 8
vif0.done = true; vif0.done = true;
vif0Regs->err = 0; vif0Regs->err = 0;
vif0Regs->stat &= ~(0xF000000 | VIF0_STAT_INT | VIF0_STAT_VSS | VIF0_STAT_VIS | VIF0_STAT_VFS | VIF0_STAT_VPS); // FQC=0 vif0Regs->stat &= ~(VIF0_STAT_FQC | VIF0_STAT_INT | VIF0_STAT_VSS | VIF0_STAT_VIS | VIF0_STAT_VFS | VIF0_STAT_VPS); // FQC=0
} }
if (value & 0x2) if (value & 0x2)
@ -1657,7 +1657,7 @@ void vif0Reset()
psHu64(VIF0_FIFO + 8) = 0; psHu64(VIF0_FIFO + 8) = 0;
vif0Regs->stat &= ~VIF0_STAT_VPS; vif0Regs->stat &= ~VIF0_STAT_VPS;
vif0.done = true; vif0.done = true;
vif0Regs->stat &= ~0xF000000; // FQC=0 vif0Regs->stat &= ~VIF0_STAT_FQC; // FQC=0
} }
void SaveState::vif0Freeze() void SaveState::vif0Freeze()
@ -2022,7 +2022,7 @@ static void Vif1CMDSTCycl() // STCYCL
static void Vif1CMDOffset() // OFFSET static void Vif1CMDOffset() // OFFSET
{ {
vif1Regs->ofst = vif1Regs->code & 0x3ff; vif1Regs->ofst = vif1Regs->code & 0x3ff;
vif1Regs->stat &= ~0x80; vif1Regs->stat &= ~VIF1_STAT_DBF;
vif1Regs->tops = vif1Regs->base; vif1Regs->tops = vif1Regs->base;
vif1.cmd &= ~0x7f; vif1.cmd &= ~0x7f;
} }
@ -2160,7 +2160,7 @@ static void Vif1CMDNull() // invalid opcode
if (!(VIF_ERR::ME1(vif1Regs))) //Ignore vifcode and tag mismatch error if (!(VIF_ERR::ME1(vif1Regs))) //Ignore vifcode and tag mismatch error
{ {
Console::WriteLn("UNKNOWN VifCmd: %x\n", params vif1.cmd); Console::WriteLn("UNKNOWN VifCmd: %x\n", params vif1.cmd);
vif1Regs->stat |= 1 << 13; vif1Regs->stat |= VIF1_STAT_ER1;
vif1.irq++; vif1.irq++;
} }
vif1.cmd = 0; vif1.cmd = 0;
@ -2258,7 +2258,7 @@ int VIF1transfer(u32 *data, int size, int istag)
if (!(VIF_ERR::ME1(vif1Regs))) //Ignore vifcode and tag mismatch error if (!(VIF_ERR::ME1(vif1Regs))) //Ignore vifcode and tag mismatch error
{ {
Console::WriteLn("UNKNOWN VifCmd: %x", params vif1.cmd); Console::WriteLn("UNKNOWN VifCmd: %x", params vif1.cmd);
vif1Regs->stat |= 1 << 13; vif1Regs->stat |= VIF1_STAT_ER1;
vif1.irq++; vif1.irq++;
} }
vif1.cmd = 0; vif1.cmd = 0;
@ -2346,7 +2346,7 @@ void vif1TransferFromMemory()
Console::WriteLn("Vif1 Tag BUSERR"); Console::WriteLn("Vif1 Tag BUSERR");
psHu32(DMAC_STAT) |= DMAC_STAT_BEIS; //If yes, set BEIS (BUSERR) in DMAC_STAT register psHu32(DMAC_STAT) |= DMAC_STAT_BEIS; //If yes, set BEIS (BUSERR) in DMAC_STAT register
vif1.done = true; vif1.done = true;
vif1Regs->stat &= ~0x1f000000; vif1Regs->stat &= ~VIF1_STAT_FQC;
vif1ch->qwc = 0; vif1ch->qwc = 0;
CPU_INT(1, 0); CPU_INT(1, 0);
@ -2532,7 +2532,7 @@ __forceinline void vif1Interrupt()
--vif1.irq; --vif1.irq;
if (vif1Regs->stat & (VIF1_STAT_VSS | VIF1_STAT_VIS | VIF1_STAT_VFS)) if (vif1Regs->stat & (VIF1_STAT_VSS | VIF1_STAT_VIS | VIF1_STAT_VFS))
{ {
vif1Regs->stat &= ~0x1F000000; // FQC=0 vif1Regs->stat &= ~VIF1_STAT_FQC; // FQC=0
// One game doesnt like vif stalling at end, cant remember what. Spiderman isnt keen on it tho // One game doesnt like vif stalling at end, cant remember what. Spiderman isnt keen on it tho
CHCR::clearSTR(vif1ch); CHCR::clearSTR(vif1ch);
@ -2677,7 +2677,7 @@ void vif1Write32(u32 mem, u32 value)
vif1Regs->err = 0; vif1Regs->err = 0;
vif1.inprogress = 0; vif1.inprogress = 0;
vif1Regs->stat &= ~(0x1F800000 | VIF1_STAT_INT | VIF1_STAT_VSS | VIF1_STAT_VIS | VIF1_STAT_VFS | VIF1_STAT_VPS); // FQC=0 vif1Regs->stat &= ~(VIF1_STAT_FQC | VIF1_STAT_FDR | VIF1_STAT_INT | VIF1_STAT_VSS | VIF1_STAT_VIS | VIF1_STAT_VFS | VIF1_STAT_VPS); // FQC=0
} }
if (value & 0x2) if (value & 0x2)
@ -2762,14 +2762,14 @@ void vif1Write32(u32 mem, u32 value)
vif1Regs->stat = (vif1Regs->stat & ~VIF1_STAT_FDR) | (value & VIF1_STAT_FDR); vif1Regs->stat = (vif1Regs->stat & ~VIF1_STAT_FDR) | (value & VIF1_STAT_FDR);
if (vif1Regs->stat & VIF1_STAT_FDR) if (vif1Regs->stat & VIF1_STAT_FDR)
{ {
vif1Regs->stat |= 0x01000000; // FQC=1 - hack but it checks this is true before tranfer? (fatal frame) vif1Regs->stat |= 0x01000000; // FQC=1 - hack but it checks this is true before transfer? (fatal frame)
} }
else else
{ {
vif1ch->qwc = 0; vif1ch->qwc = 0;
vif1.vifstalled = false; vif1.vifstalled = false;
vif1.done = true; vif1.done = true;
vif1Regs->stat &= ~0x1F000000; // FQC=0 vif1Regs->stat &= ~VIF1_STAT_FQC; // FQC=0
} }
break; break;
@ -2809,11 +2809,11 @@ void vif1Reset()
memzero_obj(*vif1Regs); memzero_obj(*vif1Regs);
SetNewMask(g_vif1Masks, g_vif1HasMask3, 0, 0xffffffff); SetNewMask(g_vif1Masks, g_vif1HasMask3, 0, 0xffffffff);
psHu64(VIF1_FIFO) = 0; psHu64(VIF1_FIFO) = 0;
psHu64(0x10005008) = 0; // VIF1_FIFO + 8 psHu64(VIF1_FIFO + 8) = 0;
vif1Regs->stat &= ~VIF1_STAT_VPS; vif1Regs->stat &= ~VIF1_STAT_VPS;
vif1.done = true; vif1.done = true;
cpuRegs.interrupt &= ~((1 << 1) | (1 << 10)); //Stop all vif1 DMA's cpuRegs.interrupt &= ~((1 << 1) | (1 << 10)); //Stop all vif1 DMA's
vif1Regs->stat &= ~0x1F000000; // FQC=0 vif1Regs->stat &= ~VIF1_STAT_FQC; // FQC=0
} }
void SaveState::vif1Freeze() void SaveState::vif1Freeze()

28
plugins/GSnull/GifTransfer.h
View File

@ -30,10 +30,10 @@
enum GIF_FLG enum GIF_FLG
{ {
GIF_FLG_PACKED = 0, GIF_FLG_PACKED = 0,
GIF_FLG_REGLIST = 1, GIF_FLG_REGLIST = 1,
GIF_FLG_IMAGE = 2, GIF_FLG_IMAGE = 2,
GIF_FLG_IMAGE2 = 3 GIF_FLG_IMAGE2 = 3
}; };
enum GIF_PATH enum GIF_PATH
@ -45,20 +45,20 @@ enum GIF_PATH
enum GIF_REG enum GIF_REG
{ {
GIF_REG_PRIM = 0x00, GIF_REG_PRIM = 0x00,
GIF_REG_RGBA = 0x01, GIF_REG_RGBA = 0x01,
GIF_REG_STQ = 0x02, GIF_REG_STQ = 0x02,
GIF_REG_UV = 0x03, GIF_REG_UV = 0x03,
GIF_REG_XYZF2 = 0x04, GIF_REG_XYZF2 = 0x04,
GIF_REG_XYZ2 = 0x05, GIF_REG_XYZ2 = 0x05,
GIF_REG_TEX0_1 = 0x06, GIF_REG_TEX0_1 = 0x06,
GIF_REG_TEX0_2 = 0x07, GIF_REG_TEX0_2 = 0x07,
GIF_REG_CLAMP_1 = 0x08, GIF_REG_CLAMP_1 = 0x08,
GIF_REG_CLAMP_2 = 0x09, GIF_REG_CLAMP_2 = 0x09,
GIF_REG_FOG = 0x0a, GIF_REG_FOG = 0x0a,
GIF_REG_XYZF3 = 0x0c, GIF_REG_XYZF3 = 0x0c,
GIF_REG_XYZ3 = 0x0d, GIF_REG_XYZ3 = 0x0d,
GIF_REG_A_D = 0x0e, GIF_REG_A_D = 0x0e,
GIF_REG_NOP = 0x0f, GIF_REG_NOP = 0x0f,
}; };

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plugins/GSnull/Registers.h Normal file
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/* GSnull
* Copyright (C) 2004-2009 PCSX2 Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
/* GSnull
* Copyright (C) 2004-2009 PCSX2 Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
struct GIF_CTRL
{
u32 RST:1, // GIF reset
u32 reserved:2,
u32 PSE:1, // Temporary Transfer Stop
u32 reserved2:28
};
struct GIF_MODE
{
u32 M3R:1,
u32 reserved:1,
u32 IMT:1,
u32 reserved2:29
};
struct GIF_STAT
{
u32 M3R:1,
u32 M3P:1,
u32 IMT:1,
u32 PSE:1,
u32 reserved:1,
u32 IP3:1,
u32 P3Q:1,
u32 P2Q:1,
u32 P1Q:1,
u32 OPH:1,
u32 APATH:2,
u32 DIR:1,
u32 reserved2:11,
u32 FQC:5,
y32 reserved3:3
};
struct GIF_CNT
{
u32 LOOPCNT:15,
u32 reserved:1,
u32 REGCNT:4,
u32 VUADDR:10,
u32 rese3rved2:2
};
struct GIF_P3CNT
{
u32 PS3CNT:15,
u32 reserved:17
};
struct GIF_P3TAG
{
u32 LOOPCNT:15,
u32 EOP:1,
u32 reserved:16
};