mirror of https://github.com/PCSX2/pcsx2.git
Modified the GIF and SPR in my wierd backward dma way :P should resolve problems with the Avatar games, 24 videos and hopefully anything else which has broken due to recent changes.
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@604 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
refraction
parent
8d86297533
commit
441b70239a
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@ -55,10 +55,10 @@ __forceinline void gsInterrupt() {
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// re-reaise the IRQ as part of the mysterious Path3fix.
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// fixme - this hack *should* have the gs_irq raised from the VIF, I think. It would be
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// more efficient and more correct. (air)
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if (!(vif1Regs->mskpath3 && (vif1ch->chcr & 0x100)) || (psHu32(GIF_MODE) & 0x1))
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CPU_INT( 2, 64 );
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/*if (!(vif1Regs->mskpath3 && (vif1ch->chcr & 0x100)) || (psHu32(GIF_MODE) & 0x1))
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CPU_INT( 2, 64 );*/
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#endif
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return;
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if(gspath3done == 0) return;
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}
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gspath3done = 0;
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@ -254,6 +254,7 @@ void GIFdma()
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FreezeXMMRegs(0);
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FreezeMMXRegs(0);
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if(gif->qwc == 0 && (gif->chcr & 0xc) == 0) gspath3done = 1;
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return;
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}
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else {
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// Chain Mode
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@ -311,9 +312,18 @@ void GIFdma()
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}
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}
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}
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prevcycles = 0;
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if (!(vif1Regs->mskpath3 || (psHu32(GIF_MODE) & 0x1))) {
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CPU_INT(2, gscycles);
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if(gspath3done == 0){
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ptag = (u32*)dmaGetAddr(gif->tadr); //Set memory pointer to TADR
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gif->qwc = (u16)ptag[0]; //QWC set to lower 16bits of the tag
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gif->chcr = ( gif->chcr & 0xFFFF ) | ( (*ptag) & 0xFFFF0000 ); //Transfer upper part of tag to CHCR bits 31-15
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CPU_INT(2, gif->qwc * BIAS);
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gif->qwc = 0;
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return;
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}
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//CPU_INT(2, gif->qwc * BIAS);
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gscycles = 0;
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}
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}
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@ -323,18 +333,46 @@ void dmaGIF() {
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// CPU_INT(2, 48); //Wait time for the buffer to fill, fixes some timing problems in path 3 masking
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//} //It takes the time of 24 QW for the BUS to become ready - The Punisher, And1 Streetball
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//else
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gspath3done = 0; // For some reason this doesnt clear? So when the system starts the thread, we will clear it :)
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if(gif->qwc > 0 && (gif->chcr & 0x4) == 0x4)
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gspath3done = 1; //Halflife sets a QWC amount in chain mode, no tadr set.
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if ((psHu32(DMAC_CTRL) & 0xC) == 0xC ) { // GIF MFIFO
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//SysPrintf("GIF MFIFO\n");
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SysPrintf("GIF MFIFO\n");
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gifMFIFOInterrupt();
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return;
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}
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GIFdma();
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gspath3done = 0; // For some reason this doesnt clear? So when the system starts the thread, we will clear it :)
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GSCSRr &= ~0xC000; //Clear FIFO stuff
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GSCSRr |= 0x8000; //FIFO full
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//psHu32(GIF_STAT)|= 0xE00; // OPH=1 | APATH=3
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psHu32(GIF_STAT)|= 0x10000000; // FQC=31, hack ;)
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if ((gif->chcr & 0xc) != 0 && gif->qwc == 0){
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u32 *ptag;
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ptag = (u32*)dmaGetAddr(gif->tadr);
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gif->qwc = (u16)ptag[0]; //QWC set to lower 16bits of the tag
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gif->chcr = ( gif->chcr & 0xFFFF ) | ( (*ptag) & 0xFFFF0000 ); //Transfer upper part of tag to CHCR bits 31-15
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CPU_INT(2, gif->qwc * BIAS);
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gif->qwc = 0;
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return;
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}
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if(gif->qwc > 0 && (gif->chcr & 0x4) == 0x4) {
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//SysPrintf("HL Hack\n");
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gspath3done = 1; //Halflife sets a QWC amount in chain mode, no tadr set.
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CPU_INT(2, gif->qwc * BIAS);
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GIFdma();
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return;
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}
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//GIFdma();
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CPU_INT(2, gif->qwc * BIAS);
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}
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#define spr0 ((DMACh*)&PS2MEM_HW[0xD000])
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@ -417,7 +455,7 @@ static __forceinline int mfifoGIFchain() {
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return 0;
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}
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int gifmfifoirq = 0;
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void mfifoGIFtransfer(int qwc) {
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u32 *ptag;
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@ -425,6 +463,8 @@ void mfifoGIFtransfer(int qwc) {
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u32 temp = 0;
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mfifocycles = 0;
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gifmfifoirq = 0;
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if(qwc > 0 ) {
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gifqwc += qwc;
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if(!(gif->chcr & 0x100))return;
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@ -432,6 +472,8 @@ void mfifoGIFtransfer(int qwc) {
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}
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SPR_LOG("mfifoGIFtransfer %x madr %x, tadr %x\n", gif->chcr, gif->madr, gif->tadr);
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if(gif->qwc == 0){
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if(gif->tadr == spr0->madr) {
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#ifdef PCSX2_DEVBUILD
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@ -489,6 +531,7 @@ void mfifoGIFtransfer(int qwc) {
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if ((gif->chcr & 0x80) && (ptag[0] >> 31)) {
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SPR_LOG("dmaIrq Set\n");
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gifstate = GIF_STATE_DONE;
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gifmfifoirq = 1;
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}
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}
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FreezeXMMRegs(1);
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@ -528,7 +571,7 @@ void gifMFIFOInterrupt()
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}
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#endif
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//if(gifqwc > 0)SysPrintf("GIF MFIFO ending with stuff in it %x\n", gifqwc);
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gifqwc = 0;
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if( gifmfifoirq == 0) gifqwc = 0;
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gifstate = GIF_STATE_EMPTY;
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gif->chcr &= ~0x100;
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hwDmacIrq(DMAC_GIF);
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@ -26,6 +26,9 @@
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#define spr0 ((DMACh*)&PS2MEM_HW[0xD000])
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#define spr1 ((DMACh*)&PS2MEM_HW[0xD400])
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int spr0finished = 0;
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int spr1finished = 0;
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u32 mfifotransferred = 0;
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void sprInit() {
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}
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@ -74,6 +77,7 @@ int _SPR0chain() {
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hwMFIFOWrite(spr0->madr, (u8*)&PS2MEM_SCRATCH[spr0->sadr & 0x3fff], spr0->qwc << 4);
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spr0->madr += spr0->qwc << 4;
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spr0->madr = psHu32(DMAC_RBOR) + (spr0->madr & psHu32(DMAC_RBSR));
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mfifotransferred += spr0->qwc;
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} else {
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memcpy_fast((u8*)pMem, &PS2MEM_SCRATCH[spr0->sadr & 0x3fff], spr0->qwc << 4);
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Cpu->Clear(spr0->madr, spr0->qwc<<2);
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@ -110,6 +114,7 @@ void _SPR0interleave() {
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if ((psHu32(DMAC_CTRL) & 0xC) == 0xC || // GIF MFIFO
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(psHu32(DMAC_CTRL) & 0xC) == 0x8) { // VIF1 MFIFO
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hwMFIFOWrite(spr0->madr, (u8*)&PS2MEM_SCRATCH[spr0->sadr & 0x3fff], spr0->qwc<<4);
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mfifotransferred += spr0->qwc;
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} else {
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Cpu->Clear(spr0->madr, spr0->qwc<<2);
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// clear VU mem also!
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@ -122,6 +127,7 @@ void _SPR0interleave() {
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}
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spr0->qwc = 0;
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spr0finished = 1;
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//CPU_INT(8, cycles);
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}
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@ -142,6 +148,7 @@ static __forceinline void _dmaSPR0() {
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int cycles = 0;
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SPR0chain();
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//CPU_INT(8, cycles);
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spr0finished = 1;
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return;
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} else if ((spr0->chcr & 0xc) == 0x4) {
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@ -153,12 +160,12 @@ static __forceinline void _dmaSPR0() {
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if(spr0->qwc > 0){
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SPR0chain();
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//CPU_INT(8, cycles);
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spr0finished = 1;
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return;
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}
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// Destination Chain Mode
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while (done == 0) { // Loop while Dn_CHCR.STR is 1
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//while (done == 0) { // Loop while Dn_CHCR.STR is 1
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ptag = (u32*)&PS2MEM_SCRATCH[spr0->sadr & 0x3fff];
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spr0->sadr+= 16;
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@ -171,7 +178,7 @@ static __forceinline void _dmaSPR0() {
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spr0->qwc = (u16)ptag[0]; //QWC set to lower 16bits of the tag
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spr0->madr = ptag[1]; //MADR = ADDR field
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SPR_LOG("dmaChain %8.8x_%8.8x size=%d, id=%d, addr=%lx\n",
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SPR_LOG("spr0 dmaChain %8.8x_%8.8x size=%d, id=%d, addr=%lx spr=%lx\n",
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ptag[1], ptag[0], spr0->qwc, id, spr0->madr);
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if ((psHu32(DMAC_CTRL) & 0x30) == 0x20) { // STS == fromSPR
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@ -184,6 +191,7 @@ static __forceinline void _dmaSPR0() {
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break;
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case 1: // CNT - Transfer QWC following the tag.
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done = 0;
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break;
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case 7: // End - Transfer QWC following the tag
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@ -195,7 +203,7 @@ static __forceinline void _dmaSPR0() {
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//SysPrintf("SPR0 TIE\n");
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done = 1;
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spr0->qwc = 0;
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break;
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//break;
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}
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@ -206,7 +214,17 @@ static __forceinline void _dmaSPR0() {
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hwDmacIrq(8);
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return;
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}*/
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//}
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spr0finished = done;
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if(done == 0) {
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ptag = (u32*)&PS2MEM_SCRATCH[spr0->sadr & 0x3fff]; //Set memory pointer to SADR
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spr0->qwc = (u16)ptag[0]; //QWC set to lower 16bits of the tag
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CPU_INT(8, spr0->qwc / BIAS);
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spr0->qwc = 0;
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return;
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}
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SPR_LOG("spr0 dmaChain complete %8.8x_%8.8x size=%d, id=%d, addr=%lx spr=%lx\n",
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ptag[1], ptag[0], spr0->qwc, id, spr0->madr);
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//CPU_INT(8, cycles);
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} else { // Interleave Mode
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_SPR0interleave();
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@ -221,7 +239,7 @@ extern void mfifoGIFtransfer(int);
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void SPRFROMinterrupt()
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{
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int qwc = spr0->qwc;
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//int qwc = spr0->qwc;
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_dmaSPR0();
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@ -229,15 +247,18 @@ void SPRFROMinterrupt()
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if((spr0->madr & ~psHu32(DMAC_RBSR)) != psHu32(DMAC_RBOR)) SysPrintf("GIF MFIFO Write outside MFIFO area\n");
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spr0->madr = psHu32(DMAC_RBOR) + (spr0->madr & psHu32(DMAC_RBSR));
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//SysPrintf("mfifoGIFtransfer %x madr %x, tadr %x\n", gif->chcr, gif->madr, gif->tadr);
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mfifoGIFtransfer(qwc);
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mfifoGIFtransfer(mfifotransferred);
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mfifotransferred = 0;
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} else
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if ((psHu32(DMAC_CTRL) & 0xC) == 0x8) { // VIF1 MFIFO
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if((spr0->madr & ~psHu32(DMAC_RBSR)) != psHu32(DMAC_RBOR)) SysPrintf("VIF MFIFO Write outside MFIFO area\n");
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spr0->madr = psHu32(DMAC_RBOR) + (spr0->madr & psHu32(DMAC_RBSR));
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//SysPrintf("mfifoVIF1transfer %x madr %x, tadr %x\n", vif1ch->chcr, vif1ch->madr, vif1ch->tadr);
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//vifqwc+= qwc;
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mfifoVIF1transfer(qwc);
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mfifoVIF1transfer(mfifotransferred);
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mfifotransferred = 0;
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}
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if(spr0finished == 0) return;
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spr0->chcr&= ~0x100;
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hwDmacIrq(8);
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}
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@ -249,10 +270,18 @@ void dmaSPR0() { // fromSPR
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SPR_LOG("dmaSPR0 chcr = %lx, madr = %lx, qwc = %lx, sadr = %lx\n",
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spr0->chcr, spr0->madr, spr0->qwc, spr0->sadr);
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if ((spr0->chcr & 0xc) == 0x4){
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u32 *ptag;
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ptag = (u32*)&PS2MEM_SCRATCH[spr0->sadr & 0x3fff]; //Set memory pointer to SADR
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spr0->qwc = (u16)ptag[0]; //QWC set to lower 16bits of the tag
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CPU_INT(8, spr0->qwc / BIAS);
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spr0->qwc = 0;
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return;
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}
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// COMPLETE HACK!!! For now at least.. FFX Videos dont rely on interrupts or reading DMA values
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// It merely assumes that the last one has finished then starts another one (broke with the DMA fix)
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// This "shouldn't" cause any problems as SPR is generally faster than the other DMAS anyway. (Refraction)
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CPU_INT(8, spr0->qwc / 2);
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CPU_INT(8, spr0->qwc / BIAS);
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@ -310,6 +339,7 @@ void _SPR1interleave() {
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}
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spr1->qwc = 0;
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spr1finished = 1;
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//CPU_INT(9, cycles);
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}
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@ -320,31 +350,35 @@ void _dmaSPR1() { // toSPR work function
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//if(spr1->qwc == 0 && (spr1->chcr & 0xc) == 1) spr1->qwc = 0xffff;
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// Transfer Dn_QWC from Dn_MADR to SPR1
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SPR1chain();
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spr1finished = 1;
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//CPU_INT(9, cycles);
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return;
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} else if ((spr1->chcr & 0xc) == 0x4){
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} else
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if ((spr1->chcr & 0xc) == 0x4){
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int cycles = 0;
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u32 *ptag;
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int id, done=0;
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if(spr1->qwc > 0){
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//if(spr1->qwc == 0 && (spr1->chcr & 0xc) == 1) spr1->qwc = 0xffff;
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// Transfer Dn_QWC from Dn_MADR to SPR1
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SPR1chain();
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//CPU_INT(9, cycles);
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return;
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}
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if(spr1->qwc > 0){
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//if(spr1->qwc == 0 && (spr1->chcr & 0xc) == 1) spr1->qwc = 0xffff;
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// Transfer Dn_QWC from Dn_MADR to SPR1
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SPR1chain();
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spr1finished = 1;
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//CPU_INT(9, cycles);
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return;
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}
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// Chain Mode
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while (done == 0) { // Loop while Dn_CHCR.STR is 1
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// while (done == 0) { // Loop while Dn_CHCR.STR is 1
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ptag = (u32*)dmaGetAddr(spr1->tadr); //Set memory pointer to TADR
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if (ptag == NULL) { //Is ptag empty?
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SysPrintf("SPR1 Tag BUSERR\n");
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spr1->chcr = ( spr1->chcr & 0xFFFF ) | ( (*ptag) & 0xFFFF0000 ); //Transfer upper part of tag to CHCR bits 31-15
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psHu32(DMAC_STAT)|= 1<<15; //If yes, set BEIS (BUSERR) in DMAC_STAT register
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done = 1;
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break;
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spr1finished = done;
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return;
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}
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spr1->chcr = ( spr1->chcr & 0xFFFF ) | ( (*ptag) & 0xFFFF0000 ); //Transfer upper part of tag to CHCR bits 31-15
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@ -358,7 +392,7 @@ void _dmaSPR1() { // toSPR work function
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SPR1transfer(ptag, 4); //Transfer Tag
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}
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SPR_LOG("dmaChain %8.8x_%8.8x size=%d, id=%d, addr=%lx\n",
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SPR_LOG("spr1 dmaChain %8.8x_%8.8x size=%d, id=%d, addr=%lx\n",
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ptag[1], ptag[0], spr1->qwc, id, spr1->madr);
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done = hwDmacSrcChain(spr1, id);
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@ -369,9 +403,17 @@ void _dmaSPR1() { // toSPR work function
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//SysPrintf("SPR1 TIE\n");
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spr1->qwc = 0;
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break;
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done = 1;
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// break;
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}
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//}
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spr1finished = done;
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if(done == 0) {
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ptag = (u32*)dmaGetAddr(spr1->tadr); //Set memory pointer to TADR
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spr1->qwc = (u16)ptag[0]; //QWC set to lower 16bits of the tag
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CPU_INT(9, spr1->qwc / BIAS);
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spr1->qwc = 0;
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}
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}
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} else { // Interleave Mode
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_SPR1interleave();
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}
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@ -387,10 +429,18 @@ void dmaSPR1() { // toSPR
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spr1->tadr, spr1->sadr);
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#endif
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if ((spr1->chcr & 0xc) == 0x4){
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u32 *ptag;
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ptag = (u32*)dmaGetAddr(spr1->tadr); //Set memory pointer to TADR
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spr1->qwc = (u16)ptag[0]; //QWC set to lower 16bits of the tag
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CPU_INT(9, spr1->qwc / BIAS);
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spr1->qwc = 0;
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return;
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}
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// COMPLETE HACK!!! For now at least.. FFX Videos dont rely on interrupts or reading DMA values
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// It merely assumes that the last one has finished then starts another one (broke with the DMA fix)
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// This "shouldn't" cause any problems as SPR is generally faster than the other DMAS anyway. (Refraction)
|
||||
CPU_INT(9, spr1->qwc / 2);
|
||||
CPU_INT(9, spr1->qwc / BIAS);
|
||||
|
||||
|
||||
}
|
||||
|
|
@ -398,6 +448,7 @@ void dmaSPR1() { // toSPR
|
|||
void SPRTOinterrupt()
|
||||
{
|
||||
_dmaSPR1();
|
||||
if( spr1finished == 0 ) return;
|
||||
spr1->chcr &= ~0x100;
|
||||
hwDmacIrq(9);
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue