diff --git a/pcsx2/FiFo.cpp b/pcsx2/FiFo.cpp
index 52d271b204..f1ba67be8c 100644
--- a/pcsx2/FiFo.cpp
+++ b/pcsx2/FiFo.cpp
@@ -46,11 +46,9 @@ void __fastcall ReadFIFO_page_4(u32 mem, u64 *out)
 	jASSUME( (mem >= VIF0_FIFO) && (mem < VIF1_FIFO) );
 
 	VIF_LOG("ReadFIFO/VIF0 0x%08X", mem);
-	//out[0] = psHu64(mem  );
-	//out[1] = psHu64(mem+8);
-
-	out[0] = psHu64(0x4000);
-	out[1] = psHu64(0x4008);
+	
+	out[0] = psHu64(VIF0_FIFO);
+	out[1] = psHu64(VIF0_FIFO + 8);
 }
 
 void __fastcall ReadFIFO_page_5(u32 mem, u64 *out)
@@ -59,7 +57,7 @@ void __fastcall ReadFIFO_page_5(u32 mem, u64 *out)
 
 	VIF_LOG("ReadFIFO/VIF1, addr=0x%08X", mem);
 
-	if( vif1Regs->stat._u32 & (VIF1_STAT_INT|VIF1_STAT_VSS|VIF1_STAT_VIS|VIF1_STAT_VFS) )
+	if (vif1Regs->stat.test(VIF1_STAT_INT | VIF1_STAT_VSS | VIF1_STAT_VIS | VIF1_STAT_VFS) )
 		DevCon.Notice( "Reading from vif1 fifo when stalled" );
 
 	if (vif1Regs->stat.FDR)
@@ -68,11 +66,8 @@ void __fastcall ReadFIFO_page_5(u32 mem, u64 *out)
 			vif1Regs->stat.FQC = 0;
 	}
 
-	//out[0] = psHu64(mem  );
-	//out[1] = psHu64(mem+8);
-
-	out[0] = psHu64(0x5000);
-	out[1] = psHu64(0x5008);
+	out[0] = psHu64(VIF1_FIFO);
+	out[1] = psHu64(VIF1_FIFO + 8);
 }
 
 void __fastcall ReadFIFO_page_6(u32 mem, u64 *out)
@@ -81,11 +76,8 @@ void __fastcall ReadFIFO_page_6(u32 mem, u64 *out)
 
 	DevCon.Notice( "ReadFIFO/GIF, addr=0x%x", mem );
 
-	//out[0] = psHu64(mem  );
-	//out[1] = psHu64(mem+8);
-
-	out[0] = psHu64(0x6000);
-	out[1] = psHu64(0x6008);
+	out[0] = psHu64(GIF_FIFO);
+	out[1] = psHu64(GIF_FIFO + 8);
 }
 
 void __fastcall ReadFIFO_page_7(u32 mem, u64 *out)
@@ -119,11 +111,8 @@ void __fastcall WriteFIFO_page_4(u32 mem, const mem128_t *value)
 
 	VIF_LOG("WriteFIFO/VIF0, addr=0x%08X", mem);
 
-	//psHu64(mem  ) = value[0];
-	//psHu64(mem+8) = value[1];
-
-	psHu64(0x4000) = value[0];
-	psHu64(0x4008) = value[1];
+	psHu64(VIF0_FIFO) = value[0];
+	psHu64(VIF0_FIFO + 8) = value[1];
 
 	vif0ch->qwc += 1;
 	int ret = VIF0transfer((u32*)value, 4, 0);
@@ -136,15 +125,12 @@ void __fastcall WriteFIFO_page_5(u32 mem, const mem128_t *value)
 
 	VIF_LOG("WriteFIFO/VIF1, addr=0x%08X", mem);
 
-	//psHu64(mem  ) = value[0];
-	//psHu64(mem+8) = value[1];
-
-	psHu64(0x5000) = value[0];
-	psHu64(0x5008) = value[1];
+	psHu64(VIF1_FIFO) = value[0];
+	psHu64(VIF1_FIFO + 8) = value[1];
 
 	if (vif1Regs->stat.FDR)
 		DevCon.Notice("writing to fifo when fdr is set!");
-	if ( vif1Regs->stat._u32 & (VIF1_STAT_INT | VIF1_STAT_VSS | VIF1_STAT_VIS | VIF1_STAT_VFS) )
+	if (vif1Regs->stat.test(VIF1_STAT_INT | VIF1_STAT_VSS | VIF1_STAT_VIS | VIF1_STAT_VFS) )
 		DevCon.Notice("writing to vif1 fifo when stalled");
 
 	vif1ch->qwc += 1;
@@ -160,11 +146,8 @@ void __fastcall WriteFIFO_page_6(u32 mem, const mem128_t *value)
 	jASSUME( (mem >= GIF_FIFO) && (mem < IPUout_FIFO) );
 	GIF_LOG("WriteFIFO/GIF, addr=0x%08X", mem);
 
-	//psHu64(mem  ) = value[0];
-	//psHu64(mem+8) = value[1];
-
-	psHu64(0x6000) = value[0];
-	psHu64(0x6008) = value[1];
+	psHu64(GIF_FIFO) = value[0];
+	psHu64(GIF_FIFO + 8) = value[1];
 
 	FreezeRegs(1);
 	mtgsThread.PrepDataPacket(GIF_PATH_3, nloop0_packet, 1);
diff --git a/pcsx2/GS.cpp b/pcsx2/GS.cpp
index f87286d056..355e501ec3 100644
--- a/pcsx2/GS.cpp
+++ b/pcsx2/GS.cpp
@@ -19,6 +19,7 @@
 
 #include "Common.h"
 #include "GS.h"
+#include "Gif.h"
 #include "iR5900.h"
 #include "Counters.h"
 #include "VifDma.h"
@@ -103,16 +104,16 @@ void gsReset()
 
 	GSCSRr = 0x551B4000;   // Set the FINISH bit to 1 for now
 	GSIMR = 0x7f00;
-	psHu32(GIF_STAT) = 0;
-	psHu32(GIF_CTRL) = 0;
-	psHu32(GIF_MODE) = 0;
+	gifRegs->stat._u32 = 0;
+	gifRegs->ctrl._u32 = 0;
+	gifRegs->mode._u32 = 0;
 }
 
 void gsGIFReset()
 {
-	psHu32(GIF_STAT) = 0;
-	psHu32(GIF_CTRL) = 0;
-	psHu32(GIF_MODE) = 0;
+	gifRegs->stat._u32 = 0;
+	gifRegs->ctrl._u32 = 0;
+	gifRegs->mode._u32 = 0;
 }
 
 void gsCSRwrite(u32 value)
@@ -166,13 +167,13 @@ __forceinline void gsWrite8(u32 mem, u8 value)
 {
 	switch (mem)
 	{
-		case 0x12001000: // GS_CSR
+		case GS_CSR: // GS_CSR
 			gsCSRwrite((CSRw & ~0x000000ff) | value); break;
-		case 0x12001001: // GS_CSR
+		case GS_CSR + 1: // GS_CSR
 			gsCSRwrite((CSRw & ~0x0000ff00) | (value <<  8)); break;
-		case 0x12001002: // GS_CSR
+		case GS_CSR + 2: // GS_CSR
 			gsCSRwrite((CSRw & ~0x00ff0000) | (value << 16)); break;
-		case 0x12001003: // GS_CSR
+		case GS_CSR + 3: // GS_CSR
 			gsCSRwrite((CSRw & ~0xff000000) | (value << 24)); break;
 		default:
 			*PS2GS_BASE(mem) = value;
diff --git a/pcsx2/Gif.cpp b/pcsx2/Gif.cpp
index 8cb5e045ed..8ca03708e2 100644
--- a/pcsx2/Gif.cpp
+++ b/pcsx2/Gif.cpp
@@ -65,8 +65,7 @@ __forceinline void gsInterrupt()
 		if (Path3progress != IMAGE_MODE) vif1Regs->stat.VGW = 0;
 	}
 
-	if (Path3progress == STOPPED_MODE) gifRegs->stat._u32 &= ~(GIF_STAT_APATH3 | GIF_STAT_OPH); // OPH=0 | APATH=0
-
+	if (Path3progress == STOPPED_MODE) gifRegs->stat.clear(GIF_STAT_APATH3 | GIF_STAT_OPH); // OPH=0 | APATH=0
 	if ((gif->qwc > 0) || (!gspath3done)) 
 	{
 		if (!dmacRegs->ctrl.DMAE) 
@@ -86,7 +85,7 @@ __forceinline void gsInterrupt()
 	gif->chcr.STR = 0;
 	vif1Regs->stat.VGW = 0;
 	
-	gifRegs->stat._u32 &= ~(GIF_STAT_APATH3 | GIF_STAT_OPH | GIF_STAT_P3Q | GIF_STAT_FQC); 
+	gifRegs->stat.clear(GIF_STAT_APATH3 | GIF_STAT_OPH | GIF_STAT_P3Q | GIF_STAT_FQC); 
 	
 	clearFIFOstuff(false);
 	hwDmacIrq(DMAC_GIF);
@@ -541,7 +540,7 @@ void gifMFIFOInterrupt()
 			//Console.WriteLn("Empty");
 			hwDmacIrq(DMAC_MFIFO_EMPTY);
 			gifstate |= GIF_STATE_EMPTY;
-			gifRegs->stat.IMT = 0; // OPH=0 | APATH=0
+			gifRegs->stat.IMT = 0;
 			return;
 		}
 		mfifoGIFtransfer(0);
@@ -561,7 +560,7 @@ void gifMFIFOInterrupt()
 	gspath3done = false;
 	gscycles = 0;
 	
-	gifRegs->stat._u32 &= ~(GIF_STAT_APATH3 | GIF_STAT_OPH | GIF_STAT_P3Q | GIF_STAT_FQC); // OPH, APATH, P3Q,  FQC = 0
+	gifRegs->stat.clear(GIF_STAT_APATH3 | GIF_STAT_OPH | GIF_STAT_P3Q | GIF_STAT_FQC); // OPH, APATH, P3Q,  FQC = 0
 	
 	vif1Regs->stat.VGW = 0;
 	gif->chcr.STR = 0;
diff --git a/pcsx2/Gif.h b/pcsx2/Gif.h
index 4c0d139601..40d7c89c6b 100644
--- a/pcsx2/Gif.h
+++ b/pcsx2/Gif.h
@@ -115,6 +115,10 @@ union tGIF_STAT
 	tGIF_STAT( u32 val ) : _u32( val )
 	{
 	}
+	
+	bool test(u32 flags) { return (_u32 & flags); }
+	void set(u32 flags) { _u32 |= flags; }
+	void clear(u32 flags) { _u32 &= ~flags; }
 };
 
 union tGIF_TAG0
diff --git a/pcsx2/Hw.h b/pcsx2/Hw.h
index 8ab1da7d16..824d07afa6 100644
--- a/pcsx2/Hw.h
+++ b/pcsx2/Hw.h
@@ -388,6 +388,10 @@ union tDMAC_STAT {
 		u32 reserved3 : 1;
 	};
 	u32 _u32;
+	
+	bool test(u32 flags) { return (_u32 & flags); }
+	void set(u32 flags) { _u32 |= flags; }
+	void clear(u32 flags) { _u32 &= ~flags; }
 };
 
 union tDMAC_PCR {
diff --git a/pcsx2/HwWrite.cpp b/pcsx2/HwWrite.cpp
index 33df800001..0180dc51b2 100644
--- a/pcsx2/HwWrite.cpp
+++ b/pcsx2/HwWrite.cpp
@@ -50,9 +50,7 @@ static __forceinline void DmaExec8( void (*func)(), u32 mem, u8 value )
 	// Upper 16bits of QWC should not be written since QWC is 16bits in size.
 	if ((psHu32(qwcRegister) >> 16) != 0)
 	{
-		DMA_LOG("DMA QWC (%x) upper 16bits set to %x\n", 
-			qwcRegister,
-			psHu32(qwcRegister) >> 16); 
+		DMA_LOG("DMA QWC (%x) upper 16bits set to %x\n", qwcRegister, psHu32(qwcRegister) >> 16); 
 		psHu32(qwcRegister) = 0; 
 	}
 
@@ -114,7 +112,7 @@ static void DmaExec( void (*func)(), u32 mem, u32 value )
 		psHu32(qwcRegister) = 0; 
 	}
 
-	/* Keep the old tag if in chain mode and hw doesnt set it*/
+	/* Keep the old tag if in chain mode and hw doesn't set it*/
 	if (((value & 0xc) == 0x4) && ((value & 0xffff0000) == 0))
 		psHu32(mem) = (psHu32(mem) & 0xffff0000) | (u16)value;
 	else /* Else (including Normal mode etc) write whatever the hardware sends*/
@@ -298,8 +296,8 @@ void hwWrite8(u32 mem, u8 value)
 			break;
 
 		case DMAC_ENABLEW + 2:
-			psHu8(0xf592) = value;
-			psHu8(0xf522) = value;
+			psHu8(DMAC_ENABLEW + 2) = value;
+			psHu8(DMAC_ENABLER + 2) = value;
 			break;
 
 		case SBUS_F200: // SIF(?)
@@ -331,7 +329,7 @@ void hwWrite8(u32 mem, u8 value)
 			break;
 		
 		default:
-			assert( (mem&0xff0f) != 0xf200 );
+			assert( (mem & 0xff0f) != 0xf200 );
 
 			switch(mem&~3) {
 				case SIO_ISR:
@@ -613,8 +611,8 @@ __forceinline void hwWrite16(u32 mem, u16 value)
 			break;
 			
 		case DMAC_ENABLEW + 2:
-			psHu16(0xf592) = value;
-			psHu16(0xf522) = value;
+			psHu16(DMAC_ENABLEW + 2) = value;
+			psHu16(DMAC_ENABLER + 2) = value;
 			break;
 		
 		case SIO_ISR:
@@ -726,20 +724,21 @@ void __fastcall hwWrite32_page_03( u32 mem, u32 value )
 			if (value & 0x1)
 				gsGIFReset();
 			else if ( value & 8 )
-				psHu32(GIF_STAT) |= GIF_STAT_PSE;
+				gifRegs->stat.PSE = 1;
 			else
-				psHu32(GIF_STAT) &= ~GIF_STAT_PSE;
+				gifRegs->stat.PSE = 0; 
 		break;
 
 		case GIF_MODE:
 		{
 			// need to set GIF_MODE (hamster ball)
-			psHu32(GIF_MODE) = value;
+			gifRegs->mode._u32 = value;
 
 			// set/clear bits 0 and 2 as per the GIF_MODE value.
-			const u32 bitmask = GIF_MODE_M3R | GIF_MODE_IMT;
+            const u32 bitmask = GIF_MODE_M3R | GIF_MODE_IMT;
 			psHu32(GIF_STAT) &= ~bitmask;
 			psHu32(GIF_STAT) |= (u32)value & bitmask;
+
 		}
 		break;
 
@@ -798,14 +797,14 @@ void __fastcall hwWrite32_page_0B( u32 mem, u32 value )
 
 void __fastcall StartQueuedDMA()
 {
-	if(QueuedDMA & 0x1) { QueuedDMA &= ~0x1; dmaVIF0(); }
-	if(QueuedDMA & 0x2) { QueuedDMA &= ~0x2; dmaVIF1(); }
-	if(QueuedDMA & 0x4) { QueuedDMA &= ~0x4; dmaGIF(); }
-	if(QueuedDMA & 0x8) { QueuedDMA &= ~0x8; dmaIPU0(); }
-	if(QueuedDMA & 0x10) { QueuedDMA &= ~0x10; dmaIPU1(); }
-	if(QueuedDMA & 0x20) { QueuedDMA &= ~0x20; dmaSIF0(); }
-	if(QueuedDMA & 0x40) { QueuedDMA &= ~0x40; dmaSIF1(); }
-	if(QueuedDMA & 0x80) { QueuedDMA &= ~0x80; dmaSIF2(); }
+	if(QueuedDMA & 0x001) { QueuedDMA &= ~0x001; dmaVIF0(); }
+	if(QueuedDMA & 0x002) { QueuedDMA &= ~0x002; dmaVIF1(); }
+	if(QueuedDMA & 0x004) { QueuedDMA &= ~0x004; dmaGIF(); }
+	if(QueuedDMA & 0x008) { QueuedDMA &= ~0x008; dmaIPU0(); }
+	if(QueuedDMA & 0x010) { QueuedDMA &= ~0x010; dmaIPU1(); }
+	if(QueuedDMA & 0x020) { QueuedDMA &= ~0x020; dmaSIF0(); }
+	if(QueuedDMA & 0x040) { QueuedDMA &= ~0x040; dmaSIF1(); }
+	if(QueuedDMA & 0x080) { QueuedDMA &= ~0x080; dmaSIF2(); }
 	if(QueuedDMA & 0x100) { QueuedDMA &= ~0x100; dmaSPR0(); }
 	if(QueuedDMA & 0x200) { QueuedDMA &= ~0x200; dmaSPR1(); }
 }
@@ -904,8 +903,8 @@ void __fastcall hwWrite32_page_0F( u32 mem, u32 value )
 
 		case HELPSWITCH(DMAC_ENABLEW):
 			HW_LOG("DMAC_ENABLEW Write 32bit %lx", value);
-			psHu32(0xf590) = value;
-			psHu32(0xf520) = value;
+			psHu32(DMAC_ENABLEW) = value;
+			psHu32(DMAC_ENABLER) = value;
 			break;
 
 		//------------------------------------------------------------------
@@ -1182,8 +1181,8 @@ void __fastcall hwWrite64_generic( u32 mem, const mem64_t* srcval )
 			break;
 
 		case DMAC_ENABLEW: // DMAC_ENABLEW
-			psHu32(0xf590) = value;
-			psHu32(0xf520) = value;
+			psHu32(DMAC_ENABLEW) = value;
+			psHu32(DMAC_ENABLER) = value;
 		break;
 
 		default:
@@ -1215,8 +1214,8 @@ void __fastcall hwWrite128_generic(u32 mem, const mem128_t *srcval)
 		break;
 
 		case DMAC_ENABLEW: // DMAC_ENABLEW
-			psHu32(0xf590) = srcval[0];
-			psHu32(0xf520) = srcval[0];
+			psHu32(DMAC_ENABLEW) = srcval[0];
+			psHu32(DMAC_ENABLER) = srcval[0];
 		break;
 
 		case SIO_ISR:
diff --git a/pcsx2/IPU/IPU.cpp b/pcsx2/IPU/IPU.cpp
index 87231e73a8..2d41f11f4b 100644
--- a/pcsx2/IPU/IPU.cpp
+++ b/pcsx2/IPU/IPU.cpp
@@ -350,7 +350,7 @@ __forceinline void ipuWrite32(u32 mem, u32 value)
 				ipuRegs->ctrl.IDP = 1;
 			}
 
-			if (ipuRegs->ctrl.RST & 0x1) ipuSoftReset(); // RESET
+			if (ipuRegs->ctrl.RST) ipuSoftReset(); // RESET
 
 			IPU_LOG("Ipu write32: IPU_CTRL=0x%08X", value);
 			break;
@@ -1005,7 +1005,7 @@ u8* prev_readbits()
 {
 	if (readbits < _readbits + 16) return _readbits + 48 - (readbits - _readbits);
 
-	return readbits -16;
+	return readbits - 16;
 }
 
 void ReorderBitstream()
@@ -1467,7 +1467,7 @@ int IPU1dma()
 		if (IPU1chain(totalqwc)) return totalqwc;
 
 		//Check TIE bit of CHCR and IRQ bit of tag
-		if (ipu1dma->chcr.TIE && (g_nDMATransfer.DOTIE1))
+		if (ipu1dma->chcr.TIE && g_nDMATransfer.DOTIE1)
 		{
 			Console.WriteLn("IPU1 TIE");
 
diff --git a/pcsx2/Tags.h b/pcsx2/Tags.h
index 8a46c0fed2..8956ccd258 100644
--- a/pcsx2/Tags.h
+++ b/pcsx2/Tags.h
@@ -45,7 +45,7 @@ enum d_ctrl_flags
 	CTRL_RELE = 0x2, // 0/1 - cycle stealing off/on
 	CTRL_MFD = 0xC, // Memory FIFO drain channel (mfd_type)
 	CTRL_STS = 0x30, // Stall Control source channel (sts type)
-	CTRL_STD = 0xC0, // Stall Controll drain channel (std_type)
+	CTRL_STD = 0xC0, // Stall Control drain channel (std_type)
 	CTRL_RCYC = 0x100 // Release cycle (8/16/32/64/128/256)
 	// When cycle stealing is on, the release cycle sets the period to release
 	// the bus to EE.
diff --git a/pcsx2/Vif.cpp b/pcsx2/Vif.cpp
index 065e32677c..65a1e0bd9a 100644
--- a/pcsx2/Vif.cpp
+++ b/pcsx2/Vif.cpp
@@ -640,7 +640,7 @@ void vifMFIFOInterrupt()
 		vif1Regs->stat.INT = 1;
 		hwIntcIrq(INTC_VIF1);
 		--vif1.irq;
-		if (vif1Regs->stat._u32 & (VIF1_STAT_VSS | VIF1_STAT_VIS | VIF1_STAT_VFS))
+		if (vif1Regs->stat.test(VIF1_STAT_VSS | VIF1_STAT_VIS | VIF1_STAT_VFS))
 		{
 			vif1Regs->stat.FQC = 0; // FQC=0
 			vif1ch->chcr.STR = 0;
diff --git a/pcsx2/Vif.h b/pcsx2/Vif.h
index ea42ce22bc..c559c90813 100644
--- a/pcsx2/Vif.h
+++ b/pcsx2/Vif.h
@@ -103,6 +103,10 @@ union tVIF_STAT {
 		u32 FQC : 5; // Amount of data. Up to 8 qwords on Vif0, 16 on Vif1.
 	};
 	u32 _u32;
+	
+	bool test(u32 flags) { return (_u32 & flags); }
+	void set(u32 flags) { _u32 |= flags; }
+	void clear(u32 flags) { _u32 &= ~flags; }
 };
 
 union tVIF_FBRST {
diff --git a/pcsx2/VifDma.cpp b/pcsx2/VifDma.cpp
index e7b7e8cfd8..7411e17ae6 100644
--- a/pcsx2/VifDma.cpp
+++ b/pcsx2/VifDma.cpp
@@ -1425,7 +1425,7 @@ void  vif0Interrupt()
 		hwIntcIrq(VIF0intc);
 		--vif0.irq;
 
-		if (vif0Regs->stat._u32 & (VIF0_STAT_VSS | VIF0_STAT_VIS | VIF0_STAT_VFS))
+		if (vif0Regs->stat.test(VIF0_STAT_VSS | VIF0_STAT_VIS | VIF0_STAT_VFS))
 		{
 			vif0Regs->stat.FQC = 0; // FQC=0
 			vif0ch->chcr.STR = 0;
@@ -1567,7 +1567,7 @@ void vif0Write32(u32 mem, u32 value)
 				psHu64(VIF0_FIFO + 8) = 0; // VIF0_FIFO + 8
 				vif0.done = true;
 				vif0Regs->err._u32 = 0;
-				vif0Regs->stat._u32 &= ~(VIF0_STAT_FQC | VIF0_STAT_INT | VIF0_STAT_VSS | VIF0_STAT_VIS | VIF0_STAT_VFS | VIF0_STAT_VPS); // FQC=0
+				vif0Regs->stat.clear(VIF0_STAT_FQC | VIF0_STAT_INT | VIF0_STAT_VSS | VIF0_STAT_VIS | VIF0_STAT_VFS | VIF0_STAT_VPS); // FQC=0
 			}
 
 			if (value & 0x2)
@@ -1596,10 +1596,10 @@ void vif0Write32(u32 mem, u32 value)
 				bool cancel = false;
 
 				/* Cancel stall, first check if there is a stall to cancel, and then clear VIF0_STAT VSS|VFS|VIS|INT|ER0|ER1 bits */
-				if (vif0Regs->stat._u32 & (VIF0_STAT_VSS | VIF0_STAT_VIS | VIF0_STAT_VFS))
+				if (vif0Regs->stat.test(VIF0_STAT_VSS | VIF0_STAT_VIS | VIF0_STAT_VFS))
 					cancel = true;
 
-				vif0Regs->stat._u32 &= ~(VIF0_STAT_VSS | VIF0_STAT_VFS | VIF0_STAT_VIS |
+				vif0Regs->stat.clear(VIF0_STAT_VSS | VIF0_STAT_VFS | VIF0_STAT_VIS |
 						    VIF0_STAT_INT | VIF0_STAT_ER0 | VIF0_STAT_ER1);
 				if (cancel)
 				{
@@ -1924,7 +1924,7 @@ static int __fastcall Vif1TransDirectHL(u32 *data)
 	}
 	else
 	{
-		gifRegs->stat._u32 &= ~(GIF_STAT_APATH2 | GIF_STAT_OPH);
+		gifRegs->stat.clear(GIF_STAT_APATH2 | GIF_STAT_OPH);
 		ret = vif1.tag.size;
 		vif1.tag.size = 0;
 		vif1.cmd = 0;
@@ -2526,7 +2526,7 @@ __forceinline void vif1Interrupt()
 		vif1Regs->stat.INT = 1;
 		hwIntcIrq(VIF1intc);
 		--vif1.irq;
-		if (vif1Regs->stat._u32 & (VIF1_STAT_VSS | VIF1_STAT_VIS | VIF1_STAT_VFS))
+		if (vif1Regs->stat.test(VIF1_STAT_VSS | VIF1_STAT_VIS | VIF1_STAT_VFS))
 		{
 			vif1Regs->stat.FQC = 0; // FQC=0
 
@@ -2632,7 +2632,7 @@ void dmaVIF1()
 	if (vif1.dmamode != VIF_NORMAL_FROM_MEM_MODE)
 		vif1Regs->stat.FQC = 0x10; // FQC=16
 	else
-		vif1Regs->stat._u32 |= min((u16)16, vif1ch->qwc) << 24; // FQC=16
+		vif1Regs->stat.set(min((u16)16, vif1ch->qwc) << 24); // FQC=16
 
 	// Chain Mode
 	vif1.done = false;
@@ -2673,7 +2673,7 @@ void vif1Write32(u32 mem, u32 value)
 
 				vif1Regs->err._u32 = 0;
 				vif1.inprogress = 0;
-				vif1Regs->stat._u32 &= ~(VIF1_STAT_FQC | VIF1_STAT_FDR | VIF1_STAT_INT | VIF1_STAT_VSS | VIF1_STAT_VIS | VIF1_STAT_VFS | VIF1_STAT_VPS); // FQC=0
+				vif1Regs->stat.clear(VIF1_STAT_FQC | VIF1_STAT_FDR | VIF1_STAT_INT | VIF1_STAT_VSS | VIF1_STAT_VIS | VIF1_STAT_VFS | VIF1_STAT_VPS); // FQC=0
 			}
 
 			if (value & 0x2)
@@ -2703,12 +2703,12 @@ void vif1Write32(u32 mem, u32 value)
 				bool cancel = false;
 
 				/* Cancel stall, first check if there is a stall to cancel, and then clear VIF1_STAT VSS|VFS|VIS|INT|ER0|ER1 bits */
-				if (vif1Regs->stat._u32 & (VIF1_STAT_VSS | VIF1_STAT_VIS | VIF1_STAT_VFS))
+				if (vif1Regs->stat.test(VIF1_STAT_VSS | VIF1_STAT_VIS | VIF1_STAT_VFS))
 				{
 					cancel = true;
 				}
 
-				vif1Regs->stat._u32 &= ~(VIF1_STAT_VSS | VIF1_STAT_VFS | VIF1_STAT_VIS |
+				vif1Regs->stat.clear(VIF1_STAT_VSS | VIF1_STAT_VFS | VIF1_STAT_VIS |
 						VIF1_STAT_INT | VIF1_STAT_ER0 | VIF1_STAT_ER1);
 
 				if (cancel)
@@ -2753,14 +2753,14 @@ void vif1Write32(u32 mem, u32 value)
 			if ((vif1Regs->stat.FDR) ^(value & VIF1_STAT_FDR))
 			{
 				// different so can't be stalled
-				if (vif1Regs->stat._u32 & (VIF1_STAT_INT | VIF1_STAT_VSS | VIF1_STAT_VIS | VIF1_STAT_VFS))
+				if (vif1Regs->stat.test(VIF1_STAT_INT | VIF1_STAT_VSS | VIF1_STAT_VIS | VIF1_STAT_VFS))
 				{
 					DevCon.WriteLn("changing dir when vif1 fifo stalled");
 				}
 			}
 #endif
 
-			vif1Regs->stat._u32 = (vif1Regs->stat._u32 & ~VIF1_STAT_FDR) | (value & VIF1_STAT_FDR);
+			vif1Regs->stat._u32 = (vif1Regs->stat.test(~VIF1_STAT_FDR)) | (value & VIF1_STAT_FDR);
 			if (vif1Regs->stat.FDR)
 			{
 				vif1Regs->stat.FQC = 1; // FQC=1 - hack but it checks this is true before transfer? (fatal frame)