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Fixes for Ikusa, Kinetica and Need for Speed Underground, should all be working again (or as good as before r3274) 

git-svn-id: http://pcsx2.googlecode.com/svn/trunk@4081 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
refraction 2010-12-11 00:29:20 +00:00
parent 2b9e609529
commit 41fc6feaf7
2 changed files with 19 additions and 9 deletions
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12
pcsx2/Vif.cpp
View File

@ -77,12 +77,16 @@ __fi void vif0FBRST(u32 value) {
memzero(vif0); memzero(vif0);
vif0ch.qwc = 0; //? vif0ch.qwc = 0; //?
cpuRegs.interrupt &= ~1; //Stop all vif0 DMA's //cpuRegs.interrupt &= ~1; //Stop all vif0 DMA's
psHu64(VIF0_FIFO) = 0; psHu64(VIF0_FIFO) = 0;
psHu64(VIF0_FIFO + 8) = 0; psHu64(VIF0_FIFO + 8) = 0;
vif0.done = false; vif0.vifstalled = false;
vif0.inprogress = 0;
vif0.cmd = 0;
//vif0.done = false;
vif0Regs.err.reset(); vif0Regs.err.reset();
vif0Regs.stat.clear_flags(VIF0_STAT_FQC | VIF0_STAT_INT | VIF0_STAT_VSS | VIF0_STAT_VIS | VIF0_STAT_VFS | VIF0_STAT_VPS); // FQC=0 vif0Regs.stat.clear_flags(VIF0_STAT_FQC | VIF0_STAT_INT | VIF0_STAT_VSS | VIF0_STAT_VIS | VIF0_STAT_VFS | VIF0_STAT_VPS); // FQC=0
if(vif0ch.chcr.STR == true) CPU_INT(DMAC_VIF0, 4);
} }
/* Fixme: Forcebreaks are pretty unknown for operation, presumption is it just stops it what its doing /* Fixme: Forcebreaks are pretty unknown for operation, presumption is it just stops it what its doing
@ -137,7 +141,8 @@ __fi void vif1FBRST(u32 value) {
memzero(vif1); memzero(vif1);
//cpuRegs.interrupt &= ~((1 << 1) | (1 << 10)); //Stop all vif1 DMA's //cpuRegs.interrupt &= ~((1 << 1) | (1 << 10)); //Stop all vif1 DMA's
vif1ch.qwc -= min((int)vif1ch.qwc, 16); //? //vif1ch.qwc -= min((int)vif1ch.qwc, 16); //not sure if the dma should stop, FFWDing could be tricky
vif1ch.qwc = 0;
psHu64(VIF1_FIFO) = 0; psHu64(VIF1_FIFO) = 0;
psHu64(VIF1_FIFO + 8) = 0; psHu64(VIF1_FIFO + 8) = 0;
//vif1.done = false; //vif1.done = false;
@ -160,6 +165,7 @@ __fi void vif1FBRST(u32 value) {
vif1.vifstalled = false; vif1.vifstalled = false;
vif1Regs.stat.FQC = 0; vif1Regs.stat.FQC = 0;
vif1Regs.stat.clear_flags(VIF1_STAT_FDR | VIF1_STAT_INT | VIF1_STAT_VSS | VIF1_STAT_VIS | VIF1_STAT_VFS | VIF1_STAT_VPS); vif1Regs.stat.clear_flags(VIF1_STAT_FDR | VIF1_STAT_INT | VIF1_STAT_VSS | VIF1_STAT_VIS | VIF1_STAT_VFS | VIF1_STAT_VPS);
if(vif1ch.chcr.STR == true) CPU_INT(DMAC_VIF1, 4);
} }
/* Fixme: Forcebreaks are pretty unknown for operation, presumption is it just stops it what its doing /* Fixme: Forcebreaks are pretty unknown for operation, presumption is it just stops it what its doing

16
pcsx2/Vif_Codes.cpp
View File

@ -115,6 +115,8 @@ vifOp(vifCode_Base) {
} }
extern bool SIGNAL_IMR_Pending; extern bool SIGNAL_IMR_Pending;
static __aligned16 u32 partial_write[4];
static uint partial_count = 0;
template<int idx> __fi int _vifCode_Direct(int pass, const u8* data, bool isDirectHL) { template<int idx> __fi int _vifCode_Direct(int pass, const u8* data, bool isDirectHL) {
pass1 { pass1 {
@ -175,7 +177,7 @@ template<int idx> __fi int _vifCode_Direct(int pass, const u8* data, bool isDire
uint minSize = aMin(vif1.vifpacketsize, vif1.tag.size); uint minSize = aMin(vif1.vifpacketsize, vif1.tag.size);
uint ret; uint ret;
if(minSize < 4) if(minSize < 4 || partial_count > 0)
{ {
// When TTE==1, the VIF might end up sending us 8-byte packets instead of the usual 16-byte // When TTE==1, the VIF might end up sending us 8-byte packets instead of the usual 16-byte
// variety, if DIRECT tags cross chain dma boundaries. The actual behavior of real hardware // variety, if DIRECT tags cross chain dma boundaries. The actual behavior of real hardware
@ -189,10 +191,10 @@ template<int idx> __fi int _vifCode_Direct(int pass, const u8* data, bool isDire
// be any need to worry about queuing more than 16 bytes of data, // be any need to worry about queuing more than 16 bytes of data,
// //
static __aligned16 u32 partial_write[4];
static uint partial_count = 0;
ret = 0; ret = 0;
minSize = aMin(minSize, 4-partial_count);
for( uint i=0; i<(minSize & 3); ++i) for( uint i=0; i<(minSize & 3); ++i)
{ {
partial_write[partial_count++] = ((u32*)data)[i]; partial_write[partial_count++] = ((u32*)data)[i];
@ -375,14 +377,16 @@ vifOp(vifCode_MSCNT) {
vifOp(vifCode_MskPath3) { vifOp(vifCode_MskPath3) {
vif1Only(); vif1Only();
pass1 { pass1 {
//I Hate the timing sensitivity of this stuff
if (vif1ch.chcr.STR && vif1.lastcmd != 0x13) { if (vif1ch.chcr.STR && vif1.lastcmd != 0x13) {
schedulepath3msk = 0x10 | ((vif1Regs.code >> 15) & 0x1); schedulepath3msk = 0x10 | ((vif1Regs.code >> 15) & 0x1);
vif1.vifstalled = true;
} }
else { else
{
schedulepath3msk = (vif1Regs.code >> 15) & 0x1; schedulepath3msk = (vif1Regs.code >> 15) & 0x1;
Vif1MskPath3(); Vif1MskPath3();
} }
if(vif1ch.chcr.STR)vif1.vifstalled = true;
vif1.cmd = 0; vif1.cmd = 0;
} }
pass3 { VifCodeLog("MskPath3"); } pass3 { VifCodeLog("MskPath3"); }