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psxmode:IOP: plug in hardware read / write handlers for PGIF and MDEC 

v2:
* Update sioRead8() to read a single byte  and add a comment on it
* Better code integration IOP REG

v3:
* only log the bad 16 bit access
This commit is contained in:
Robert 2016-09-23 10:38:13 +02:00 committed by Gregory Hainaut
parent 35fa20d965
commit 4047e34050
3 changed files with 89 additions and 145 deletions
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14
pcsx2/IopHw.h
View File

@ -18,12 +18,14 @@
#include "IopMem.h"
static const u32
HW_USB_START = 0x1f801600,
HW_USB_END = 0x1f801700,
HW_FW_START = 0x1f808400,
HW_FW_END = 0x1f808550, // end addr for FW is a guess...
HW_SPU2_START = 0x1f801c00,
HW_SPU2_END = 0x1f801e00;
HW_PS1_GPU_START = 0x1F8010A0,
HW_PS1_GPU_END = 0x1F8010B0,
HW_USB_START = 0x1f801600,
HW_USB_END = 0x1f801700,
HW_FW_START = 0x1f808400,
HW_FW_END = 0x1f808550, // end addr for FW is a guess...
HW_SPU2_START = 0x1f801c00,
HW_SPU2_END = 0x1f801e00;
static const u32
HW_SSBUS_SPD_ADDR = 0x1f801000,

77
pcsx2/ps2/Iop/IopHwRead.cpp
View File

@ -20,6 +20,9 @@
#include "Sio.h"
#include "CDVD/CdRom.h"
#include "ps2/pgif.h"
#include "Mdec.h"
namespace IopMemory
{
using namespace Internal;
@ -36,7 +39,12 @@ mem8_t __fastcall iopHwRead8_Page1( u32 addr )
mem8_t ret; // using a return var can be helpful in debugging.
switch( masked_addr )
{
mcase(HW_SIO_DATA): ret = sioRead8(); break;
mcase(HW_SIO_DATA) :
// 1F801040h 1/4 JOY_DATA Joypad/Memory Card Data (R/W)
// psxmode: documentation suggests a valid 8 bit read and the rest of the 32 bit register is unclear.
// todo: check this and compare with the HW_SIO_DATA read around line 245 as well.
ret = sioRead8();
break;
// for use of serial port ignore for now
//case 0x50: ret = serial_read8(); break;
@ -85,7 +93,8 @@ mem8_t __fastcall iopHwRead8_Page3( u32 addr )
mem8_t ret;
if( addr == 0x1f803100 ) // PS/EE/IOP conf related
ret = 0x10; // Dram 2M
//ret = 0x10; // Dram 2M
ret = 0xFF; //all high bus is the corect default state for CEX PS2!
else
ret = psxHu8( addr );
@ -110,7 +119,6 @@ mem8_t __fastcall iopHwRead8_Page8( u32 addr )
IopHwTraceLog<mem8_t>( addr, ret, true );
return ret;
}
//////////////////////////////////////////////////////////////////////////////////////////
//
template< typename T >
@ -126,7 +134,7 @@ static __fi T _HwRead_16or32_Page1( u32 addr )
);
u32 masked_addr = pgmsk( addr );
T ret;
T ret = 0;
// ------------------------------------------------------------------------
// Counters, 16-bit varieties!
@ -216,10 +224,23 @@ static __fi T _HwRead_16or32_Page1( u32 addr )
ret = SPU2read( addr );
else
{
DbgCon.Warning( "HwRead32 from SPU2? @ 0x%08X .. What manner of trickery is this?!", addr );
DevCon.Warning( "HwRead32 from SPU2? @ 0x%08X .. What manner of trickery is this?!", addr );
ret = psxHu32(addr);
}
}
// ------------------------------------------------------------------------
// PS1 GPU access
//
else if( (masked_addr >= pgmsk(HW_PS1_GPU_START)) && (masked_addr < pgmsk(HW_PS1_GPU_END)) )
{
// todo: psx mode: this is new
if( sizeof(T) == 2 )
DevCon.Warning( "HwRead16 from PS1 GPU? @ 0x%08X .. What manner of trickery is this?!", addr );
pxAssert(sizeof(T) == 4);
ret = psxDma2GpuR(addr);
}
else
{
switch( masked_addr )
@ -237,6 +258,8 @@ static __fi T _HwRead_16or32_Page1( u32 addr )
mcase(HW_SIO_STAT):
ret = sio.StatReg;
sioStatRead();
// Console.WriteLn( "SIO0 Read STAT %02X INT_STAT= %08X IOPpc= %08X " , ret, psxHu32(0x1070), psxRegs.pc);
break;
mcase(HW_SIO_MODE):
@ -301,51 +324,26 @@ static __fi T _HwRead_16or32_Page1( u32 addr )
break;
mcase(HW_PS1_GPU_DATA) :
ret = psxHu32(addr);
ret = psxGPUr(addr);
//ret = psxHu32(addr); // old
DevCon.Warning("GPU Data Read %x", ret);
break;
mcase(HW_PS1_GPU_STATUS) :
//ret = psxHu32(addr);
/*if (sif2.fifo.size == 0x8) psxHu32(0x1f801814) &= ~(3 << 25);
else psxHu32(0x1f801814) |= (3 << 25);*/
/*switch ((psxHu32(HW_PS1_GPU_STATUS) >> 29) & 0x3)
{
case 0x0:
//DevCon.Warning("Set DMA Mode OFF");
psxHu32(HW_PS1_GPU_STATUS) &= ~0x2000000;
break;
case 0x1:
//DevCon.Warning("Set DMA Mode FIFO");
psxHu32(HW_PS1_GPU_STATUS) |= 0x2000000;
break;
case 0x2:
//DevCon.Warning("Set DMA Mode CPU->GPU");
psxHu32(HW_PS1_GPU_STATUS) = (psxHu32(HW_PS1_GPU_STATUS) & ~0x2000000) | ((psxHu32(HW_PS1_GPU_STATUS) & 0x10000000) >> 3);
break;
case 0x3:
//DevCon.Warning("Set DMA Mode GPUREAD->CPU");
psxHu32(HW_PS1_GPU_STATUS) = (psxHu32(HW_PS1_GPU_STATUS) & ~0x2000000) | ((psxHu32(HW_PS1_GPU_STATUS) & 0x8000000) >> 2);
break;
}*/
ret = psxHu32(addr); //Idle & Ready to recieve command.
//psxHu32(addr) = psHu32(0x1000f300);
#if PSX_EXTRALOGS
DevCon.Warning("GPU Status Read %x Sif fifo size %x", ret, sif2.fifo.size);
#endif
//ret = -1; // fake alive GPU :p
ret = psxGPUr(addr);
break;
mcase (0x1f801820): // MDEC
ret = psxHu32(addr);
// ret = psxHu32(addr); // old
ret = mdecRead0();
#if PSX_EXTRALOGS
DevCon.Warning("MDEC 1820 Read %x", ret);
#endif
break;
mcase (0x1f801824): // MDEC
ret = psxHu32(addr);
//ret = psxHu32(addr); // old
ret = mdecRead1();
#if PSX_EXTRALOGS
DevCon.Warning("MDEC 1824 Read %x", ret);
#endif
@ -461,12 +459,15 @@ mem32_t __fastcall iopHwRead32_Page8( u32 addr )
// 4-byte FIFO input?
// The old IOP system just ignored it, so that's what we do here. I've included commented code
// for treating it as a 16/32 bit write though [which is what the SIO does, for example).
mcase(HW_SIO2_FIFO):
mcase(HW_SIO2_FIFO) :
//ret = sio2_fifoOut();
//ret |= sio2_fifoOut() << 8;
//ret |= sio2_fifoOut() << 16;
//ret |= sio2_fifoOut() << 24;
//break;
DevCon.Warning("HW_SIO2_FIFO read");
ret = psxHu32(addr);
break;
default:
ret = psxHu32(addr);

143
pcsx2/ps2/Iop/IopHwWrite.cpp
View File

@ -19,6 +19,9 @@
#include "Sio.h"
#include "CDVD/CdRom.h"
#include "ps2/pgif.h"
#include "Mdec.h"
namespace IopMemory {
using namespace Internal;
@ -248,6 +251,19 @@ static __fi void _HwWrite_16or32_Page1( u32 addr, T val )
//psxHu(addr) = val;
}
}
// ------------------------------------------------------------------------
// PS1 GPU access
//
else if( (masked_addr >= pgmsk(HW_PS1_GPU_START)) && (masked_addr < pgmsk(HW_PS1_GPU_END)) )
{
// todo: psx mode: this is new
if( sizeof(T) == 2 )
DevCon.Warning( "HwWrite16 to PS1 GPU? @ 0x%08X .. What manner of trickery is this?!", addr );
pxAssert(sizeof(T) == 4);
psxDma2GpuW(addr, val);
}
else
{
switch( masked_addr )
@ -279,7 +295,8 @@ static __fi void _HwWrite_16or32_Page1( u32 addr, T val )
break;
mcase(HW_SIO_CTRL):
sio.CtrlReg = (u16)val;
//sio.CtrlReg = (u16)val;
sioWriteCtrl16((u16)val);
break;
mcase(HW_SIO_BAUD):
@ -295,6 +312,10 @@ static __fi void _HwWrite_16or32_Page1( u32 addr, T val )
mcase(HW_IREG):
psxHu(addr) &= val;
if ((val == 0xffffffff) ) {
psxHu32(addr) |= 1 << 2;
psxHu32(addr) |= 1 << 3;
}
break;
mcase(HW_IREG+2):
@ -342,16 +363,18 @@ static __fi void _HwWrite_16or32_Page1( u32 addr, T val )
// ------------------------------------------------------------------------
//
mcase(0x1f801088) : // DMA0 CHCR -- MDEC IN [ignored]
//DmaExec(0);
DevCon.Warning("MDEC IN (DMA0) Started"); //Can be disabled later, need to see when this is used.
HW_DMA0_CHCR &= ~0x01000000;
mcase(0x1f801088) : // DMA0 CHCR -- MDEC IN
// psx mode
HW_DMA0_CHCR = val;
//Console.WriteLn("MDEC WR DMA0 %08X = %08X", addr, val);
psxDma0(HW_DMA0_MADR, HW_DMA0_BCR, HW_DMA0_CHCR);
break;
mcase(0x1f801098): // DMA1 CHCR -- MDEC OUT [ignored]
//DmaExec(1);
DevCon.Warning("MDEC IN (DMA1) Started"); //Can be disabled later, need to see when this is used.
HW_DMA1_CHCR &= ~0x01000000;
mcase(0x1f801098): // DMA1 CHCR -- MDEC OUT
// psx mode
HW_DMA1_CHCR = val;
//Console.WriteLn("MDEC WR DMA1 %08X = %08X", addr, val);
psxDma1(HW_DMA1_MADR, HW_DMA1_BCR, HW_DMA1_CHCR);
break;
mcase(0x1f8010ac):
DevCon.Warning("SIF2 IOP TADR?? write");
@ -359,6 +382,7 @@ static __fi void _HwWrite_16or32_Page1( u32 addr, T val )
break;
mcase(0x1f8010a8) : // DMA2 CHCR -- GPU [ignored]
// todo: psx mode: Original mod doesn't do "psxHu(addr) = val;"
psxHu(addr) = val;
DmaExec(2);
break;
@ -511,103 +535,20 @@ static __fi void _HwWrite_16or32_Page1( u32 addr, T val )
//
mcase(HW_PS1_GPU_DATA) :
DevCon.Warning("GPUDATA Write %x", val);
/*if (val == 0x00000000)
{
psxHu32(HW_PS1_GPU_STATUS) = 0x14802000;
}
else if (val == 0x01000000)
{
DevCon.Warning("GP0 FIFO Clear");
sif2.fifo.clear();
}
else
{*/
psxHu(HW_PS1_GPU_DATA) = val; // guess
WriteFifoSingleWord();
//}
//GPU_writeData(value); // really old code from PCSX? (rama)
break;
psxGPUw(addr, val);
break;
mcase (HW_PS1_GPU_STATUS):
DevCon.Warning("GPUSTATUS Write Command %x Param %x", (u32)val >> 24, val & 0xffffff);
//psxHu(addr) = val; // guess
//psxHu(HW_PS1_GPU_STATUS) = val;
//WriteFifoSingleWord();
// psxHu(HW_PS1_GPU_DATA) = val; // guess
// WriteFifoSingleWord();
/*if (val == 0) //Reset
{
psxHu32(HW_PS1_GPU_STATUS) = 0x14802000;
}
else if (val == 0x10000007) //Get GPU version
{
//DevCon.Warning("Get Version");
psxHu(HW_PS1_GPU_DATA) = 2;
}
else if ((val & 0xff000000) == 0x04000000)
{
//psxHu32(HW_PS1_GPU_STATUS) = psxHu32(HW_PS1_GPU_STATUS) &= ~0x60000000;
psxHu32(HW_PS1_GPU_STATUS) |= (val & 0x3) << 29;
switch (val & 0x3)
{
case 0x0:
//DevCon.Warning("Set DMA Mode OFF");
psxHu32(HW_PS1_GPU_STATUS) &= ~0x2000000;
break;
case 0x1:
//DevCon.Warning("Set DMA Mode FIFO");
psxHu32(HW_PS1_GPU_STATUS) |= 0x2000000;
break;
case 0x2:
//DevCon.Warning("Set DMA Mode CPU->GPU");
psxHu32(HW_PS1_GPU_STATUS) = (psxHu32(HW_PS1_GPU_STATUS) & ~0x2000000) | ((psxHu32(HW_PS1_GPU_STATUS) & 0x10000000) >> 3);
break;
case 0x3:
//DevCon.Warning("Set DMA Mode GPUREAD->CPU");
psxHu32(HW_PS1_GPU_STATUS) = (psxHu32(HW_PS1_GPU_STATUS) & ~0x2000000) | ((psxHu32(HW_PS1_GPU_STATUS) & 0x8000000) >> 2);
break;
}
}
else if (val == 0x03000000)
{
// DevCon.Warning("Turn Display on");
psxHu32(HW_PS1_GPU_STATUS) &= ~(1 << 23);
}
else if ((val & 0xff000000) == 0x05000000)
{
DevCon.Warning("Start display area");
//psxHu32(HW_PS1_GPU_STATUS) |= 0x80000000;
//psxHu32(HW_PS1_GPU_STATUS) &= ~(1 << 26);
}
else if ((val & 0xff000000) == 0x08000000)
{
//DevCon.Warning("Display Mode");
psxHu32(HW_PS1_GPU_STATUS) &= ~0x7F4000;
psxHu32(HW_PS1_GPU_STATUS) |= (u32)(val & 0x3f) << 17;
psxHu32(HW_PS1_GPU_STATUS) |= (u32)(val & 0x40) << 10;
psxHu32(HW_PS1_GPU_STATUS) |= (u32)(val & 0x80) << 7;
//psxHu32(HW_PS1_GPU_STATUS) |= 0x80000000;
//psxHu32(HW_PS1_GPU_STATUS) &= ~(1 << 26);
}
else
{
//DevCon.Warning("Unknown GP1 Command");
}*/
//GPU_writeStatus(value); // really old code from PCSX? (rama)
break;
psxGPUw(addr, val);
psxHu(addr) = val; // guess
break;
mcase (0x1f801820): // MDEC
DevCon.Warning("MDEX 1820 Write %x", val);
psxHu(addr) = val; // guess
//mdecWrite0(value); // really old code from PCSX? (rama)
break;
mdecWrite0(val);
break;
mcase (0x1f801824): // MDEC
DevCon.Warning("MDEX 1824 Write %x", val);
psxHu(addr) = val; // guess
//mdecWrite1(value); // really old code from PCSX? (rama)
break;
mdecWrite1(val);
break;
// ------------------------------------------------------------------------