mirror of https://github.com/PCSX2/pcsx2.git
psxmode:IOP: plug in hardware read / write handlers for PGIF and MDEC
v2: * Update sioRead8() to read a single byte and add a comment on it * Better code integration IOP REG v3: * only log the bad 16 bit access
This commit is contained in:
Robert
Gregory Hainaut
parent
35fa20d965
commit
4047e34050
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@ -18,12 +18,14 @@
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#include "IopMem.h"
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static const u32
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HW_USB_START = 0x1f801600,
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HW_USB_END = 0x1f801700,
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HW_FW_START = 0x1f808400,
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HW_FW_END = 0x1f808550, // end addr for FW is a guess...
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HW_SPU2_START = 0x1f801c00,
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HW_SPU2_END = 0x1f801e00;
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HW_PS1_GPU_START = 0x1F8010A0,
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HW_PS1_GPU_END = 0x1F8010B0,
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HW_USB_START = 0x1f801600,
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HW_USB_END = 0x1f801700,
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HW_FW_START = 0x1f808400,
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HW_FW_END = 0x1f808550, // end addr for FW is a guess...
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HW_SPU2_START = 0x1f801c00,
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HW_SPU2_END = 0x1f801e00;
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static const u32
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HW_SSBUS_SPD_ADDR = 0x1f801000,
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@ -20,6 +20,9 @@
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#include "Sio.h"
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#include "CDVD/CdRom.h"
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#include "ps2/pgif.h"
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#include "Mdec.h"
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namespace IopMemory
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{
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using namespace Internal;
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@ -36,7 +39,12 @@ mem8_t __fastcall iopHwRead8_Page1( u32 addr )
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mem8_t ret; // using a return var can be helpful in debugging.
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switch( masked_addr )
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{
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mcase(HW_SIO_DATA): ret = sioRead8(); break;
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mcase(HW_SIO_DATA) :
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// 1F801040h 1/4 JOY_DATA Joypad/Memory Card Data (R/W)
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// psxmode: documentation suggests a valid 8 bit read and the rest of the 32 bit register is unclear.
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// todo: check this and compare with the HW_SIO_DATA read around line 245 as well.
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ret = sioRead8();
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break;
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// for use of serial port ignore for now
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//case 0x50: ret = serial_read8(); break;
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@ -85,7 +93,8 @@ mem8_t __fastcall iopHwRead8_Page3( u32 addr )
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mem8_t ret;
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if( addr == 0x1f803100 ) // PS/EE/IOP conf related
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ret = 0x10; // Dram 2M
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//ret = 0x10; // Dram 2M
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ret = 0xFF; //all high bus is the corect default state for CEX PS2!
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else
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ret = psxHu8( addr );
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@ -110,7 +119,6 @@ mem8_t __fastcall iopHwRead8_Page8( u32 addr )
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IopHwTraceLog<mem8_t>( addr, ret, true );
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return ret;
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}
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//////////////////////////////////////////////////////////////////////////////////////////
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//
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template< typename T >
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@ -126,7 +134,7 @@ static __fi T _HwRead_16or32_Page1( u32 addr )
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);
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u32 masked_addr = pgmsk( addr );
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T ret;
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T ret = 0;
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// ------------------------------------------------------------------------
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// Counters, 16-bit varieties!
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@ -216,10 +224,23 @@ static __fi T _HwRead_16or32_Page1( u32 addr )
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ret = SPU2read( addr );
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else
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{
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DbgCon.Warning( "HwRead32 from SPU2? @ 0x%08X .. What manner of trickery is this?!", addr );
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DevCon.Warning( "HwRead32 from SPU2? @ 0x%08X .. What manner of trickery is this?!", addr );
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ret = psxHu32(addr);
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}
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}
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// ------------------------------------------------------------------------
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// PS1 GPU access
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//
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else if( (masked_addr >= pgmsk(HW_PS1_GPU_START)) && (masked_addr < pgmsk(HW_PS1_GPU_END)) )
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{
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// todo: psx mode: this is new
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if( sizeof(T) == 2 )
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DevCon.Warning( "HwRead16 from PS1 GPU? @ 0x%08X .. What manner of trickery is this?!", addr );
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pxAssert(sizeof(T) == 4);
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ret = psxDma2GpuR(addr);
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}
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else
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{
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switch( masked_addr )
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@ -237,6 +258,8 @@ static __fi T _HwRead_16or32_Page1( u32 addr )
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mcase(HW_SIO_STAT):
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ret = sio.StatReg;
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sioStatRead();
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// Console.WriteLn( "SIO0 Read STAT %02X INT_STAT= %08X IOPpc= %08X " , ret, psxHu32(0x1070), psxRegs.pc);
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break;
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mcase(HW_SIO_MODE):
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@ -301,51 +324,26 @@ static __fi T _HwRead_16or32_Page1( u32 addr )
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break;
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mcase(HW_PS1_GPU_DATA) :
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ret = psxHu32(addr);
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ret = psxGPUr(addr);
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//ret = psxHu32(addr); // old
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DevCon.Warning("GPU Data Read %x", ret);
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break;
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mcase(HW_PS1_GPU_STATUS) :
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//ret = psxHu32(addr);
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/*if (sif2.fifo.size == 0x8) psxHu32(0x1f801814) &= ~(3 << 25);
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else psxHu32(0x1f801814) |= (3 << 25);*/
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/*switch ((psxHu32(HW_PS1_GPU_STATUS) >> 29) & 0x3)
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{
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case 0x0:
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//DevCon.Warning("Set DMA Mode OFF");
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psxHu32(HW_PS1_GPU_STATUS) &= ~0x2000000;
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break;
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case 0x1:
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//DevCon.Warning("Set DMA Mode FIFO");
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psxHu32(HW_PS1_GPU_STATUS) |= 0x2000000;
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break;
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case 0x2:
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//DevCon.Warning("Set DMA Mode CPU->GPU");
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psxHu32(HW_PS1_GPU_STATUS) = (psxHu32(HW_PS1_GPU_STATUS) & ~0x2000000) | ((psxHu32(HW_PS1_GPU_STATUS) & 0x10000000) >> 3);
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break;
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case 0x3:
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//DevCon.Warning("Set DMA Mode GPUREAD->CPU");
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psxHu32(HW_PS1_GPU_STATUS) = (psxHu32(HW_PS1_GPU_STATUS) & ~0x2000000) | ((psxHu32(HW_PS1_GPU_STATUS) & 0x8000000) >> 2);
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break;
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}*/
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ret = psxHu32(addr); //Idle & Ready to recieve command.
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//psxHu32(addr) = psHu32(0x1000f300);
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#if PSX_EXTRALOGS
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DevCon.Warning("GPU Status Read %x Sif fifo size %x", ret, sif2.fifo.size);
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#endif
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//ret = -1; // fake alive GPU :p
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ret = psxGPUr(addr);
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break;
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mcase (0x1f801820): // MDEC
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ret = psxHu32(addr);
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// ret = psxHu32(addr); // old
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ret = mdecRead0();
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#if PSX_EXTRALOGS
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DevCon.Warning("MDEC 1820 Read %x", ret);
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#endif
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break;
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mcase (0x1f801824): // MDEC
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ret = psxHu32(addr);
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//ret = psxHu32(addr); // old
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ret = mdecRead1();
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#if PSX_EXTRALOGS
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DevCon.Warning("MDEC 1824 Read %x", ret);
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#endif
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@ -461,12 +459,15 @@ mem32_t __fastcall iopHwRead32_Page8( u32 addr )
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// 4-byte FIFO input?
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// The old IOP system just ignored it, so that's what we do here. I've included commented code
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// for treating it as a 16/32 bit write though [which is what the SIO does, for example).
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mcase(HW_SIO2_FIFO):
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mcase(HW_SIO2_FIFO) :
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//ret = sio2_fifoOut();
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//ret |= sio2_fifoOut() << 8;
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//ret |= sio2_fifoOut() << 16;
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//ret |= sio2_fifoOut() << 24;
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//break;
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DevCon.Warning("HW_SIO2_FIFO read");
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ret = psxHu32(addr);
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break;
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default:
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ret = psxHu32(addr);
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@ -19,6 +19,9 @@
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#include "Sio.h"
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#include "CDVD/CdRom.h"
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#include "ps2/pgif.h"
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#include "Mdec.h"
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namespace IopMemory {
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using namespace Internal;
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@ -248,6 +251,19 @@ static __fi void _HwWrite_16or32_Page1( u32 addr, T val )
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//psxHu(addr) = val;
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}
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}
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// ------------------------------------------------------------------------
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// PS1 GPU access
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//
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else if( (masked_addr >= pgmsk(HW_PS1_GPU_START)) && (masked_addr < pgmsk(HW_PS1_GPU_END)) )
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{
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// todo: psx mode: this is new
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if( sizeof(T) == 2 )
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DevCon.Warning( "HwWrite16 to PS1 GPU? @ 0x%08X .. What manner of trickery is this?!", addr );
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pxAssert(sizeof(T) == 4);
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psxDma2GpuW(addr, val);
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}
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else
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{
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switch( masked_addr )
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@ -279,7 +295,8 @@ static __fi void _HwWrite_16or32_Page1( u32 addr, T val )
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break;
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mcase(HW_SIO_CTRL):
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sio.CtrlReg = (u16)val;
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//sio.CtrlReg = (u16)val;
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sioWriteCtrl16((u16)val);
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break;
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mcase(HW_SIO_BAUD):
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@ -295,6 +312,10 @@ static __fi void _HwWrite_16or32_Page1( u32 addr, T val )
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mcase(HW_IREG):
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psxHu(addr) &= val;
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if ((val == 0xffffffff) ) {
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psxHu32(addr) |= 1 << 2;
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psxHu32(addr) |= 1 << 3;
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}
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break;
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mcase(HW_IREG+2):
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@ -342,16 +363,18 @@ static __fi void _HwWrite_16or32_Page1( u32 addr, T val )
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// ------------------------------------------------------------------------
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//
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mcase(0x1f801088) : // DMA0 CHCR -- MDEC IN [ignored]
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//DmaExec(0);
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DevCon.Warning("MDEC IN (DMA0) Started"); //Can be disabled later, need to see when this is used.
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HW_DMA0_CHCR &= ~0x01000000;
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mcase(0x1f801088) : // DMA0 CHCR -- MDEC IN
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// psx mode
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HW_DMA0_CHCR = val;
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//Console.WriteLn("MDEC WR DMA0 %08X = %08X", addr, val);
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psxDma0(HW_DMA0_MADR, HW_DMA0_BCR, HW_DMA0_CHCR);
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break;
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mcase(0x1f801098): // DMA1 CHCR -- MDEC OUT [ignored]
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//DmaExec(1);
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DevCon.Warning("MDEC IN (DMA1) Started"); //Can be disabled later, need to see when this is used.
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HW_DMA1_CHCR &= ~0x01000000;
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mcase(0x1f801098): // DMA1 CHCR -- MDEC OUT
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// psx mode
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HW_DMA1_CHCR = val;
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//Console.WriteLn("MDEC WR DMA1 %08X = %08X", addr, val);
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psxDma1(HW_DMA1_MADR, HW_DMA1_BCR, HW_DMA1_CHCR);
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break;
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mcase(0x1f8010ac):
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DevCon.Warning("SIF2 IOP TADR?? write");
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@ -359,6 +382,7 @@ static __fi void _HwWrite_16or32_Page1( u32 addr, T val )
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break;
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mcase(0x1f8010a8) : // DMA2 CHCR -- GPU [ignored]
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// todo: psx mode: Original mod doesn't do "psxHu(addr) = val;"
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psxHu(addr) = val;
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DmaExec(2);
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break;
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@ -511,103 +535,20 @@ static __fi void _HwWrite_16or32_Page1( u32 addr, T val )
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//
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mcase(HW_PS1_GPU_DATA) :
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DevCon.Warning("GPUDATA Write %x", val);
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/*if (val == 0x00000000)
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{
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psxHu32(HW_PS1_GPU_STATUS) = 0x14802000;
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}
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else if (val == 0x01000000)
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{
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DevCon.Warning("GP0 FIFO Clear");
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sif2.fifo.clear();
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}
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else
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{*/
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psxHu(HW_PS1_GPU_DATA) = val; // guess
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WriteFifoSingleWord();
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//}
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//GPU_writeData(value); // really old code from PCSX? (rama)
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break;
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psxGPUw(addr, val);
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break;
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mcase (HW_PS1_GPU_STATUS):
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DevCon.Warning("GPUSTATUS Write Command %x Param %x", (u32)val >> 24, val & 0xffffff);
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//psxHu(addr) = val; // guess
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//psxHu(HW_PS1_GPU_STATUS) = val;
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//WriteFifoSingleWord();
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// psxHu(HW_PS1_GPU_DATA) = val; // guess
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// WriteFifoSingleWord();
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/*if (val == 0) //Reset
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{
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psxHu32(HW_PS1_GPU_STATUS) = 0x14802000;
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}
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else if (val == 0x10000007) //Get GPU version
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{
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//DevCon.Warning("Get Version");
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psxHu(HW_PS1_GPU_DATA) = 2;
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}
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else if ((val & 0xff000000) == 0x04000000)
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{
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//psxHu32(HW_PS1_GPU_STATUS) = psxHu32(HW_PS1_GPU_STATUS) &= ~0x60000000;
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psxHu32(HW_PS1_GPU_STATUS) |= (val & 0x3) << 29;
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switch (val & 0x3)
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{
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case 0x0:
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//DevCon.Warning("Set DMA Mode OFF");
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psxHu32(HW_PS1_GPU_STATUS) &= ~0x2000000;
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break;
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case 0x1:
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//DevCon.Warning("Set DMA Mode FIFO");
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psxHu32(HW_PS1_GPU_STATUS) |= 0x2000000;
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break;
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case 0x2:
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//DevCon.Warning("Set DMA Mode CPU->GPU");
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psxHu32(HW_PS1_GPU_STATUS) = (psxHu32(HW_PS1_GPU_STATUS) & ~0x2000000) | ((psxHu32(HW_PS1_GPU_STATUS) & 0x10000000) >> 3);
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break;
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case 0x3:
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//DevCon.Warning("Set DMA Mode GPUREAD->CPU");
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psxHu32(HW_PS1_GPU_STATUS) = (psxHu32(HW_PS1_GPU_STATUS) & ~0x2000000) | ((psxHu32(HW_PS1_GPU_STATUS) & 0x8000000) >> 2);
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break;
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}
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}
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else if (val == 0x03000000)
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{
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// DevCon.Warning("Turn Display on");
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psxHu32(HW_PS1_GPU_STATUS) &= ~(1 << 23);
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}
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else if ((val & 0xff000000) == 0x05000000)
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{
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DevCon.Warning("Start display area");
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//psxHu32(HW_PS1_GPU_STATUS) |= 0x80000000;
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//psxHu32(HW_PS1_GPU_STATUS) &= ~(1 << 26);
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}
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else if ((val & 0xff000000) == 0x08000000)
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{
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//DevCon.Warning("Display Mode");
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psxHu32(HW_PS1_GPU_STATUS) &= ~0x7F4000;
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psxHu32(HW_PS1_GPU_STATUS) |= (u32)(val & 0x3f) << 17;
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psxHu32(HW_PS1_GPU_STATUS) |= (u32)(val & 0x40) << 10;
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psxHu32(HW_PS1_GPU_STATUS) |= (u32)(val & 0x80) << 7;
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//psxHu32(HW_PS1_GPU_STATUS) |= 0x80000000;
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//psxHu32(HW_PS1_GPU_STATUS) &= ~(1 << 26);
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}
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else
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{
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//DevCon.Warning("Unknown GP1 Command");
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}*/
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//GPU_writeStatus(value); // really old code from PCSX? (rama)
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break;
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psxGPUw(addr, val);
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psxHu(addr) = val; // guess
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break;
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mcase (0x1f801820): // MDEC
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DevCon.Warning("MDEX 1820 Write %x", val);
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psxHu(addr) = val; // guess
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//mdecWrite0(value); // really old code from PCSX? (rama)
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break;
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mdecWrite0(val);
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break;
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mcase (0x1f801824): // MDEC
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DevCon.Warning("MDEX 1824 Write %x", val);
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psxHu(addr) = val; // guess
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//mdecWrite1(value); // really old code from PCSX? (rama)
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break;
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mdecWrite1(val);
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break;
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// ------------------------------------------------------------------------
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